2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #include "qemu/osdep.h"
29 #include "qapi/error.h"
30 #include "qemu-common.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/boards.h"
34 #include "hw/loader.h"
36 #include "exec/memory.h"
37 #include "exec/address-spaces.h"
38 #include "hw/char/serial.h"
40 #include "hw/sysbus.h"
41 #include "hw/block/flash.h"
42 #include "sysemu/block-backend.h"
43 #include "chardev/char.h"
44 #include "sysemu/device_tree.h"
45 #include "qemu/error-report.h"
46 #include "bootparam.h"
48 typedef struct LxBoardDesc
{
51 size_t flash_boot_base
;
52 size_t flash_sector_size
;
56 typedef struct Lx60FpgaState
{
62 static void lx60_fpga_reset(void *opaque
)
64 Lx60FpgaState
*s
= opaque
;
70 static uint64_t lx60_fpga_read(void *opaque
, hwaddr addr
,
73 Lx60FpgaState
*s
= opaque
;
76 case 0x0: /*build date code*/
79 case 0x4: /*processor clock frequency, Hz*/
82 case 0x8: /*LEDs (off = 0, on = 1)*/
85 case 0xc: /*DIP switches (off = 0, on = 1)*/
91 static void lx60_fpga_write(void *opaque
, hwaddr addr
,
92 uint64_t val
, unsigned size
)
94 Lx60FpgaState
*s
= opaque
;
97 case 0x8: /*LEDs (off = 0, on = 1)*/
101 case 0x10: /*board reset*/
103 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
109 static const MemoryRegionOps lx60_fpga_ops
= {
110 .read
= lx60_fpga_read
,
111 .write
= lx60_fpga_write
,
112 .endianness
= DEVICE_NATIVE_ENDIAN
,
115 static Lx60FpgaState
*lx60_fpga_init(MemoryRegion
*address_space
,
118 Lx60FpgaState
*s
= g_malloc(sizeof(Lx60FpgaState
));
120 memory_region_init_io(&s
->iomem
, NULL
, &lx60_fpga_ops
, s
,
121 "lx60.fpga", 0x10000);
122 memory_region_add_subregion(address_space
, base
, &s
->iomem
);
124 qemu_register_reset(lx60_fpga_reset
, s
);
128 static void lx60_net_init(MemoryRegion
*address_space
,
132 qemu_irq irq
, NICInfo
*nd
)
138 dev
= qdev_create(NULL
, "open_eth");
139 qdev_set_nic_properties(dev
, nd
);
140 qdev_init_nofail(dev
);
142 s
= SYS_BUS_DEVICE(dev
);
143 sysbus_connect_irq(s
, 0, irq
);
144 memory_region_add_subregion(address_space
, base
,
145 sysbus_mmio_get_region(s
, 0));
146 memory_region_add_subregion(address_space
, descriptors
,
147 sysbus_mmio_get_region(s
, 1));
149 ram
= g_malloc(sizeof(*ram
));
150 memory_region_init_ram_nomigrate(ram
, OBJECT(s
), "open_eth.ram", 16384,
152 vmstate_register_ram_global(ram
);
153 memory_region_add_subregion(address_space
, buffers
, ram
);
156 static pflash_t
*xtfpga_flash_init(MemoryRegion
*address_space
,
157 const LxBoardDesc
*board
,
158 DriveInfo
*dinfo
, int be
)
161 DeviceState
*dev
= qdev_create(NULL
, "cfi.pflash01");
163 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
165 qdev_prop_set_uint32(dev
, "num-blocks",
166 board
->flash_size
/ board
->flash_sector_size
);
167 qdev_prop_set_uint64(dev
, "sector-length", board
->flash_sector_size
);
168 qdev_prop_set_uint8(dev
, "width", 2);
169 qdev_prop_set_bit(dev
, "big-endian", be
);
170 qdev_prop_set_string(dev
, "name", "lx60.io.flash");
171 qdev_init_nofail(dev
);
172 s
= SYS_BUS_DEVICE(dev
);
173 memory_region_add_subregion(address_space
, board
->flash_base
,
174 sysbus_mmio_get_region(s
, 0));
175 return OBJECT_CHECK(pflash_t
, (dev
), "cfi.pflash01");
178 static uint64_t translate_phys_addr(void *opaque
, uint64_t addr
)
180 XtensaCPU
*cpu
= opaque
;
182 return cpu_get_phys_page_debug(CPU(cpu
), addr
);
185 static void lx60_reset(void *opaque
)
187 XtensaCPU
*cpu
= opaque
;
192 static uint64_t lx60_io_read(void *opaque
, hwaddr addr
,
198 static void lx60_io_write(void *opaque
, hwaddr addr
,
199 uint64_t val
, unsigned size
)
203 static const MemoryRegionOps lx60_io_ops
= {
204 .read
= lx60_io_read
,
205 .write
= lx60_io_write
,
206 .endianness
= DEVICE_NATIVE_ENDIAN
,
209 static void lx_init(const LxBoardDesc
*board
, MachineState
*machine
)
211 #ifdef TARGET_WORDS_BIGENDIAN
216 MemoryRegion
*system_memory
= get_system_memory();
217 XtensaCPU
*cpu
= NULL
;
218 CPUXtensaState
*env
= NULL
;
219 MemoryRegion
*ram
, *rom
, *system_io
;
221 pflash_t
*flash
= NULL
;
222 QemuOpts
*machine_opts
= qemu_get_machine_opts();
223 const char *cpu_model
= machine
->cpu_model
;
224 const char *kernel_filename
= qemu_opt_get(machine_opts
, "kernel");
225 const char *kernel_cmdline
= qemu_opt_get(machine_opts
, "append");
226 const char *dtb_filename
= qemu_opt_get(machine_opts
, "dtb");
227 const char *initrd_filename
= qemu_opt_get(machine_opts
, "initrd");
231 cpu_model
= XTENSA_DEFAULT_CPU_MODEL
;
234 for (n
= 0; n
< smp_cpus
; n
++) {
235 cpu
= XTENSA_CPU(cpu_generic_init(TYPE_XTENSA_CPU
, cpu_model
));
237 error_report("unable to find CPU definition '%s'",
243 env
->sregs
[PRID
] = n
;
244 qemu_register_reset(lx60_reset
, cpu
);
245 /* Need MMU initialized prior to ELF loading,
246 * so that ELF gets loaded into virtual addresses
251 ram
= g_malloc(sizeof(*ram
));
252 memory_region_init_ram(ram
, NULL
, "lx60.dram", machine
->ram_size
,
254 memory_region_add_subregion(system_memory
, 0, ram
);
256 system_io
= g_malloc(sizeof(*system_io
));
257 memory_region_init_io(system_io
, NULL
, &lx60_io_ops
, NULL
, "lx60.io",
259 memory_region_add_subregion(system_memory
, 0xf0000000, system_io
);
260 lx60_fpga_init(system_io
, 0x0d020000);
261 if (nd_table
[0].used
) {
262 lx60_net_init(system_io
, 0x0d030000, 0x0d030400, 0x0d800000,
263 xtensa_get_extint(env
, 1), nd_table
);
266 if (!serial_hds
[0]) {
267 serial_hds
[0] = qemu_chr_new("serial0", "null");
270 serial_mm_init(system_io
, 0x0d050020, 2, xtensa_get_extint(env
, 0),
271 115200, serial_hds
[0], DEVICE_NATIVE_ENDIAN
);
273 dinfo
= drive_get(IF_PFLASH
, 0, 0);
275 flash
= xtfpga_flash_init(system_io
, board
, dinfo
, be
);
278 /* Use presence of kernel file name as 'boot from SRAM' switch. */
279 if (kernel_filename
) {
280 uint32_t entry_point
= env
->pc
;
281 size_t bp_size
= 3 * get_tag_size(0); /* first/last and memory tags */
282 uint32_t tagptr
= 0xfe000000 + board
->sram_size
;
284 BpMemInfo memory_location
= {
285 .type
= tswap32(MEMORY_TYPE_CONVENTIONAL
),
287 .end
= tswap32(machine
->ram_size
),
289 uint32_t lowmem_end
= machine
->ram_size
< 0x08000000 ?
290 machine
->ram_size
: 0x08000000;
291 uint32_t cur_lowmem
= QEMU_ALIGN_UP(lowmem_end
/ 2, 4096);
293 rom
= g_malloc(sizeof(*rom
));
294 memory_region_init_ram(rom
, NULL
, "lx60.sram", board
->sram_size
,
296 memory_region_add_subregion(system_memory
, 0xfe000000, rom
);
298 if (kernel_cmdline
) {
299 bp_size
+= get_tag_size(strlen(kernel_cmdline
) + 1);
302 bp_size
+= get_tag_size(sizeof(uint32_t));
304 if (initrd_filename
) {
305 bp_size
+= get_tag_size(sizeof(BpMemInfo
));
308 /* Put kernel bootparameters to the end of that SRAM */
309 tagptr
= (tagptr
- bp_size
) & ~0xff;
310 cur_tagptr
= put_tag(tagptr
, BP_TAG_FIRST
, 0, NULL
);
311 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_MEMORY
,
312 sizeof(memory_location
), &memory_location
);
314 if (kernel_cmdline
) {
315 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_COMMAND_LINE
,
316 strlen(kernel_cmdline
) + 1, kernel_cmdline
);
321 void *fdt
= load_device_tree(dtb_filename
, &fdt_size
);
322 uint32_t dtb_addr
= tswap32(cur_lowmem
);
325 error_report("could not load DTB '%s'", dtb_filename
);
329 cpu_physical_memory_write(cur_lowmem
, fdt
, fdt_size
);
330 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_FDT
,
331 sizeof(dtb_addr
), &dtb_addr
);
332 cur_lowmem
= QEMU_ALIGN_UP(cur_lowmem
+ fdt_size
, 4096);
336 error_report("could not load DTB '%s': "
337 "FDT support is not configured in QEMU",
342 if (initrd_filename
) {
343 BpMemInfo initrd_location
= { 0 };
344 int initrd_size
= load_ramdisk(initrd_filename
, cur_lowmem
,
345 lowmem_end
- cur_lowmem
);
347 if (initrd_size
< 0) {
348 initrd_size
= load_image_targphys(initrd_filename
,
350 lowmem_end
- cur_lowmem
);
352 if (initrd_size
< 0) {
353 error_report("could not load initrd '%s'", initrd_filename
);
356 initrd_location
.start
= tswap32(cur_lowmem
);
357 initrd_location
.end
= tswap32(cur_lowmem
+ initrd_size
);
358 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_INITRD
,
359 sizeof(initrd_location
), &initrd_location
);
360 cur_lowmem
= QEMU_ALIGN_UP(cur_lowmem
+ initrd_size
, 4096);
362 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_LAST
, 0, NULL
);
363 env
->regs
[2] = tagptr
;
366 uint64_t elf_lowaddr
;
367 int success
= load_elf(kernel_filename
, translate_phys_addr
, cpu
,
368 &elf_entry
, &elf_lowaddr
, NULL
, be
, EM_XTENSA
, 0, 0);
370 entry_point
= elf_entry
;
374 success
= load_uimage(kernel_filename
, &ep
, NULL
, &is_linux
,
375 translate_phys_addr
, cpu
);
376 if (success
> 0 && is_linux
) {
379 error_report("could not load kernel '%s'",
384 if (entry_point
!= env
->pc
) {
385 static const uint8_t jx_a0
[] = {
386 #ifdef TARGET_WORDS_BIGENDIAN
392 env
->regs
[0] = entry_point
;
393 cpu_physical_memory_write(env
->pc
, jx_a0
, sizeof(jx_a0
));
397 MemoryRegion
*flash_mr
= pflash_cfi01_get_memory(flash
);
398 MemoryRegion
*flash_io
= g_malloc(sizeof(*flash_io
));
400 memory_region_init_alias(flash_io
, NULL
, "lx60.flash",
401 flash_mr
, board
->flash_boot_base
,
402 board
->flash_size
- board
->flash_boot_base
< 0x02000000 ?
403 board
->flash_size
- board
->flash_boot_base
: 0x02000000);
404 memory_region_add_subregion(system_memory
, 0xfe000000,
410 static void xtensa_lx60_init(MachineState
*machine
)
412 static const LxBoardDesc lx60_board
= {
413 .flash_base
= 0x08000000,
414 .flash_size
= 0x00400000,
415 .flash_sector_size
= 0x10000,
416 .sram_size
= 0x20000,
418 lx_init(&lx60_board
, machine
);
421 static void xtensa_lx200_init(MachineState
*machine
)
423 static const LxBoardDesc lx200_board
= {
424 .flash_base
= 0x08000000,
425 .flash_size
= 0x01000000,
426 .flash_sector_size
= 0x20000,
427 .sram_size
= 0x2000000,
429 lx_init(&lx200_board
, machine
);
432 static void xtensa_ml605_init(MachineState
*machine
)
434 static const LxBoardDesc ml605_board
= {
435 .flash_base
= 0x08000000,
436 .flash_size
= 0x01000000,
437 .flash_sector_size
= 0x20000,
438 .sram_size
= 0x2000000,
440 lx_init(&ml605_board
, machine
);
443 static void xtensa_kc705_init(MachineState
*machine
)
445 static const LxBoardDesc kc705_board
= {
446 .flash_base
= 0x00000000,
447 .flash_size
= 0x08000000,
448 .flash_boot_base
= 0x06000000,
449 .flash_sector_size
= 0x20000,
450 .sram_size
= 0x2000000,
452 lx_init(&kc705_board
, machine
);
455 static void xtensa_lx60_class_init(ObjectClass
*oc
, void *data
)
457 MachineClass
*mc
= MACHINE_CLASS(oc
);
459 mc
->desc
= "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL
")";
460 mc
->init
= xtensa_lx60_init
;
464 static const TypeInfo xtensa_lx60_type
= {
465 .name
= MACHINE_TYPE_NAME("lx60"),
466 .parent
= TYPE_MACHINE
,
467 .class_init
= xtensa_lx60_class_init
,
470 static void xtensa_lx200_class_init(ObjectClass
*oc
, void *data
)
472 MachineClass
*mc
= MACHINE_CLASS(oc
);
474 mc
->desc
= "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL
")";
475 mc
->init
= xtensa_lx200_init
;
479 static const TypeInfo xtensa_lx200_type
= {
480 .name
= MACHINE_TYPE_NAME("lx200"),
481 .parent
= TYPE_MACHINE
,
482 .class_init
= xtensa_lx200_class_init
,
485 static void xtensa_ml605_class_init(ObjectClass
*oc
, void *data
)
487 MachineClass
*mc
= MACHINE_CLASS(oc
);
489 mc
->desc
= "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL
")";
490 mc
->init
= xtensa_ml605_init
;
494 static const TypeInfo xtensa_ml605_type
= {
495 .name
= MACHINE_TYPE_NAME("ml605"),
496 .parent
= TYPE_MACHINE
,
497 .class_init
= xtensa_ml605_class_init
,
500 static void xtensa_kc705_class_init(ObjectClass
*oc
, void *data
)
502 MachineClass
*mc
= MACHINE_CLASS(oc
);
504 mc
->desc
= "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL
")";
505 mc
->init
= xtensa_kc705_init
;
509 static const TypeInfo xtensa_kc705_type
= {
510 .name
= MACHINE_TYPE_NAME("kc705"),
511 .parent
= TYPE_MACHINE
,
512 .class_init
= xtensa_kc705_class_init
,
515 static void xtensa_lx_machines_init(void)
517 type_register_static(&xtensa_lx60_type
);
518 type_register_static(&xtensa_lx200_type
);
519 type_register_static(&xtensa_ml605_type
);
520 type_register_static(&xtensa_kc705_type
);
523 type_init(xtensa_lx_machines_init
)