hw/display/pl110.c

   1 /*
   2  * Arm PrimeCell PL110 Color LCD Controller
   3  *
   4  * Copyright (c) 2005-2009 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GNU LGPL
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/irq.h"
  12 #include "hw/sysbus.h"
  13 #include "migration/vmstate.h"
  14 #include "ui/console.h"
  15 #include "framebuffer.h"
  16 #include "ui/pixel_ops.h"
  17 #include "qemu/timer.h"
  18 #include "qemu/log.h"
  19 #include "qemu/module.h"
  20
  21 #define PL110_CR_EN   0x001
  22 #define PL110_CR_BGR  0x100
  23 #define PL110_CR_BEBO 0x200
  24 #define PL110_CR_BEPO 0x400
  25 #define PL110_CR_PWR  0x800
  26 #define PL110_IE_NB   0x004
  27 #define PL110_IE_VC   0x008
  28
  29 enum pl110_bppmode
  30 {
  31     BPP_1,
  32     BPP_2,
  33     BPP_4,
  34     BPP_8,
  35     BPP_16,
  36     BPP_32,
  37     BPP_16_565, /* PL111 only */
  38     BPP_12      /* PL111 only */
  39 };
  40
  41
  42 /* The Versatile/PB uses a slightly modified PL110 controller.  */
  43 enum pl110_version
  44 {
  45     PL110,
  46     PL110_VERSATILE,
  47     PL111
  48 };
  49
  50 #define TYPE_PL110 "pl110"
  51 #define PL110(obj) OBJECT_CHECK(PL110State, (obj), TYPE_PL110)
  52
  53 typedef struct PL110State {
  54     SysBusDevice parent_obj;
  55
  56     MemoryRegion iomem;
  57     MemoryRegionSection fbsection;
  58     QemuConsole *con;
  59     QEMUTimer *vblank_timer;
  60
  61     int version;
  62     uint32_t timing[4];
  63     uint32_t cr;
  64     uint32_t upbase;
  65     uint32_t lpbase;
  66     uint32_t int_status;
  67     uint32_t int_mask;
  68     int cols;
  69     int rows;
  70     enum pl110_bppmode bpp;
  71     int invalidate;
  72     uint32_t mux_ctrl;
  73     uint32_t palette[256];
  74     uint32_t raw_palette[128];
  75     qemu_irq irq;
  76 } PL110State;
  77
  78 static int vmstate_pl110_post_load(void *opaque, int version_id);
  79
  80 static const VMStateDescription vmstate_pl110 = {
  81     .name = "pl110",
  82     .version_id = 2,
  83     .minimum_version_id = 1,
  84     .post_load = vmstate_pl110_post_load,
  85     .fields = (VMStateField[]) {
  86         VMSTATE_INT32(version, PL110State),
  87         VMSTATE_UINT32_ARRAY(timing, PL110State, 4),
  88         VMSTATE_UINT32(cr, PL110State),
  89         VMSTATE_UINT32(upbase, PL110State),
  90         VMSTATE_UINT32(lpbase, PL110State),
  91         VMSTATE_UINT32(int_status, PL110State),
  92         VMSTATE_UINT32(int_mask, PL110State),
  93         VMSTATE_INT32(cols, PL110State),
  94         VMSTATE_INT32(rows, PL110State),
  95         VMSTATE_UINT32(bpp, PL110State),
  96         VMSTATE_INT32(invalidate, PL110State),
  97         VMSTATE_UINT32_ARRAY(palette, PL110State, 256),
  98         VMSTATE_UINT32_ARRAY(raw_palette, PL110State, 128),
  99         VMSTATE_UINT32_V(mux_ctrl, PL110State, 2),
 100         VMSTATE_END_OF_LIST()
 101     }
 102 };
 103
 104 static const unsigned char pl110_id[] =
 105 { 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
 106
 107 static const unsigned char pl111_id[] = {
 108     0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1
 109 };
 110
 111
 112 /* Indexed by pl110_version */
 113 static const unsigned char *idregs[] = {
 114     pl110_id,
 115     /* The ARM documentation (DDI0224C) says the CLCDC on the Versatile board
 116      * has a different ID (0x93, 0x10, 0x04, 0x00, ...). However the hardware
 117      * itself has the same ID values as a stock PL110, and guests (in
 118      * particular Linux) rely on this. We emulate what the hardware does,
 119      * rather than what the docs claim it ought to do.
 120      */
 121     pl110_id,
 122     pl111_id
 123 };
 124
 125 #define BITS 8
 126 #include "pl110_template.h"
 127 #define BITS 15
 128 #include "pl110_template.h"
 129 #define BITS 16
 130 #include "pl110_template.h"
 131 #define BITS 24
 132 #include "pl110_template.h"
 133 #define BITS 32
 134 #include "pl110_template.h"
 135
 136 static int pl110_enabled(PL110State *s)
 137 {
 138   return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
 139 }
 140
 141 static void pl110_update_display(void *opaque)
 142 {
 143     PL110State *s = (PL110State *)opaque;
 144     SysBusDevice *sbd;
 145     DisplaySurface *surface = qemu_console_surface(s->con);
 146     drawfn* fntable;
 147     drawfn fn;
 148     int dest_width;
 149     int src_width;
 150     int bpp_offset;
 151     int first;
 152     int last;
 153
 154     if (!pl110_enabled(s)) {
 155         return;
 156     }
 157
 158     sbd = SYS_BUS_DEVICE(s);
 159
 160     switch (surface_bits_per_pixel(surface)) {
 161     case 0:
 162         return;
 163     case 8:
 164         fntable = pl110_draw_fn_8;
 165         dest_width = 1;
 166         break;
 167     case 15:
 168         fntable = pl110_draw_fn_15;
 169         dest_width = 2;
 170         break;
 171     case 16:
 172         fntable = pl110_draw_fn_16;
 173         dest_width = 2;
 174         break;
 175     case 24:
 176         fntable = pl110_draw_fn_24;
 177         dest_width = 3;
 178         break;
 179     case 32:
 180         fntable = pl110_draw_fn_32;
 181         dest_width = 4;
 182         break;
 183     default:
 184         fprintf(stderr, "pl110: Bad color depth\n");
 185         exit(1);
 186     }
 187     if (s->cr & PL110_CR_BGR)
 188         bpp_offset = 0;
 189     else
 190         bpp_offset = 24;
 191
 192     if ((s->version != PL111) && (s->bpp == BPP_16)) {
 193         /* The PL110's native 16 bit mode is 5551; however
 194          * most boards with a PL110 implement an external
 195          * mux which allows bits to be reshuffled to give
 196          * 565 format. The mux is typically controlled by
 197          * an external system register.
 198          * This is controlled by a GPIO input pin
 199          * so boards can wire it up to their register.
 200          *
 201          * The PL111 straightforwardly implements both
 202          * 5551 and 565 under control of the bpp field
 203          * in the LCDControl register.
 204          */
 205         switch (s->mux_ctrl) {
 206         case 3: /* 565 BGR */
 207             bpp_offset = (BPP_16_565 - BPP_16);
 208             break;
 209         case 1: /* 5551 */
 210             break;
 211         case 0: /* 888; also if we have loaded vmstate from an old version */
 212         case 2: /* 565 RGB */
 213         default:
 214             /* treat as 565 but honour BGR bit */
 215             bpp_offset += (BPP_16_565 - BPP_16);
 216             break;
 217         }
 218     }
 219
 220     if (s->cr & PL110_CR_BEBO)
 221         fn = fntable[s->bpp + 8 + bpp_offset];
 222     else if (s->cr & PL110_CR_BEPO)
 223         fn = fntable[s->bpp + 16 + bpp_offset];
 224     else
 225         fn = fntable[s->bpp + bpp_offset];
 226
 227     src_width = s->cols;
 228     switch (s->bpp) {
 229     case BPP_1:
 230         src_width >>= 3;
 231         break;
 232     case BPP_2:
 233         src_width >>= 2;
 234         break;
 235     case BPP_4:
 236         src_width >>= 1;
 237         break;
 238     case BPP_8:
 239         break;
 240     case BPP_16:
 241     case BPP_16_565:
 242     case BPP_12:
 243         src_width <<= 1;
 244         break;
 245     case BPP_32:
 246         src_width <<= 2;
 247         break;
 248     }
 249     dest_width *= s->cols;
 250     first = 0;
 251     if (s->invalidate) {
 252         framebuffer_update_memory_section(&s->fbsection,
 253                                           sysbus_address_space(sbd),
 254                                           s->upbase,
 255                                           s->rows, src_width);
 256     }
 257
 258     framebuffer_update_display(surface, &s->fbsection,
 259                                s->cols, s->rows,
 260                                src_width, dest_width, 0,
 261                                s->invalidate,
 262                                fn, s->palette,
 263                                &first, &last);
 264
 265     if (first >= 0) {
 266         dpy_gfx_update(s->con, 0, first, s->cols, last - first + 1);
 267     }
 268     s->invalidate = 0;
 269 }
 270
 271 static void pl110_invalidate_display(void * opaque)
 272 {
 273     PL110State *s = (PL110State *)opaque;
 274     s->invalidate = 1;
 275     if (pl110_enabled(s)) {
 276         qemu_console_resize(s->con, s->cols, s->rows);
 277     }
 278 }
 279
 280 static void pl110_update_palette(PL110State *s, int n)
 281 {
 282     DisplaySurface *surface = qemu_console_surface(s->con);
 283     int i;
 284     uint32_t raw;
 285     unsigned int r, g, b;
 286
 287     raw = s->raw_palette[n];
 288     n <<= 1;
 289     for (i = 0; i < 2; i++) {
 290         r = (raw & 0x1f) << 3;
 291         raw >>= 5;
 292         g = (raw & 0x1f) << 3;
 293         raw >>= 5;
 294         b = (raw & 0x1f) << 3;
 295         /* The I bit is ignored.  */
 296         raw >>= 6;
 297         switch (surface_bits_per_pixel(surface)) {
 298         case 8:
 299             s->palette[n] = rgb_to_pixel8(r, g, b);
 300             break;
 301         case 15:
 302             s->palette[n] = rgb_to_pixel15(r, g, b);
 303             break;
 304         case 16:
 305             s->palette[n] = rgb_to_pixel16(r, g, b);
 306             break;
 307         case 24:
 308         case 32:
 309             s->palette[n] = rgb_to_pixel32(r, g, b);
 310             break;
 311         }
 312         n++;
 313     }
 314 }
 315
 316 static void pl110_resize(PL110State *s, int width, int height)
 317 {
 318     if (width != s->cols || height != s->rows) {
 319         if (pl110_enabled(s)) {
 320             qemu_console_resize(s->con, width, height);
 321         }
 322     }
 323     s->cols = width;
 324     s->rows = height;
 325 }
 326
 327 /* Update interrupts.  */
 328 static void pl110_update(PL110State *s)
 329 {
 330     /* Raise IRQ if enabled and any status bit is 1 */
 331     if (s->int_status & s->int_mask) {
 332         qemu_irq_raise(s->irq);
 333     } else {
 334         qemu_irq_lower(s->irq);
 335     }
 336 }
 337
 338 static void pl110_vblank_interrupt(void *opaque)
 339 {
 340     PL110State *s = opaque;
 341
 342     /* Fire the vertical compare and next base IRQs and re-arm */
 343     s->int_status |= (PL110_IE_NB | PL110_IE_VC);
 344     timer_mod(s->vblank_timer,
 345               qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 346                                 NANOSECONDS_PER_SECOND / 60);
 347     pl110_update(s);
 348 }
 349
 350 static uint64_t pl110_read(void *opaque, hwaddr offset,
 351                            unsigned size)
 352 {
 353     PL110State *s = (PL110State *)opaque;
 354
 355     if (offset >= 0xfe0 && offset < 0x1000) {
 356         return idregs[s->version][(offset - 0xfe0) >> 2];
 357     }
 358     if (offset >= 0x200 && offset < 0x400) {
 359         return s->raw_palette[(offset - 0x200) >> 2];
 360     }
 361     switch (offset >> 2) {
 362     case 0: /* LCDTiming0 */
 363         return s->timing[0];
 364     case 1: /* LCDTiming1 */
 365         return s->timing[1];
 366     case 2: /* LCDTiming2 */
 367         return s->timing[2];
 368     case 3: /* LCDTiming3 */
 369         return s->timing[3];
 370     case 4: /* LCDUPBASE */
 371         return s->upbase;
 372     case 5: /* LCDLPBASE */
 373         return s->lpbase;
 374     case 6: /* LCDIMSC */
 375         if (s->version != PL110) {
 376             return s->cr;
 377         }
 378         return s->int_mask;
 379     case 7: /* LCDControl */
 380         if (s->version != PL110) {
 381             return s->int_mask;
 382         }
 383         return s->cr;
 384     case 8: /* LCDRIS */
 385         return s->int_status;
 386     case 9: /* LCDMIS */
 387         return s->int_status & s->int_mask;
 388     case 11: /* LCDUPCURR */
 389         /* TODO: Implement vertical refresh.  */
 390         return s->upbase;
 391     case 12: /* LCDLPCURR */
 392         return s->lpbase;
 393     default:
 394         qemu_log_mask(LOG_GUEST_ERROR,
 395                       "pl110_read: Bad offset %x\n", (int)offset);
 396         return 0;
 397     }
 398 }
 399
 400 static void pl110_write(void *opaque, hwaddr offset,
 401                         uint64_t val, unsigned size)
 402 {
 403     PL110State *s = (PL110State *)opaque;
 404     int n;
 405
 406     /* For simplicity invalidate the display whenever a control register
 407        is written to.  */
 408     s->invalidate = 1;
 409     if (offset >= 0x200 && offset < 0x400) {
 410         /* Palette.  */
 411         n = (offset - 0x200) >> 2;
 412         s->raw_palette[(offset - 0x200) >> 2] = val;
 413         pl110_update_palette(s, n);
 414         return;
 415     }
 416     switch (offset >> 2) {
 417     case 0: /* LCDTiming0 */
 418         s->timing[0] = val;
 419         n = ((val & 0xfc) + 4) * 4;
 420         pl110_resize(s, n, s->rows);
 421         break;
 422     case 1: /* LCDTiming1 */
 423         s->timing[1] = val;
 424         n = (val & 0x3ff) + 1;
 425         pl110_resize(s, s->cols, n);
 426         break;
 427     case 2: /* LCDTiming2 */
 428         s->timing[2] = val;
 429         break;
 430     case 3: /* LCDTiming3 */
 431         s->timing[3] = val;
 432         break;
 433     case 4: /* LCDUPBASE */
 434         s->upbase = val;
 435         break;
 436     case 5: /* LCDLPBASE */
 437         s->lpbase = val;
 438         break;
 439     case 6: /* LCDIMSC */
 440         if (s->version != PL110) {
 441             goto control;
 442         }
 443     imsc:
 444         s->int_mask = val;
 445         pl110_update(s);
 446         break;
 447     case 7: /* LCDControl */
 448         if (s->version != PL110) {
 449             goto imsc;
 450         }
 451     control:
 452         s->cr = val;
 453         s->bpp = (val >> 1) & 7;
 454         if (pl110_enabled(s)) {
 455             qemu_console_resize(s->con, s->cols, s->rows);
 456             timer_mod(s->vblank_timer,
 457                       qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 458                                         NANOSECONDS_PER_SECOND / 60);
 459         } else {
 460             timer_del(s->vblank_timer);
 461         }
 462         break;
 463     case 10: /* LCDICR */
 464         s->int_status &= ~val;
 465         pl110_update(s);
 466         break;
 467     default:
 468         qemu_log_mask(LOG_GUEST_ERROR,
 469                       "pl110_write: Bad offset %x\n", (int)offset);
 470     }
 471 }
 472
 473 static const MemoryRegionOps pl110_ops = {
 474     .read = pl110_read,
 475     .write = pl110_write,
 476     .endianness = DEVICE_NATIVE_ENDIAN,
 477 };
 478
 479 static void pl110_mux_ctrl_set(void *opaque, int line, int level)
 480 {
 481     PL110State *s = (PL110State *)opaque;
 482     s->mux_ctrl = level;
 483 }
 484
 485 static int vmstate_pl110_post_load(void *opaque, int version_id)
 486 {
 487     PL110State *s = opaque;
 488     /* Make sure we redraw, and at the right size */
 489     pl110_invalidate_display(s);
 490     return 0;
 491 }
 492
 493 static const GraphicHwOps pl110_gfx_ops = {
 494     .invalidate  = pl110_invalidate_display,
 495     .gfx_update  = pl110_update_display,
 496 };
 497
 498 static void pl110_realize(DeviceState *dev, Error **errp)
 499 {
 500     PL110State *s = PL110(dev);
 501     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 502
 503     memory_region_init_io(&s->iomem, OBJECT(s), &pl110_ops, s, "pl110", 0x1000);
 504     sysbus_init_mmio(sbd, &s->iomem);
 505     sysbus_init_irq(sbd, &s->irq);
 506     s->vblank_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 507                                    pl110_vblank_interrupt, s);
 508     qdev_init_gpio_in(dev, pl110_mux_ctrl_set, 1);
 509     s->con = graphic_console_init(dev, 0, &pl110_gfx_ops, s);
 510 }
 511
 512 static void pl110_init(Object *obj)
 513 {
 514     PL110State *s = PL110(obj);
 515
 516     s->version = PL110;
 517 }
 518
 519 static void pl110_versatile_init(Object *obj)
 520 {
 521     PL110State *s = PL110(obj);
 522
 523     s->version = PL110_VERSATILE;
 524 }
 525
 526 static void pl111_init(Object *obj)
 527 {
 528     PL110State *s = PL110(obj);
 529
 530     s->version = PL111;
 531 }
 532
 533 static void pl110_class_init(ObjectClass *klass, void *data)
 534 {
 535     DeviceClass *dc = DEVICE_CLASS(klass);
 536
 537     set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
 538     dc->vmsd = &vmstate_pl110;
 539     dc->realize = pl110_realize;
 540 }
 541
 542 static const TypeInfo pl110_info = {
 543     .name          = TYPE_PL110,
 544     .parent        = TYPE_SYS_BUS_DEVICE,
 545     .instance_size = sizeof(PL110State),
 546     .instance_init = pl110_init,
 547     .class_init    = pl110_class_init,
 548 };
 549
 550 static const TypeInfo pl110_versatile_info = {
 551     .name          = "pl110_versatile",
 552     .parent        = TYPE_PL110,
 553     .instance_init = pl110_versatile_init,
 554 };
 555
 556 static const TypeInfo pl111_info = {
 557     .name          = "pl111",
 558     .parent        = TYPE_PL110,
 559     .instance_init = pl111_init,
 560 };
 561
 562 static void pl110_register_types(void)
 563 {
 564     type_register_static(&pl110_info);
 565     type_register_static(&pl110_versatile_info);
 566     type_register_static(&pl111_info);
 567 }
 568
 569 type_init(pl110_register_types)