hw/scsi/mfi.h

   1 /*
   2  * NetBSD header file, copied from
   3  * http://gitorious.org/freebsd/freebsd/blobs/HEAD/sys/dev/mfi/mfireg.h
   4  */
   5 /*-
   6  * Copyright (c) 2006 IronPort Systems
   7  * Copyright (c) 2007 LSI Corp.
   8  * Copyright (c) 2007 Rajesh Prabhakaran.
   9  * All rights reserved.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  */
  32
  33 #ifndef MFI_REG_H
  34 #define MFI_REG_H
  35
  36 /*
  37  * MegaRAID SAS MFI firmware definitions
  38  */
  39
  40 /*
  41  * Start with the register set.  All registers are 32 bits wide.
  42  * The usual Intel IOP style setup.
  43  */
  44 #define MFI_IMSG0 0x10    /* Inbound message 0 */
  45 #define MFI_IMSG1 0x14    /* Inbound message 1 */
  46 #define MFI_OMSG0 0x18    /* Outbound message 0 */
  47 #define MFI_OMSG1 0x1c    /* Outbound message 1 */
  48 #define MFI_IDB   0x20    /* Inbound doorbell */
  49 #define MFI_ISTS  0x24    /* Inbound interrupt status */
  50 #define MFI_IMSK  0x28    /* Inbound interrupt mask */
  51 #define MFI_ODB   0x2c    /* Outbound doorbell */
  52 #define MFI_OSTS  0x30    /* Outbound interrupt status */
  53 #define MFI_OMSK  0x34    /* Outbound interrupt mask */
  54 #define MFI_IQP   0x40    /* Inbound queue port */
  55 #define MFI_OQP   0x44    /* Outbound queue port */
  56
  57 /*
  58  * 1078 specific related register
  59  */
  60 #define MFI_ODR0        0x9c            /* outbound doorbell register0 */
  61 #define MFI_ODCR0       0xa0            /* outbound doorbell clear register0  */
  62 #define MFI_OSP0        0xb0            /* outbound scratch pad0  */
  63 #define MFI_IQPL        0xc0            /* Inbound queue port (low bytes)  */
  64 #define MFI_IQPH        0xc4            /* Inbound queue port (high bytes)  */
  65 #define MFI_DIAG        0xf8            /* Host diag */
  66 #define MFI_SEQ         0xfc            /* Sequencer offset */
  67 #define MFI_1078_EIM    0x80000004      /* 1078 enable intrrupt mask  */
  68 #define MFI_RMI         0x2             /* reply message interrupt  */
  69 #define MFI_1078_RM     0x80000000      /* reply 1078 message interrupt  */
  70 #define MFI_ODC         0x4             /* outbound doorbell change interrupt */
  71
  72 /*
  73  * gen2 specific changes
  74  */
  75 #define MFI_GEN2_EIM    0x00000005      /* gen2 enable interrupt mask */
  76 #define MFI_GEN2_RM     0x00000001      /* reply gen2 message interrupt */
  77
  78 /*
  79  * skinny specific changes
  80  */
  81 #define MFI_SKINNY_IDB  0x00    /* Inbound doorbell is at 0x00 for skinny */
  82 #define MFI_SKINNY_RM   0x00000001      /* reply skinny message interrupt */
  83
  84 /* Bits for MFI_OSTS */
  85 #define MFI_OSTS_INTR_VALID     0x00000002
  86
  87 /*
  88  * Firmware state values.  Found in OMSG0 during initialization.
  89  */
  90 #define MFI_FWSTATE_MASK                0xf0000000
  91 #define MFI_FWSTATE_UNDEFINED           0x00000000
  92 #define MFI_FWSTATE_BB_INIT             0x10000000
  93 #define MFI_FWSTATE_FW_INIT             0x40000000
  94 #define MFI_FWSTATE_WAIT_HANDSHAKE      0x60000000
  95 #define MFI_FWSTATE_FW_INIT_2           0x70000000
  96 #define MFI_FWSTATE_DEVICE_SCAN         0x80000000
  97 #define MFI_FWSTATE_BOOT_MSG_PENDING    0x90000000
  98 #define MFI_FWSTATE_FLUSH_CACHE         0xa0000000
  99 #define MFI_FWSTATE_READY               0xb0000000
 100 #define MFI_FWSTATE_OPERATIONAL         0xc0000000
 101 #define MFI_FWSTATE_FAULT               0xf0000000
 102 #define MFI_FWSTATE_MAXSGL_MASK         0x00ff0000
 103 #define MFI_FWSTATE_MAXCMD_MASK         0x0000ffff
 104 #define MFI_FWSTATE_MSIX_SUPPORTED      0x04000000
 105 #define MFI_FWSTATE_HOSTMEMREQD_MASK    0x08000000
 106
 107 /*
 108  * Control bits to drive the card to ready state.  These go into the IDB
 109  * register.
 110  */
 111 #define MFI_FWINIT_ABORT        0x00000001 /* Abort all pending commands */
 112 #define MFI_FWINIT_READY        0x00000002 /* Move from operational to ready */
 113 #define MFI_FWINIT_MFIMODE      0x00000004 /* unknown */
 114 #define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */
 115 #define MFI_FWINIT_HOTPLUG      0x00000010
 116 #define MFI_FWINIT_STOP_ADP     0x00000020 /* Move to operational, stop */
 117 #define MFI_FWINIT_ADP_RESET    0x00000040 /* Reset ADP */
 118
 119 /* MFI Commands */
 120 typedef enum {
 121     MFI_CMD_INIT = 0x00,
 122     MFI_CMD_LD_READ,
 123     MFI_CMD_LD_WRITE,
 124     MFI_CMD_LD_SCSI_IO,
 125     MFI_CMD_PD_SCSI_IO,
 126     MFI_CMD_DCMD,
 127     MFI_CMD_ABORT,
 128     MFI_CMD_SMP,
 129     MFI_CMD_STP
 130 } mfi_cmd_t;
 131
 132 /* Direct commands */
 133 typedef enum {
 134     MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC =  0x0100e100,
 135     MFI_DCMD_CTRL_GET_INFO =            0x01010000,
 136     MFI_DCMD_CTRL_GET_PROPERTIES =      0x01020100,
 137     MFI_DCMD_CTRL_SET_PROPERTIES =      0x01020200,
 138     MFI_DCMD_CTRL_ALARM =               0x01030000,
 139     MFI_DCMD_CTRL_ALARM_GET =           0x01030100,
 140     MFI_DCMD_CTRL_ALARM_ENABLE =        0x01030200,
 141     MFI_DCMD_CTRL_ALARM_DISABLE =       0x01030300,
 142     MFI_DCMD_CTRL_ALARM_SILENCE =       0x01030400,
 143     MFI_DCMD_CTRL_ALARM_TEST =          0x01030500,
 144     MFI_DCMD_CTRL_EVENT_GETINFO =       0x01040100,
 145     MFI_DCMD_CTRL_EVENT_CLEAR =         0x01040200,
 146     MFI_DCMD_CTRL_EVENT_GET =           0x01040300,
 147     MFI_DCMD_CTRL_EVENT_COUNT =         0x01040400,
 148     MFI_DCMD_CTRL_EVENT_WAIT =          0x01040500,
 149     MFI_DCMD_CTRL_SHUTDOWN =            0x01050000,
 150     MFI_DCMD_HIBERNATE_STANDBY =        0x01060000,
 151     MFI_DCMD_CTRL_GET_TIME =            0x01080101,
 152     MFI_DCMD_CTRL_SET_TIME =            0x01080102,
 153     MFI_DCMD_CTRL_BIOS_DATA_GET =       0x010c0100,
 154     MFI_DCMD_CTRL_BIOS_DATA_SET =       0x010c0200,
 155     MFI_DCMD_CTRL_FACTORY_DEFAULTS =    0x010d0000,
 156     MFI_DCMD_CTRL_MFC_DEFAULTS_GET =    0x010e0201,
 157     MFI_DCMD_CTRL_MFC_DEFAULTS_SET =    0x010e0202,
 158     MFI_DCMD_CTRL_CACHE_FLUSH =         0x01101000,
 159     MFI_DCMD_PD_GET_LIST =              0x02010000,
 160     MFI_DCMD_PD_LIST_QUERY =            0x02010100,
 161     MFI_DCMD_PD_GET_INFO =              0x02020000,
 162     MFI_DCMD_PD_STATE_SET =             0x02030100,
 163     MFI_DCMD_PD_REBUILD =               0x02040100,
 164     MFI_DCMD_PD_BLINK =                 0x02070100,
 165     MFI_DCMD_PD_UNBLINK =               0x02070200,
 166     MFI_DCMD_LD_GET_LIST =              0x03010000,
 167     MFI_DCMD_LD_LIST_QUERY =            0x03010100,
 168     MFI_DCMD_LD_GET_INFO =              0x03020000,
 169     MFI_DCMD_LD_GET_PROP =              0x03030000,
 170     MFI_DCMD_LD_SET_PROP =              0x03040000,
 171     MFI_DCMD_LD_DELETE =                0x03090000,
 172     MFI_DCMD_CFG_READ =                 0x04010000,
 173     MFI_DCMD_CFG_ADD =                  0x04020000,
 174     MFI_DCMD_CFG_CLEAR =                0x04030000,
 175     MFI_DCMD_CFG_FOREIGN_READ =         0x04060100,
 176     MFI_DCMD_CFG_FOREIGN_IMPORT =       0x04060400,
 177     MFI_DCMD_BBU_STATUS =               0x05010000,
 178     MFI_DCMD_BBU_CAPACITY_INFO =        0x05020000,
 179     MFI_DCMD_BBU_DESIGN_INFO =          0x05030000,
 180     MFI_DCMD_BBU_PROP_GET =             0x05050100,
 181     MFI_DCMD_CLUSTER =                  0x08000000,
 182     MFI_DCMD_CLUSTER_RESET_ALL =        0x08010100,
 183     MFI_DCMD_CLUSTER_RESET_LD =         0x08010200
 184 } mfi_dcmd_t;
 185
 186 /* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */
 187 #define MFI_FLUSHCACHE_CTRL     0x01
 188 #define MFI_FLUSHCACHE_DISK     0x02
 189
 190 /* Modifiers for MFI_DCMD_CTRL_SHUTDOWN */
 191 #define MFI_SHUTDOWN_SPINDOWN   0x01
 192
 193 /*
 194  * MFI Frame flags
 195  */
 196 typedef enum {
 197     MFI_FRAME_DONT_POST_IN_REPLY_QUEUE =        0x0001,
 198     MFI_FRAME_SGL64 =                           0x0002,
 199     MFI_FRAME_SENSE64 =                         0x0004,
 200     MFI_FRAME_DIR_WRITE =                       0x0008,
 201     MFI_FRAME_DIR_READ =                        0x0010,
 202     MFI_FRAME_IEEE_SGL =                        0x0020,
 203 } mfi_frame_flags;
 204
 205 /* MFI Status codes */
 206 typedef enum {
 207     MFI_STAT_OK =                       0x00,
 208     MFI_STAT_INVALID_CMD,
 209     MFI_STAT_INVALID_DCMD,
 210     MFI_STAT_INVALID_PARAMETER,
 211     MFI_STAT_INVALID_SEQUENCE_NUMBER,
 212     MFI_STAT_ABORT_NOT_POSSIBLE,
 213     MFI_STAT_APP_HOST_CODE_NOT_FOUND,
 214     MFI_STAT_APP_IN_USE,
 215     MFI_STAT_APP_NOT_INITIALIZED,
 216     MFI_STAT_ARRAY_INDEX_INVALID,
 217     MFI_STAT_ARRAY_ROW_NOT_EMPTY,
 218     MFI_STAT_CONFIG_RESOURCE_CONFLICT,
 219     MFI_STAT_DEVICE_NOT_FOUND,
 220     MFI_STAT_DRIVE_TOO_SMALL,
 221     MFI_STAT_FLASH_ALLOC_FAIL,
 222     MFI_STAT_FLASH_BUSY,
 223     MFI_STAT_FLASH_ERROR =              0x10,
 224     MFI_STAT_FLASH_IMAGE_BAD,
 225     MFI_STAT_FLASH_IMAGE_INCOMPLETE,
 226     MFI_STAT_FLASH_NOT_OPEN,
 227     MFI_STAT_FLASH_NOT_STARTED,
 228     MFI_STAT_FLUSH_FAILED,
 229     MFI_STAT_HOST_CODE_NOT_FOUNT,
 230     MFI_STAT_LD_CC_IN_PROGRESS,
 231     MFI_STAT_LD_INIT_IN_PROGRESS,
 232     MFI_STAT_LD_LBA_OUT_OF_RANGE,
 233     MFI_STAT_LD_MAX_CONFIGURED,
 234     MFI_STAT_LD_NOT_OPTIMAL,
 235     MFI_STAT_LD_RBLD_IN_PROGRESS,
 236     MFI_STAT_LD_RECON_IN_PROGRESS,
 237     MFI_STAT_LD_WRONG_RAID_LEVEL,
 238     MFI_STAT_MAX_SPARES_EXCEEDED,
 239     MFI_STAT_MEMORY_NOT_AVAILABLE =     0x20,
 240     MFI_STAT_MFC_HW_ERROR,
 241     MFI_STAT_NO_HW_PRESENT,
 242     MFI_STAT_NOT_FOUND,
 243     MFI_STAT_NOT_IN_ENCL,
 244     MFI_STAT_PD_CLEAR_IN_PROGRESS,
 245     MFI_STAT_PD_TYPE_WRONG,
 246     MFI_STAT_PR_DISABLED,
 247     MFI_STAT_ROW_INDEX_INVALID,
 248     MFI_STAT_SAS_CONFIG_INVALID_ACTION,
 249     MFI_STAT_SAS_CONFIG_INVALID_DATA,
 250     MFI_STAT_SAS_CONFIG_INVALID_PAGE,
 251     MFI_STAT_SAS_CONFIG_INVALID_TYPE,
 252     MFI_STAT_SCSI_DONE_WITH_ERROR,
 253     MFI_STAT_SCSI_IO_FAILED,
 254     MFI_STAT_SCSI_RESERVATION_CONFLICT,
 255     MFI_STAT_SHUTDOWN_FAILED =          0x30,
 256     MFI_STAT_TIME_NOT_SET,
 257     MFI_STAT_WRONG_STATE,
 258     MFI_STAT_LD_OFFLINE,
 259     MFI_STAT_PEER_NOTIFICATION_REJECTED,
 260     MFI_STAT_PEER_NOTIFICATION_FAILED,
 261     MFI_STAT_RESERVATION_IN_PROGRESS,
 262     MFI_STAT_I2C_ERRORS_DETECTED,
 263     MFI_STAT_PCI_ERRORS_DETECTED,
 264     MFI_STAT_DIAG_FAILED,
 265     MFI_STAT_BOOT_MSG_PENDING,
 266     MFI_STAT_FOREIGN_CONFIG_INCOMPLETE,
 267     MFI_STAT_INVALID_SGL,
 268     MFI_STAT_UNSUPPORTED_HW,
 269     MFI_STAT_CC_SCHEDULE_DISABLED,
 270     MFI_STAT_PD_COPYBACK_IN_PROGRESS,
 271     MFI_STAT_MULTIPLE_PDS_IN_ARRAY =    0x40,
 272     MFI_STAT_FW_DOWNLOAD_ERROR,
 273     MFI_STAT_FEATURE_SECURITY_NOT_ENABLED,
 274     MFI_STAT_LOCK_KEY_ALREADY_EXISTS,
 275     MFI_STAT_LOCK_KEY_BACKUP_NOT_ALLOWED,
 276     MFI_STAT_LOCK_KEY_VERIFY_NOT_ALLOWED,
 277     MFI_STAT_LOCK_KEY_VERIFY_FAILED,
 278     MFI_STAT_LOCK_KEY_REKEY_NOT_ALLOWED,
 279     MFI_STAT_LOCK_KEY_INVALID,
 280     MFI_STAT_LOCK_KEY_ESCROW_INVALID,
 281     MFI_STAT_LOCK_KEY_BACKUP_REQUIRED,
 282     MFI_STAT_SECURE_LD_EXISTS,
 283     MFI_STAT_LD_SECURE_NOT_ALLOWED,
 284     MFI_STAT_REPROVISION_NOT_ALLOWED,
 285     MFI_STAT_PD_SECURITY_TYPE_WRONG,
 286     MFI_STAT_LD_ENCRYPTION_TYPE_INVALID,
 287     MFI_STAT_CONFIG_FDE_NON_FDE_MIX_NOT_ALLOWED = 0x50,
 288     MFI_STAT_CONFIG_LD_ENCRYPTION_TYPE_MIX_NOT_ALLOWED,
 289     MFI_STAT_SECRET_KEY_NOT_ALLOWED,
 290     MFI_STAT_PD_HW_ERRORS_DETECTED,
 291     MFI_STAT_LD_CACHE_PINNED,
 292     MFI_STAT_POWER_STATE_SET_IN_PROGRESS,
 293     MFI_STAT_POWER_STATE_SET_BUSY,
 294     MFI_STAT_POWER_STATE_WRONG,
 295     MFI_STAT_PR_NO_AVAILABLE_PD_FOUND,
 296     MFI_STAT_CTRL_RESET_REQUIRED,
 297     MFI_STAT_LOCK_KEY_EKM_NO_BOOT_AGENT,
 298     MFI_STAT_SNAP_NO_SPACE,
 299     MFI_STAT_SNAP_PARTIAL_FAILURE,
 300     MFI_STAT_UPGRADE_KEY_INCOMPATIBLE,
 301     MFI_STAT_PFK_INCOMPATIBLE,
 302     MFI_STAT_PD_MAX_UNCONFIGURED,
 303     MFI_STAT_IO_METRICS_DISABLED =      0x60,
 304     MFI_STAT_AEC_NOT_STOPPED,
 305     MFI_STAT_PI_TYPE_WRONG,
 306     MFI_STAT_LD_PD_PI_INCOMPATIBLE,
 307     MFI_STAT_PI_NOT_ENABLED,
 308     MFI_STAT_LD_BLOCK_SIZE_MISMATCH,
 309     MFI_STAT_INVALID_STATUS =           0xFF
 310 } mfi_status_t;
 311
 312 /* Event classes */
 313 typedef enum {
 314     MFI_EVT_CLASS_DEBUG =      -2,
 315     MFI_EVT_CLASS_PROGRESS =   -1,
 316     MFI_EVT_CLASS_INFO =        0,
 317     MFI_EVT_CLASS_WARNING =     1,
 318     MFI_EVT_CLASS_CRITICAL =    2,
 319     MFI_EVT_CLASS_FATAL =       3,
 320     MFI_EVT_CLASS_DEAD =        4
 321 } mfi_evt_class_t;
 322
 323 /* Event locales */
 324 typedef enum {
 325     MFI_EVT_LOCALE_LD =         0x0001,
 326     MFI_EVT_LOCALE_PD =         0x0002,
 327     MFI_EVT_LOCALE_ENCL =       0x0004,
 328     MFI_EVT_LOCALE_BBU =        0x0008,
 329     MFI_EVT_LOCALE_SAS =        0x0010,
 330     MFI_EVT_LOCALE_CTRL =       0x0020,
 331     MFI_EVT_LOCALE_CONFIG =     0x0040,
 332     MFI_EVT_LOCALE_CLUSTER =    0x0080,
 333     MFI_EVT_LOCALE_ALL =        0xffff
 334 } mfi_evt_locale_t;
 335
 336 /* Event args */
 337 typedef enum {
 338     MR_EVT_ARGS_NONE =          0x00,
 339     MR_EVT_ARGS_CDB_SENSE,
 340     MR_EVT_ARGS_LD,
 341     MR_EVT_ARGS_LD_COUNT,
 342     MR_EVT_ARGS_LD_LBA,
 343     MR_EVT_ARGS_LD_OWNER,
 344     MR_EVT_ARGS_LD_LBA_PD_LBA,
 345     MR_EVT_ARGS_LD_PROG,
 346     MR_EVT_ARGS_LD_STATE,
 347     MR_EVT_ARGS_LD_STRIP,
 348     MR_EVT_ARGS_PD,
 349     MR_EVT_ARGS_PD_ERR,
 350     MR_EVT_ARGS_PD_LBA,
 351     MR_EVT_ARGS_PD_LBA_LD,
 352     MR_EVT_ARGS_PD_PROG,
 353     MR_EVT_ARGS_PD_STATE,
 354     MR_EVT_ARGS_PCI,
 355     MR_EVT_ARGS_RATE,
 356     MR_EVT_ARGS_STR,
 357     MR_EVT_ARGS_TIME,
 358     MR_EVT_ARGS_ECC,
 359     MR_EVT_ARGS_LD_PROP,
 360     MR_EVT_ARGS_PD_SPARE,
 361     MR_EVT_ARGS_PD_INDEX,
 362     MR_EVT_ARGS_DIAG_PASS,
 363     MR_EVT_ARGS_DIAG_FAIL,
 364     MR_EVT_ARGS_PD_LBA_LBA,
 365     MR_EVT_ARGS_PORT_PHY,
 366     MR_EVT_ARGS_PD_MISSING,
 367     MR_EVT_ARGS_PD_ADDRESS,
 368     MR_EVT_ARGS_BITMAP,
 369     MR_EVT_ARGS_CONNECTOR,
 370     MR_EVT_ARGS_PD_PD,
 371     MR_EVT_ARGS_PD_FRU,
 372     MR_EVT_ARGS_PD_PATHINFO,
 373     MR_EVT_ARGS_PD_POWER_STATE,
 374     MR_EVT_ARGS_GENERIC,
 375 } mfi_evt_args;
 376
 377 /* Event codes */
 378 #define MR_EVT_CFG_CLEARED                          0x0004
 379 #define MR_EVT_CTRL_SHUTDOWN                        0x002a
 380 #define MR_EVT_LD_STATE_CHANGE                      0x0051
 381 #define MR_EVT_PD_INSERTED                          0x005b
 382 #define MR_EVT_PD_REMOVED                           0x0070
 383 #define MR_EVT_PD_STATE_CHANGED                     0x0072
 384 #define MR_EVT_LD_CREATED                           0x008a
 385 #define MR_EVT_LD_DELETED                           0x008b
 386 #define MR_EVT_FOREIGN_CFG_IMPORTED                 0x00db
 387 #define MR_EVT_LD_OFFLINE                           0x00fc
 388 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED         0x0152
 389
 390 typedef enum {
 391     MR_LD_CACHE_WRITE_BACK =            0x01,
 392     MR_LD_CACHE_WRITE_ADAPTIVE =        0x02,
 393     MR_LD_CACHE_READ_AHEAD =            0x04,
 394     MR_LD_CACHE_READ_ADAPTIVE =         0x08,
 395     MR_LD_CACHE_WRITE_CACHE_BAD_BBU =   0x10,
 396     MR_LD_CACHE_ALLOW_WRITE_CACHE =     0x20,
 397     MR_LD_CACHE_ALLOW_READ_CACHE =      0x40
 398 } mfi_ld_cache;
 399
 400 typedef enum {
 401     MR_PD_CACHE_UNCHANGED  =    0,
 402     MR_PD_CACHE_ENABLE =        1,
 403     MR_PD_CACHE_DISABLE =       2
 404 } mfi_pd_cache;
 405
 406 typedef enum {
 407     MR_PD_QUERY_TYPE_ALL =              0,
 408     MR_PD_QUERY_TYPE_STATE =            1,
 409     MR_PD_QUERY_TYPE_POWER_STATE =      2,
 410     MR_PD_QUERY_TYPE_MEDIA_TYPE =       3,
 411     MR_PD_QUERY_TYPE_SPEED =            4,
 412     MR_PD_QUERY_TYPE_EXPOSED_TO_HOST =  5, /*query for system drives */
 413 } mfi_pd_query_type;
 414
 415 typedef enum {
 416     MR_LD_QUERY_TYPE_ALL =              0,
 417     MR_LD_QUERY_TYPE_EXPOSED_TO_HOST =  1,
 418     MR_LD_QUERY_TYPE_USED_TGT_IDS =     2,
 419     MR_LD_QUERY_TYPE_CLUSTER_ACCESS =   3,
 420     MR_LD_QUERY_TYPE_CLUSTER_LOCALE =   4,
 421 } mfi_ld_query_type;
 422
 423 /*
 424  * Other propertities and definitions
 425  */
 426 #define MFI_MAX_PD_CHANNELS     2
 427 #define MFI_MAX_LD_CHANNELS     2
 428 #define MFI_MAX_CHANNELS        (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS)
 429 #define MFI_MAX_CHANNEL_DEVS  128
 430 #define MFI_DEFAULT_ID         -1
 431 #define MFI_MAX_LUN             8
 432 #define MFI_MAX_LD             64
 433
 434 #define MFI_FRAME_SIZE         64
 435 #define MFI_MBOX_SIZE          12
 436
 437 /* Firmware flashing can take 40s */
 438 #define MFI_POLL_TIMEOUT_SECS  50
 439
 440 /* Allow for speedier math calculations */
 441 #define MFI_SECTOR_LEN        512
 442
 443 /* Scatter Gather elements */
 444 struct mfi_sg32 {
 445     uint32_t addr;
 446     uint32_t len;
 447 } QEMU_PACKED;
 448
 449 struct mfi_sg64 {
 450     uint64_t addr;
 451     uint32_t len;
 452 } QEMU_PACKED;
 453
 454 struct mfi_sg_skinny {
 455     uint64_t addr;
 456     uint32_t len;
 457     uint32_t flag;
 458 } QEMU_PACKED;
 459
 460 union mfi_sgl {
 461     struct mfi_sg32 sg32[1];
 462     struct mfi_sg64 sg64[1];
 463     struct mfi_sg_skinny sg_skinny[1];
 464 } QEMU_PACKED;
 465
 466 /* Message frames.  All messages have a common header */
 467 struct mfi_frame_header {
 468     uint8_t frame_cmd;
 469     uint8_t sense_len;
 470     uint8_t cmd_status;
 471     uint8_t scsi_status;
 472     uint8_t target_id;
 473     uint8_t lun_id;
 474     uint8_t cdb_len;
 475     uint8_t sge_count;
 476     uint64_t context;
 477     uint16_t flags;
 478     uint16_t timeout;
 479     uint32_t data_len;
 480 } QEMU_PACKED;
 481
 482 struct mfi_init_frame {
 483     struct mfi_frame_header header;
 484     uint32_t qinfo_new_addr_lo;
 485     uint32_t qinfo_new_addr_hi;
 486     uint32_t qinfo_old_addr_lo;
 487     uint32_t qinfo_old_addr_hi;
 488     uint32_t reserved[6];
 489 };
 490
 491 #define MFI_IO_FRAME_SIZE 40
 492 struct mfi_io_frame {
 493     struct mfi_frame_header header;
 494     uint32_t sense_addr_lo;
 495     uint32_t sense_addr_hi;
 496     uint32_t lba_lo;
 497     uint32_t lba_hi;
 498     union mfi_sgl sgl;
 499 } QEMU_PACKED;
 500
 501 #define MFI_PASS_FRAME_SIZE 48
 502 struct mfi_pass_frame {
 503     struct mfi_frame_header header;
 504     uint32_t sense_addr_lo;
 505     uint32_t sense_addr_hi;
 506     uint8_t cdb[16];
 507     union mfi_sgl sgl;
 508 } QEMU_PACKED;
 509
 510 #define MFI_DCMD_FRAME_SIZE 40
 511 struct mfi_dcmd_frame {
 512     struct mfi_frame_header header;
 513     uint32_t opcode;
 514     uint8_t mbox[MFI_MBOX_SIZE];
 515     union mfi_sgl sgl;
 516 } QEMU_PACKED;
 517
 518 struct mfi_abort_frame {
 519     struct mfi_frame_header header;
 520     uint64_t abort_context;
 521     uint32_t abort_mfi_addr_lo;
 522     uint32_t abort_mfi_addr_hi;
 523     uint32_t reserved1[6];
 524 } QEMU_PACKED;
 525
 526 struct mfi_smp_frame {
 527     struct mfi_frame_header header;
 528     uint64_t sas_addr;
 529     union {
 530         struct mfi_sg32 sg32[2];
 531         struct mfi_sg64 sg64[2];
 532     } sgl;
 533 } QEMU_PACKED;
 534
 535 struct mfi_stp_frame {
 536     struct mfi_frame_header header;
 537     uint16_t fis[10];
 538     uint32_t stp_flags;
 539     union {
 540         struct mfi_sg32 sg32[2];
 541         struct mfi_sg64 sg64[2];
 542     } sgl;
 543 } QEMU_PACKED;
 544
 545 union mfi_frame {
 546     struct mfi_frame_header header;
 547     struct mfi_init_frame init;
 548     struct mfi_io_frame io;
 549     struct mfi_pass_frame pass;
 550     struct mfi_dcmd_frame dcmd;
 551     struct mfi_abort_frame abort;
 552     struct mfi_smp_frame smp;
 553     struct mfi_stp_frame stp;
 554     uint64_t raw[8];
 555     uint8_t bytes[MFI_FRAME_SIZE];
 556 };
 557
 558 #define MFI_SENSE_LEN 128
 559 struct mfi_sense {
 560     uint8_t     data[MFI_SENSE_LEN];
 561 };
 562
 563 #define MFI_QUEUE_FLAG_CONTEXT64 0x00000002
 564
 565 /* The queue init structure that is passed with the init message */
 566 struct mfi_init_qinfo {
 567     uint32_t flags;
 568     uint32_t rq_entries;
 569     uint32_t rq_addr_lo;
 570     uint32_t rq_addr_hi;
 571     uint32_t pi_addr_lo;
 572     uint32_t pi_addr_hi;
 573     uint32_t ci_addr_lo;
 574     uint32_t ci_addr_hi;
 575 } QEMU_PACKED;
 576
 577 /* Controller properties */
 578 struct mfi_ctrl_props {
 579     uint16_t seq_num;
 580     uint16_t pred_fail_poll_interval;
 581     uint16_t intr_throttle_cnt;
 582     uint16_t intr_throttle_timeout;
 583     uint8_t rebuild_rate;
 584     uint8_t patrol_read_rate;
 585     uint8_t bgi_rate;
 586     uint8_t cc_rate;
 587     uint8_t recon_rate;
 588     uint8_t cache_flush_interval;
 589     uint8_t spinup_drv_cnt;
 590     uint8_t spinup_delay;
 591     uint8_t cluster_enable;
 592     uint8_t coercion_mode;
 593     uint8_t alarm_enable;
 594     uint8_t disable_auto_rebuild;
 595     uint8_t disable_battery_warn;
 596     uint8_t ecc_bucket_size;
 597     uint16_t ecc_bucket_leak_rate;
 598     uint8_t restore_hotspare_on_insertion;
 599     uint8_t expose_encl_devices;
 600     uint8_t maintainPdFailHistory;
 601     uint8_t disallowHostRequestReordering;
 602     uint8_t abortCCOnError;
 603     uint8_t loadBalanceMode;
 604     uint8_t disableAutoDetectBackplane;
 605     uint8_t snapVDSpace;
 606     uint32_t OnOffProperties;
 607 /* set TRUE to disable copyBack (0=copyback enabled) */
 608 #define MFI_CTRL_PROP_CopyBackDisabled           (1 << 0)
 609 #define MFI_CTRL_PROP_SMARTerEnabled             (1 << 1)
 610 #define MFI_CTRL_PROP_PRCorrectUnconfiguredAreas (1 << 2)
 611 #define MFI_CTRL_PROP_UseFdeOnly                 (1 << 3)
 612 #define MFI_CTRL_PROP_DisableNCQ                 (1 << 4)
 613 #define MFI_CTRL_PROP_SSDSMARTerEnabled          (1 << 5)
 614 #define MFI_CTRL_PROP_SSDPatrolReadEnabled       (1 << 6)
 615 #define MFI_CTRL_PROP_EnableSpinDownUnconfigured (1 << 7)
 616 #define MFI_CTRL_PROP_AutoEnhancedImport         (1 << 8)
 617 #define MFI_CTRL_PROP_EnableSecretKeyControl     (1 << 9)
 618 #define MFI_CTRL_PROP_DisableOnlineCtrlReset     (1 << 10)
 619 #define MFI_CTRL_PROP_AllowBootWithPinnedCache   (1 << 11)
 620 #define MFI_CTRL_PROP_DisableSpinDownHS          (1 << 12)
 621 #define MFI_CTRL_PROP_EnableJBOD                 (1 << 13)
 622
 623     uint8_t autoSnapVDSpace; /* % of source LD to be
 624                               * reserved for auto snapshot
 625                               * in snapshot repository, for
 626                               * metadata and user data
 627                               * 1=5%, 2=10%, 3=15% and so on
 628                               */
 629     uint8_t viewSpace;       /* snapshot writeable VIEWs
 630                               * capacity as a % of source LD
 631                               * capacity. 0=READ only
 632                               * 1=5%, 2=10%, 3=15% and so on
 633                               */
 634     uint16_t spinDownTime;    /* # of idle minutes before device
 635                                * is spun down (0=use FW defaults)
 636                                */
 637     uint8_t reserved[24];
 638 } QEMU_PACKED;
 639
 640 /* PCI information about the card. */
 641 struct mfi_info_pci {
 642     uint16_t vendor;
 643     uint16_t device;
 644     uint16_t subvendor;
 645     uint16_t subdevice;
 646     uint8_t reserved[24];
 647 } QEMU_PACKED;
 648
 649 /* Host (front end) interface information */
 650 struct mfi_info_host {
 651     uint8_t type;
 652 #define MFI_INFO_HOST_PCIX      0x01
 653 #define MFI_INFO_HOST_PCIE      0x02
 654 #define MFI_INFO_HOST_ISCSI     0x04
 655 #define MFI_INFO_HOST_SAS3G     0x08
 656     uint8_t reserved[6];
 657     uint8_t port_count;
 658     uint64_t port_addr[8];
 659 } QEMU_PACKED;
 660
 661 /* Device (back end) interface information */
 662 struct mfi_info_device {
 663     uint8_t type;
 664 #define MFI_INFO_DEV_SPI        0x01
 665 #define MFI_INFO_DEV_SAS3G      0x02
 666 #define MFI_INFO_DEV_SATA1      0x04
 667 #define MFI_INFO_DEV_SATA3G     0x08
 668 #define MFI_INFO_DEV_PCIE       0x10
 669     uint8_t reserved[6];
 670     uint8_t port_count;
 671     uint64_t port_addr[8];
 672 } QEMU_PACKED;
 673
 674 /* Firmware component information */
 675 struct mfi_info_component {
 676     char name[8];
 677     char version[32];
 678     char build_date[16];
 679     char build_time[16];
 680 } QEMU_PACKED;
 681
 682 /* Controller default settings */
 683 struct mfi_defaults {
 684     uint64_t sas_addr;
 685     uint8_t phy_polarity;
 686     uint8_t background_rate;
 687     uint8_t stripe_size;
 688     uint8_t flush_time;
 689     uint8_t write_back;
 690     uint8_t read_ahead;
 691     uint8_t cache_when_bbu_bad;
 692     uint8_t cached_io;
 693     uint8_t smart_mode;
 694     uint8_t alarm_disable;
 695     uint8_t coercion;
 696     uint8_t zrc_config;
 697     uint8_t dirty_led_shows_drive_activity;
 698     uint8_t bios_continue_on_error;
 699     uint8_t spindown_mode;
 700     uint8_t allowed_device_types;
 701     uint8_t allow_mix_in_enclosure;
 702     uint8_t allow_mix_in_ld;
 703     uint8_t allow_sata_in_cluster;
 704     uint8_t max_chained_enclosures;
 705     uint8_t disable_ctrl_r;
 706     uint8_t enable_web_bios;
 707     uint8_t phy_polarity_split;
 708     uint8_t direct_pd_mapping;
 709     uint8_t bios_enumerate_lds;
 710     uint8_t restored_hot_spare_on_insertion;
 711     uint8_t expose_enclosure_devices;
 712     uint8_t maintain_pd_fail_history;
 713     uint8_t disable_puncture;
 714     uint8_t zero_based_enumeration;
 715     uint8_t disable_preboot_cli;
 716     uint8_t show_drive_led_on_activity;
 717     uint8_t cluster_disable;
 718     uint8_t sas_disable;
 719     uint8_t auto_detect_backplane;
 720     uint8_t fde_only;
 721     uint8_t delay_during_post;
 722     uint8_t resv[19];
 723 } QEMU_PACKED;
 724
 725 /* Controller default settings */
 726 struct mfi_bios_data {
 727     uint16_t boot_target_id;
 728     uint8_t do_not_int_13;
 729     uint8_t continue_on_error;
 730     uint8_t verbose;
 731     uint8_t geometry;
 732     uint8_t expose_all_drives;
 733     uint8_t reserved[56];
 734     uint8_t check_sum;
 735 } QEMU_PACKED;
 736
 737 /* SAS (?) controller info, returned from MFI_DCMD_CTRL_GETINFO. */
 738 struct mfi_ctrl_info {
 739     struct mfi_info_pci pci;
 740     struct mfi_info_host host;
 741     struct mfi_info_device device;
 742
 743     /* Firmware components that are present and active. */
 744     uint32_t image_check_word;
 745     uint32_t image_component_count;
 746     struct mfi_info_component image_component[8];
 747
 748     /* Firmware components that have been flashed but are inactive */
 749     uint32_t pending_image_component_count;
 750     struct mfi_info_component pending_image_component[8];
 751
 752     uint8_t max_arms;
 753     uint8_t max_spans;
 754     uint8_t max_arrays;
 755     uint8_t max_lds;
 756     char product_name[80];
 757     char serial_number[32];
 758     uint32_t hw_present;
 759 #define MFI_INFO_HW_BBU         0x01
 760 #define MFI_INFO_HW_ALARM       0x02
 761 #define MFI_INFO_HW_NVRAM       0x04
 762 #define MFI_INFO_HW_UART        0x08
 763 #define MFI_INFO_HW_MEM         0x10
 764 #define MFI_INFO_HW_FLASH       0x20
 765     uint32_t current_fw_time;
 766     uint16_t max_cmds;
 767     uint16_t max_sg_elements;
 768     uint32_t max_request_size;
 769     uint16_t lds_present;
 770     uint16_t lds_degraded;
 771     uint16_t lds_offline;
 772     uint16_t pd_present;
 773     uint16_t pd_disks_present;
 774     uint16_t pd_disks_pred_failure;
 775     uint16_t pd_disks_failed;
 776     uint16_t nvram_size;
 777     uint16_t memory_size;
 778     uint16_t flash_size;
 779     uint16_t ram_correctable_errors;
 780     uint16_t ram_uncorrectable_errors;
 781     uint8_t cluster_allowed;
 782     uint8_t cluster_active;
 783     uint16_t max_strips_per_io;
 784
 785     uint32_t raid_levels;
 786 #define MFI_INFO_RAID_0         0x01
 787 #define MFI_INFO_RAID_1         0x02
 788 #define MFI_INFO_RAID_5         0x04
 789 #define MFI_INFO_RAID_1E        0x08
 790 #define MFI_INFO_RAID_6         0x10
 791
 792     uint32_t adapter_ops;
 793 #define MFI_INFO_AOPS_RBLD_RATE         0x0001
 794 #define MFI_INFO_AOPS_CC_RATE           0x0002
 795 #define MFI_INFO_AOPS_BGI_RATE          0x0004
 796 #define MFI_INFO_AOPS_RECON_RATE        0x0008
 797 #define MFI_INFO_AOPS_PATROL_RATE       0x0010
 798 #define MFI_INFO_AOPS_ALARM_CONTROL     0x0020
 799 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040
 800 #define MFI_INFO_AOPS_BBU               0x0080
 801 #define MFI_INFO_AOPS_SPANNING_ALLOWED  0x0100
 802 #define MFI_INFO_AOPS_DEDICATED_SPARES  0x0200
 803 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400
 804 #define MFI_INFO_AOPS_FOREIGN_IMPORT    0x0800
 805 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC   0x1000
 806 #define MFI_INFO_AOPS_MIXED_ARRAY       0x2000
 807 #define MFI_INFO_AOPS_GLOBAL_SPARES     0x4000
 808
 809     uint32_t ld_ops;
 810 #define MFI_INFO_LDOPS_READ_POLICY      0x01
 811 #define MFI_INFO_LDOPS_WRITE_POLICY     0x02
 812 #define MFI_INFO_LDOPS_IO_POLICY        0x04
 813 #define MFI_INFO_LDOPS_ACCESS_POLICY    0x08
 814 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10
 815
 816     struct {
 817         uint8_t min;
 818         uint8_t max;
 819         uint8_t reserved[2];
 820     } QEMU_PACKED stripe_sz_ops;
 821
 822     uint32_t pd_ops;
 823 #define MFI_INFO_PDOPS_FORCE_ONLINE     0x01
 824 #define MFI_INFO_PDOPS_FORCE_OFFLINE    0x02
 825 #define MFI_INFO_PDOPS_FORCE_REBUILD    0x04
 826
 827     uint32_t pd_mix_support;
 828 #define MFI_INFO_PDMIX_SAS              0x01
 829 #define MFI_INFO_PDMIX_SATA             0x02
 830 #define MFI_INFO_PDMIX_ENCL             0x04
 831 #define MFI_INFO_PDMIX_LD               0x08
 832 #define MFI_INFO_PDMIX_SATA_CLUSTER     0x10
 833
 834     uint8_t ecc_bucket_count;
 835     uint8_t reserved2[11];
 836     struct mfi_ctrl_props properties;
 837     char package_version[0x60];
 838     uint8_t pad[0x800 - 0x6a0];
 839 } QEMU_PACKED;
 840
 841 /* keep track of an event. */
 842 union mfi_evt {
 843     struct {
 844         uint16_t locale;
 845         uint8_t reserved;
 846         int8_t class;
 847     } members;
 848     uint32_t word;
 849 } QEMU_PACKED;
 850
 851 /* event log state. */
 852 struct mfi_evt_log_state {
 853     uint32_t newest_seq_num;
 854     uint32_t oldest_seq_num;
 855     uint32_t clear_seq_num;
 856     uint32_t shutdown_seq_num;
 857     uint32_t boot_seq_num;
 858 } QEMU_PACKED;
 859
 860 struct mfi_progress {
 861     uint16_t progress;
 862     uint16_t elapsed_seconds;
 863 } QEMU_PACKED;
 864
 865 struct mfi_evt_ld {
 866     uint16_t target_id;
 867     uint8_t ld_index;
 868     uint8_t reserved;
 869 } QEMU_PACKED;
 870
 871 struct mfi_evt_pd {
 872     uint16_t device_id;
 873     uint8_t enclosure_index;
 874     uint8_t slot_number;
 875 } QEMU_PACKED;
 876
 877 /* event detail, returned from MFI_DCMD_CTRL_EVENT_WAIT. */
 878 struct mfi_evt_detail {
 879     uint32_t seq;
 880     uint32_t time;
 881     uint32_t code;
 882     union mfi_evt class;
 883     uint8_t arg_type;
 884     uint8_t reserved1[15];
 885
 886     union {
 887         struct {
 888             struct mfi_evt_pd pd;
 889             uint8_t cdb_len;
 890             uint8_t sense_len;
 891             uint8_t reserved[2];
 892             uint8_t cdb[16];
 893             uint8_t sense[64];
 894         } cdb_sense;
 895
 896         struct mfi_evt_ld ld;
 897
 898         struct {
 899             struct mfi_evt_ld ld;
 900             uint64_t count;
 901         } ld_count;
 902
 903         struct {
 904             uint64_t lba;
 905             struct mfi_evt_ld ld;
 906         } ld_lba;
 907
 908         struct {
 909             struct mfi_evt_ld ld;
 910             uint32_t pre_owner;
 911             uint32_t new_owner;
 912         } ld_owner;
 913
 914         struct {
 915             uint64_t ld_lba;
 916             uint64_t pd_lba;
 917             struct mfi_evt_ld ld;
 918             struct mfi_evt_pd pd;
 919         } ld_lba_pd_lba;
 920
 921         struct {
 922             struct mfi_evt_ld ld;
 923             struct mfi_progress prog;
 924         } ld_prog;
 925
 926         struct {
 927             struct mfi_evt_ld ld;
 928             uint32_t prev_state;
 929             uint32_t new_state;
 930         } ld_state;
 931
 932         struct {
 933             uint64_t strip;
 934             struct mfi_evt_ld ld;
 935         } ld_strip;
 936
 937         struct mfi_evt_pd pd;
 938
 939         struct {
 940             struct mfi_evt_pd pd;
 941             uint32_t err;
 942         } pd_err;
 943
 944         struct {
 945             uint64_t lba;
 946             struct mfi_evt_pd pd;
 947         } pd_lba;
 948
 949         struct {
 950             uint64_t lba;
 951             struct mfi_evt_pd pd;
 952             struct mfi_evt_ld ld;
 953         } pd_lba_ld;
 954
 955         struct {
 956             struct mfi_evt_pd pd;
 957             struct mfi_progress prog;
 958         } pd_prog;
 959
 960         struct {
 961             struct mfi_evt_pd ld;
 962             uint32_t prev_state;
 963             uint32_t new_state;
 964         } pd_state;
 965
 966         struct {
 967             uint16_t venderId;
 968             uint16_t deviceId;
 969             uint16_t subVenderId;
 970             uint16_t subDeviceId;
 971         } pci;
 972
 973         uint32_t rate;
 974
 975         char str[96];
 976
 977         struct {
 978             uint32_t rtc;
 979             uint16_t elapsedSeconds;
 980         } time;
 981
 982         struct {
 983             uint32_t ecar;
 984             uint32_t elog;
 985             char str[64];
 986         } ecc;
 987
 988         uint8_t b[96];
 989         uint16_t s[48];
 990         uint32_t w[24];
 991         uint64_t d[12];
 992     } args;
 993
 994     char description[128];
 995 } QEMU_PACKED;
 996
 997 struct mfi_evt_list {
 998     uint32_t count;
 999     uint32_t reserved;
1000     struct mfi_evt_detail event[1];
1001 } QEMU_PACKED;
1002
1003 union mfi_pd_ref {
1004     struct {
1005         uint16_t device_id;
1006         uint16_t seq_num;
1007     } v;
1008     uint32_t ref;
1009 } QEMU_PACKED;
1010
1011 union mfi_pd_ddf_type {
1012     struct {
1013         uint16_t pd_type;
1014 #define MFI_PD_DDF_TYPE_FORCED_PD_GUID (1 << 0)
1015 #define MFI_PD_DDF_TYPE_IN_VD          (1 << 1)
1016 #define MFI_PD_DDF_TYPE_IS_GLOBAL_SPARE (1 << 2)
1017 #define MFI_PD_DDF_TYPE_IS_SPARE        (1 << 3)
1018 #define MFI_PD_DDF_TYPE_IS_FOREIGN      (1 << 4)
1019 #define MFI_PD_DDF_TYPE_INTF_SPI        (1 << 12)
1020 #define MFI_PD_DDF_TYPE_INTF_SAS        (1 << 13)
1021 #define MFI_PD_DDF_TYPE_INTF_SATA1      (1 << 14)
1022 #define MFI_PD_DDF_TYPE_INTF_SATA3G     (1 << 15)
1023         uint16_t reserved;
1024     } ddf;
1025     struct {
1026         uint32_t reserved;
1027     } non_disk;
1028     uint32_t type;
1029 } QEMU_PACKED;
1030
1031 struct mfi_pd_progress {
1032     uint32_t active;
1033 #define PD_PROGRESS_ACTIVE_REBUILD (1 << 0)
1034 #define PD_PROGRESS_ACTIVE_PATROL  (1 << 1)
1035 #define PD_PROGRESS_ACTIVE_CLEAR   (1 << 2)
1036     struct mfi_progress rbld;
1037     struct mfi_progress patrol;
1038     struct mfi_progress clear;
1039     struct mfi_progress reserved[4];
1040 } QEMU_PACKED;
1041
1042 struct mfi_pd_info {
1043     union mfi_pd_ref ref;
1044     uint8_t inquiry_data[96];
1045     uint8_t vpd_page83[64];
1046     uint8_t not_supported;
1047     uint8_t scsi_dev_type;
1048     uint8_t connected_port_bitmap;
1049     uint8_t device_speed;
1050     uint32_t media_err_count;
1051     uint32_t other_err_count;
1052     uint32_t pred_fail_count;
1053     uint32_t last_pred_fail_event_seq_num;
1054     uint16_t fw_state;
1055     uint8_t disable_for_removal;
1056     uint8_t link_speed;
1057     union mfi_pd_ddf_type state;
1058     struct {
1059         uint8_t count;
1060         uint8_t is_path_broken;
1061         uint8_t reserved[6];
1062         uint64_t sas_addr[4];
1063     } path_info;
1064     uint64_t raw_size;
1065     uint64_t non_coerced_size;
1066     uint64_t coerced_size;
1067     uint16_t encl_device_id;
1068     uint8_t encl_index;
1069     uint8_t slot_number;
1070     struct mfi_pd_progress prog_info;
1071     uint8_t bad_block_table_full;
1072     uint8_t unusable_in_current_config;
1073     uint8_t vpd_page83_ext[64];
1074     uint8_t reserved[512-358];
1075 } QEMU_PACKED;
1076
1077 struct mfi_pd_address {
1078     uint16_t device_id;
1079     uint16_t encl_device_id;
1080     uint8_t encl_index;
1081     uint8_t slot_number;
1082     uint8_t scsi_dev_type;
1083     uint8_t connect_port_bitmap;
1084     uint64_t sas_addr[2];
1085 } QEMU_PACKED;
1086
1087 #define MFI_MAX_SYS_PDS 240
1088 struct mfi_pd_list {
1089     uint32_t size;
1090     uint32_t count;
1091     struct mfi_pd_address addr[MFI_MAX_SYS_PDS];
1092 } QEMU_PACKED;
1093
1094 union mfi_ld_ref {
1095     struct {
1096         uint8_t target_id;
1097         uint8_t lun_id;
1098         uint16_t seq;
1099     } v;
1100     uint32_t ref;
1101 } QEMU_PACKED;
1102
1103 struct mfi_ld_list {
1104     uint32_t ld_count;
1105     uint32_t reserved1;
1106     struct {
1107         union mfi_ld_ref ld;
1108         uint8_t state;
1109         uint8_t reserved2[3];
1110         uint64_t size;
1111     } ld_list[MFI_MAX_LD];
1112 } QEMU_PACKED;
1113
1114 enum mfi_ld_access {
1115     MFI_LD_ACCESS_RW =          0,
1116     MFI_LD_ACCSSS_RO =          2,
1117     MFI_LD_ACCESS_BLOCKED =     3,
1118 };
1119 #define MFI_LD_ACCESS_MASK      3
1120
1121 enum mfi_ld_state {
1122     MFI_LD_STATE_OFFLINE =              0,
1123     MFI_LD_STATE_PARTIALLY_DEGRADED =   1,
1124     MFI_LD_STATE_DEGRADED =             2,
1125     MFI_LD_STATE_OPTIMAL =              3
1126 };
1127
1128 enum mfi_syspd_state {
1129     MFI_PD_STATE_UNCONFIGURED_GOOD =    0x00,
1130     MFI_PD_STATE_UNCONFIGURED_BAD =     0x01,
1131     MFI_PD_STATE_HOT_SPARE =            0x02,
1132     MFI_PD_STATE_OFFLINE =              0x10,
1133     MFI_PD_STATE_FAILED =               0x11,
1134     MFI_PD_STATE_REBUILD =              0x14,
1135     MFI_PD_STATE_ONLINE =               0x18,
1136     MFI_PD_STATE_COPYBACK =             0x20,
1137     MFI_PD_STATE_SYSTEM =               0x40
1138 };
1139
1140 struct mfi_ld_props {
1141     union mfi_ld_ref ld;
1142     char name[16];
1143     uint8_t default_cache_policy;
1144     uint8_t access_policy;
1145     uint8_t disk_cache_policy;
1146     uint8_t current_cache_policy;
1147     uint8_t no_bgi;
1148     uint8_t reserved[7];
1149 } QEMU_PACKED;
1150
1151 struct mfi_ld_params {
1152     uint8_t primary_raid_level;
1153     uint8_t raid_level_qualifier;
1154     uint8_t secondary_raid_level;
1155     uint8_t stripe_size;
1156     uint8_t num_drives;
1157     uint8_t span_depth;
1158     uint8_t state;
1159     uint8_t init_state;
1160     uint8_t is_consistent;
1161     uint8_t reserved[23];
1162 } QEMU_PACKED;
1163
1164 struct mfi_ld_progress {
1165     uint32_t            active;
1166 #define MFI_LD_PROGRESS_CC      (1<<0)
1167 #define MFI_LD_PROGRESS_BGI     (1<<1)
1168 #define MFI_LD_PROGRESS_FGI     (1<<2)
1169 #define MFI_LD_PORGRESS_RECON   (1<<3)
1170     struct mfi_progress cc;
1171     struct mfi_progress bgi;
1172     struct mfi_progress fgi;
1173     struct mfi_progress recon;
1174     struct mfi_progress reserved[4];
1175 } QEMU_PACKED;
1176
1177 struct mfi_span {
1178     uint64_t start_block;
1179     uint64_t num_blocks;
1180     uint16_t array_ref;
1181     uint8_t reserved[6];
1182 } QEMU_PACKED;
1183
1184 #define MFI_MAX_SPAN_DEPTH      8
1185 struct mfi_ld_config {
1186     struct mfi_ld_props properties;
1187     struct mfi_ld_params params;
1188     struct mfi_span span[MFI_MAX_SPAN_DEPTH];
1189 } QEMU_PACKED;
1190
1191 struct mfi_ld_info {
1192     struct mfi_ld_config ld_config;
1193     uint64_t size;
1194     struct mfi_ld_progress progress;
1195     uint16_t cluster_owner;
1196     uint8_t reconstruct_active;
1197     uint8_t reserved1[1];
1198     uint8_t vpd_page83[64];
1199     uint8_t reserved2[16];
1200 } QEMU_PACKED;
1201
1202 union mfi_spare_type {
1203     uint8_t flags;
1204 #define MFI_SPARE_IS_DEDICATED (1 << 0)
1205 #define MFI_SPARE_IS_REVERTABLE (1 << 1)
1206 #define MFI_SPARE_IS_ENCL_AFFINITY (1 << 2)
1207     uint8_t type;
1208 } QEMU_PACKED;
1209
1210 #define MFI_MAX_ARRAYS 16
1211 struct mfi_spare {
1212     union mfi_pd_ref ref;
1213     union mfi_spare_type spare_type;
1214     uint8_t reserved[2];
1215     uint8_t array_count;
1216     uint16_t array_refd[MFI_MAX_ARRAYS];
1217 } QEMU_PACKED;
1218
1219 #define MFI_MAX_ROW_SIZE 32
1220 struct mfi_array {
1221     uint64_t size;
1222     uint8_t num_drives;
1223     uint8_t reserved;
1224     uint16_t array_ref;
1225     uint8_t pad[20];
1226     struct {
1227         union mfi_pd_ref ref;
1228         uint16_t fw_state; /* enum mfi_syspd_state */
1229         struct {
1230             uint8_t pd;
1231             uint8_t slot;
1232         } encl;
1233     } pd[MFI_MAX_ROW_SIZE];
1234 } QEMU_PACKED;
1235
1236 struct mfi_config_data {
1237     uint32_t size;
1238     uint16_t array_count;
1239     uint16_t array_size;
1240     uint16_t log_drv_count;
1241     uint16_t log_drv_size;
1242     uint16_t spares_count;
1243     uint16_t spares_size;
1244     uint8_t reserved[16];
1245     /*
1246       struct mfi_array  array[];
1247       struct mfi_ld_config ld[];
1248       struct mfi_spare  spare[];
1249     */
1250 } QEMU_PACKED;
1251
1252 #define MFI_SCSI_MAX_TARGETS  128
1253 #define MFI_SCSI_MAX_LUNS       8
1254 #define MFI_SCSI_INITIATOR_ID 255
1255 #define MFI_SCSI_MAX_CMDS       8
1256 #define MFI_SCSI_MAX_CDB_LEN   16
1257
1258 #endif /* MFI_REG_H */