hw/arm/musicpal.c

   1 /*
   2  * Marvell MV88W8618 / Freecom MusicPal emulation.
   3  *
   4  * Copyright (c) 2008 Jan Kiszka
   5  *
   6  * This code is licensed under the GNU GPL v2.
   7  *
   8  * Contributions after 2012-01-13 are licensed under the terms of the
   9  * GNU GPL, version 2 or (at your option) any later version.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "qapi/error.h"
  14 #include "qemu-common.h"
  15 #include "cpu.h"
  16 #include "hw/sysbus.h"
  17 #include "hw/arm/arm.h"
  18 #include "hw/devices.h"
  19 #include "net/net.h"
  20 #include "sysemu/sysemu.h"
  21 #include "hw/boards.h"
  22 #include "hw/char/serial.h"
  23 #include "qemu/timer.h"
  24 #include "hw/ptimer.h"
  25 #include "hw/block/flash.h"
  26 #include "ui/console.h"
  27 #include "hw/i2c/i2c.h"
  28 #include "sysemu/block-backend.h"
  29 #include "exec/address-spaces.h"
  30 #include "ui/pixel_ops.h"
  31
  32 #define MP_MISC_BASE            0x80002000
  33 #define MP_MISC_SIZE            0x00001000
  34
  35 #define MP_ETH_BASE             0x80008000
  36 #define MP_ETH_SIZE             0x00001000
  37
  38 #define MP_WLAN_BASE            0x8000C000
  39 #define MP_WLAN_SIZE            0x00000800
  40
  41 #define MP_UART1_BASE           0x8000C840
  42 #define MP_UART2_BASE           0x8000C940
  43
  44 #define MP_GPIO_BASE            0x8000D000
  45 #define MP_GPIO_SIZE            0x00001000
  46
  47 #define MP_FLASHCFG_BASE        0x90006000
  48 #define MP_FLASHCFG_SIZE        0x00001000
  49
  50 #define MP_AUDIO_BASE           0x90007000
  51
  52 #define MP_PIC_BASE             0x90008000
  53 #define MP_PIC_SIZE             0x00001000
  54
  55 #define MP_PIT_BASE             0x90009000
  56 #define MP_PIT_SIZE             0x00001000
  57
  58 #define MP_LCD_BASE             0x9000c000
  59 #define MP_LCD_SIZE             0x00001000
  60
  61 #define MP_SRAM_BASE            0xC0000000
  62 #define MP_SRAM_SIZE            0x00020000
  63
  64 #define MP_RAM_DEFAULT_SIZE     32*1024*1024
  65 #define MP_FLASH_SIZE_MAX       32*1024*1024
  66
  67 #define MP_TIMER1_IRQ           4
  68 #define MP_TIMER2_IRQ           5
  69 #define MP_TIMER3_IRQ           6
  70 #define MP_TIMER4_IRQ           7
  71 #define MP_EHCI_IRQ             8
  72 #define MP_ETH_IRQ              9
  73 #define MP_UART1_IRQ            11
  74 #define MP_UART2_IRQ            11
  75 #define MP_GPIO_IRQ             12
  76 #define MP_RTC_IRQ              28
  77 #define MP_AUDIO_IRQ            30
  78
  79 /* Wolfson 8750 I2C address */
  80 #define MP_WM_ADDR              0x1A
  81
  82 /* Ethernet register offsets */
  83 #define MP_ETH_SMIR             0x010
  84 #define MP_ETH_PCXR             0x408
  85 #define MP_ETH_SDCMR            0x448
  86 #define MP_ETH_ICR              0x450
  87 #define MP_ETH_IMR              0x458
  88 #define MP_ETH_FRDP0            0x480
  89 #define MP_ETH_FRDP1            0x484
  90 #define MP_ETH_FRDP2            0x488
  91 #define MP_ETH_FRDP3            0x48C
  92 #define MP_ETH_CRDP0            0x4A0
  93 #define MP_ETH_CRDP1            0x4A4
  94 #define MP_ETH_CRDP2            0x4A8
  95 #define MP_ETH_CRDP3            0x4AC
  96 #define MP_ETH_CTDP0            0x4E0
  97 #define MP_ETH_CTDP1            0x4E4
  98
  99 /* MII PHY access */
 100 #define MP_ETH_SMIR_DATA        0x0000FFFF
 101 #define MP_ETH_SMIR_ADDR        0x03FF0000
 102 #define MP_ETH_SMIR_OPCODE      (1 << 26) /* Read value */
 103 #define MP_ETH_SMIR_RDVALID     (1 << 27)
 104
 105 /* PHY registers */
 106 #define MP_ETH_PHY1_BMSR        0x00210000
 107 #define MP_ETH_PHY1_PHYSID1     0x00410000
 108 #define MP_ETH_PHY1_PHYSID2     0x00610000
 109
 110 #define MP_PHY_BMSR_LINK        0x0004
 111 #define MP_PHY_BMSR_AUTONEG     0x0008
 112
 113 #define MP_PHY_88E3015          0x01410E20
 114
 115 /* TX descriptor status */
 116 #define MP_ETH_TX_OWN           (1U << 31)
 117
 118 /* RX descriptor status */
 119 #define MP_ETH_RX_OWN           (1U << 31)
 120
 121 /* Interrupt cause/mask bits */
 122 #define MP_ETH_IRQ_RX_BIT       0
 123 #define MP_ETH_IRQ_RX           (1 << MP_ETH_IRQ_RX_BIT)
 124 #define MP_ETH_IRQ_TXHI_BIT     2
 125 #define MP_ETH_IRQ_TXLO_BIT     3
 126
 127 /* Port config bits */
 128 #define MP_ETH_PCXR_2BSM_BIT    28 /* 2-byte incoming suffix */
 129
 130 /* SDMA command bits */
 131 #define MP_ETH_CMD_TXHI         (1 << 23)
 132 #define MP_ETH_CMD_TXLO         (1 << 22)
 133
 134 typedef struct mv88w8618_tx_desc {
 135     uint32_t cmdstat;
 136     uint16_t res;
 137     uint16_t bytes;
 138     uint32_t buffer;
 139     uint32_t next;
 140 } mv88w8618_tx_desc;
 141
 142 typedef struct mv88w8618_rx_desc {
 143     uint32_t cmdstat;
 144     uint16_t bytes;
 145     uint16_t buffer_size;
 146     uint32_t buffer;
 147     uint32_t next;
 148 } mv88w8618_rx_desc;
 149
 150 #define TYPE_MV88W8618_ETH "mv88w8618_eth"
 151 #define MV88W8618_ETH(obj) \
 152     OBJECT_CHECK(mv88w8618_eth_state, (obj), TYPE_MV88W8618_ETH)
 153
 154 typedef struct mv88w8618_eth_state {
 155     /*< private >*/
 156     SysBusDevice parent_obj;
 157     /*< public >*/
 158
 159     MemoryRegion iomem;
 160     qemu_irq irq;
 161     uint32_t smir;
 162     uint32_t icr;
 163     uint32_t imr;
 164     int mmio_index;
 165     uint32_t vlan_header;
 166     uint32_t tx_queue[2];
 167     uint32_t rx_queue[4];
 168     uint32_t frx_queue[4];
 169     uint32_t cur_rx[4];
 170     NICState *nic;
 171     NICConf conf;
 172 } mv88w8618_eth_state;
 173
 174 static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
 175 {
 176     cpu_to_le32s(&desc->cmdstat);
 177     cpu_to_le16s(&desc->bytes);
 178     cpu_to_le16s(&desc->buffer_size);
 179     cpu_to_le32s(&desc->buffer);
 180     cpu_to_le32s(&desc->next);
 181     cpu_physical_memory_write(addr, desc, sizeof(*desc));
 182 }
 183
 184 static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
 185 {
 186     cpu_physical_memory_read(addr, desc, sizeof(*desc));
 187     le32_to_cpus(&desc->cmdstat);
 188     le16_to_cpus(&desc->bytes);
 189     le16_to_cpus(&desc->buffer_size);
 190     le32_to_cpus(&desc->buffer);
 191     le32_to_cpus(&desc->next);
 192 }
 193
 194 static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size)
 195 {
 196     mv88w8618_eth_state *s = qemu_get_nic_opaque(nc);
 197     uint32_t desc_addr;
 198     mv88w8618_rx_desc desc;
 199     int i;
 200
 201     for (i = 0; i < 4; i++) {
 202         desc_addr = s->cur_rx[i];
 203         if (!desc_addr) {
 204             continue;
 205         }
 206         do {
 207             eth_rx_desc_get(desc_addr, &desc);
 208             if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
 209                 cpu_physical_memory_write(desc.buffer + s->vlan_header,
 210                                           buf, size);
 211                 desc.bytes = size + s->vlan_header;
 212                 desc.cmdstat &= ~MP_ETH_RX_OWN;
 213                 s->cur_rx[i] = desc.next;
 214
 215                 s->icr |= MP_ETH_IRQ_RX;
 216                 if (s->icr & s->imr) {
 217                     qemu_irq_raise(s->irq);
 218                 }
 219                 eth_rx_desc_put(desc_addr, &desc);
 220                 return size;
 221             }
 222             desc_addr = desc.next;
 223         } while (desc_addr != s->rx_queue[i]);
 224     }
 225     return size;
 226 }
 227
 228 static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
 229 {
 230     cpu_to_le32s(&desc->cmdstat);
 231     cpu_to_le16s(&desc->res);
 232     cpu_to_le16s(&desc->bytes);
 233     cpu_to_le32s(&desc->buffer);
 234     cpu_to_le32s(&desc->next);
 235     cpu_physical_memory_write(addr, desc, sizeof(*desc));
 236 }
 237
 238 static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
 239 {
 240     cpu_physical_memory_read(addr, desc, sizeof(*desc));
 241     le32_to_cpus(&desc->cmdstat);
 242     le16_to_cpus(&desc->res);
 243     le16_to_cpus(&desc->bytes);
 244     le32_to_cpus(&desc->buffer);
 245     le32_to_cpus(&desc->next);
 246 }
 247
 248 static void eth_send(mv88w8618_eth_state *s, int queue_index)
 249 {
 250     uint32_t desc_addr = s->tx_queue[queue_index];
 251     mv88w8618_tx_desc desc;
 252     uint32_t next_desc;
 253     uint8_t buf[2048];
 254     int len;
 255
 256     do {
 257         eth_tx_desc_get(desc_addr, &desc);
 258         next_desc = desc.next;
 259         if (desc.cmdstat & MP_ETH_TX_OWN) {
 260             len = desc.bytes;
 261             if (len < 2048) {
 262                 cpu_physical_memory_read(desc.buffer, buf, len);
 263                 qemu_send_packet(qemu_get_queue(s->nic), buf, len);
 264             }
 265             desc.cmdstat &= ~MP_ETH_TX_OWN;
 266             s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
 267             eth_tx_desc_put(desc_addr, &desc);
 268         }
 269         desc_addr = next_desc;
 270     } while (desc_addr != s->tx_queue[queue_index]);
 271 }
 272
 273 static uint64_t mv88w8618_eth_read(void *opaque, hwaddr offset,
 274                                    unsigned size)
 275 {
 276     mv88w8618_eth_state *s = opaque;
 277
 278     switch (offset) {
 279     case MP_ETH_SMIR:
 280         if (s->smir & MP_ETH_SMIR_OPCODE) {
 281             switch (s->smir & MP_ETH_SMIR_ADDR) {
 282             case MP_ETH_PHY1_BMSR:
 283                 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
 284                        MP_ETH_SMIR_RDVALID;
 285             case MP_ETH_PHY1_PHYSID1:
 286                 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
 287             case MP_ETH_PHY1_PHYSID2:
 288                 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
 289             default:
 290                 return MP_ETH_SMIR_RDVALID;
 291             }
 292         }
 293         return 0;
 294
 295     case MP_ETH_ICR:
 296         return s->icr;
 297
 298     case MP_ETH_IMR:
 299         return s->imr;
 300
 301     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 302         return s->frx_queue[(offset - MP_ETH_FRDP0)/4];
 303
 304     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 305         return s->rx_queue[(offset - MP_ETH_CRDP0)/4];
 306
 307     case MP_ETH_CTDP0 ... MP_ETH_CTDP1:
 308         return s->tx_queue[(offset - MP_ETH_CTDP0)/4];
 309
 310     default:
 311         return 0;
 312     }
 313 }
 314
 315 static void mv88w8618_eth_write(void *opaque, hwaddr offset,
 316                                 uint64_t value, unsigned size)
 317 {
 318     mv88w8618_eth_state *s = opaque;
 319
 320     switch (offset) {
 321     case MP_ETH_SMIR:
 322         s->smir = value;
 323         break;
 324
 325     case MP_ETH_PCXR:
 326         s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
 327         break;
 328
 329     case MP_ETH_SDCMR:
 330         if (value & MP_ETH_CMD_TXHI) {
 331             eth_send(s, 1);
 332         }
 333         if (value & MP_ETH_CMD_TXLO) {
 334             eth_send(s, 0);
 335         }
 336         if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) {
 337             qemu_irq_raise(s->irq);
 338         }
 339         break;
 340
 341     case MP_ETH_ICR:
 342         s->icr &= value;
 343         break;
 344
 345     case MP_ETH_IMR:
 346         s->imr = value;
 347         if (s->icr & s->imr) {
 348             qemu_irq_raise(s->irq);
 349         }
 350         break;
 351
 352     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 353         s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
 354         break;
 355
 356     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 357         s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
 358             s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
 359         break;
 360
 361     case MP_ETH_CTDP0 ... MP_ETH_CTDP1:
 362         s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
 363         break;
 364     }
 365 }
 366
 367 static const MemoryRegionOps mv88w8618_eth_ops = {
 368     .read = mv88w8618_eth_read,
 369     .write = mv88w8618_eth_write,
 370     .endianness = DEVICE_NATIVE_ENDIAN,
 371 };
 372
 373 static void eth_cleanup(NetClientState *nc)
 374 {
 375     mv88w8618_eth_state *s = qemu_get_nic_opaque(nc);
 376
 377     s->nic = NULL;
 378 }
 379
 380 static NetClientInfo net_mv88w8618_info = {
 381     .type = NET_CLIENT_DRIVER_NIC,
 382     .size = sizeof(NICState),
 383     .receive = eth_receive,
 384     .cleanup = eth_cleanup,
 385 };
 386
 387 static void mv88w8618_eth_init(Object *obj)
 388 {
 389     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 390     DeviceState *dev = DEVICE(sbd);
 391     mv88w8618_eth_state *s = MV88W8618_ETH(dev);
 392
 393     sysbus_init_irq(sbd, &s->irq);
 394     memory_region_init_io(&s->iomem, obj, &mv88w8618_eth_ops, s,
 395                           "mv88w8618-eth", MP_ETH_SIZE);
 396     sysbus_init_mmio(sbd, &s->iomem);
 397 }
 398
 399 static void mv88w8618_eth_realize(DeviceState *dev, Error **errp)
 400 {
 401     mv88w8618_eth_state *s = MV88W8618_ETH(dev);
 402
 403     s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
 404                           object_get_typename(OBJECT(dev)), dev->id, s);
 405 }
 406
 407 static const VMStateDescription mv88w8618_eth_vmsd = {
 408     .name = "mv88w8618_eth",
 409     .version_id = 1,
 410     .minimum_version_id = 1,
 411     .fields = (VMStateField[]) {
 412         VMSTATE_UINT32(smir, mv88w8618_eth_state),
 413         VMSTATE_UINT32(icr, mv88w8618_eth_state),
 414         VMSTATE_UINT32(imr, mv88w8618_eth_state),
 415         VMSTATE_UINT32(vlan_header, mv88w8618_eth_state),
 416         VMSTATE_UINT32_ARRAY(tx_queue, mv88w8618_eth_state, 2),
 417         VMSTATE_UINT32_ARRAY(rx_queue, mv88w8618_eth_state, 4),
 418         VMSTATE_UINT32_ARRAY(frx_queue, mv88w8618_eth_state, 4),
 419         VMSTATE_UINT32_ARRAY(cur_rx, mv88w8618_eth_state, 4),
 420         VMSTATE_END_OF_LIST()
 421     }
 422 };
 423
 424 static Property mv88w8618_eth_properties[] = {
 425     DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf),
 426     DEFINE_PROP_END_OF_LIST(),
 427 };
 428
 429 static void mv88w8618_eth_class_init(ObjectClass *klass, void *data)
 430 {
 431     DeviceClass *dc = DEVICE_CLASS(klass);
 432
 433     dc->vmsd = &mv88w8618_eth_vmsd;
 434     dc->props = mv88w8618_eth_properties;
 435     dc->realize = mv88w8618_eth_realize;
 436 }
 437
 438 static const TypeInfo mv88w8618_eth_info = {
 439     .name          = TYPE_MV88W8618_ETH,
 440     .parent        = TYPE_SYS_BUS_DEVICE,
 441     .instance_size = sizeof(mv88w8618_eth_state),
 442     .instance_init = mv88w8618_eth_init,
 443     .class_init    = mv88w8618_eth_class_init,
 444 };
 445
 446 /* LCD register offsets */
 447 #define MP_LCD_IRQCTRL          0x180
 448 #define MP_LCD_IRQSTAT          0x184
 449 #define MP_LCD_SPICTRL          0x1ac
 450 #define MP_LCD_INST             0x1bc
 451 #define MP_LCD_DATA             0x1c0
 452
 453 /* Mode magics */
 454 #define MP_LCD_SPI_DATA         0x00100011
 455 #define MP_LCD_SPI_CMD          0x00104011
 456 #define MP_LCD_SPI_INVALID      0x00000000
 457
 458 /* Commmands */
 459 #define MP_LCD_INST_SETPAGE0    0xB0
 460 /* ... */
 461 #define MP_LCD_INST_SETPAGE7    0xB7
 462
 463 #define MP_LCD_TEXTCOLOR        0xe0e0ff /* RRGGBB */
 464
 465 #define TYPE_MUSICPAL_LCD "musicpal_lcd"
 466 #define MUSICPAL_LCD(obj) \
 467     OBJECT_CHECK(musicpal_lcd_state, (obj), TYPE_MUSICPAL_LCD)
 468
 469 typedef struct musicpal_lcd_state {
 470     /*< private >*/
 471     SysBusDevice parent_obj;
 472     /*< public >*/
 473
 474     MemoryRegion iomem;
 475     uint32_t brightness;
 476     uint32_t mode;
 477     uint32_t irqctrl;
 478     uint32_t page;
 479     uint32_t page_off;
 480     QemuConsole *con;
 481     uint8_t video_ram[128*64/8];
 482 } musicpal_lcd_state;
 483
 484 static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col)
 485 {
 486     switch (s->brightness) {
 487     case 7:
 488         return col;
 489     case 0:
 490         return 0;
 491     default:
 492         return (col * s->brightness) / 7;
 493     }
 494 }
 495
 496 #define SET_LCD_PIXEL(depth, type) \
 497 static inline void glue(set_lcd_pixel, depth) \
 498         (musicpal_lcd_state *s, int x, int y, type col) \
 499 { \
 500     int dx, dy; \
 501     DisplaySurface *surface = qemu_console_surface(s->con); \
 502     type *pixel = &((type *) surface_data(surface))[(y * 128 * 3 + x) * 3]; \
 503 \
 504     for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
 505         for (dx = 0; dx < 3; dx++, pixel++) \
 506             *pixel = col; \
 507 }
 508 SET_LCD_PIXEL(8, uint8_t)
 509 SET_LCD_PIXEL(16, uint16_t)
 510 SET_LCD_PIXEL(32, uint32_t)
 511
 512 static void lcd_refresh(void *opaque)
 513 {
 514     musicpal_lcd_state *s = opaque;
 515     DisplaySurface *surface = qemu_console_surface(s->con);
 516     int x, y, col;
 517
 518     switch (surface_bits_per_pixel(surface)) {
 519     case 0:
 520         return;
 521 #define LCD_REFRESH(depth, func) \
 522     case depth: \
 523         col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \
 524                    scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \
 525                    scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
 526         for (x = 0; x < 128; x++) { \
 527             for (y = 0; y < 64; y++) { \
 528                 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \
 529                     glue(set_lcd_pixel, depth)(s, x, y, col); \
 530                 } else { \
 531                     glue(set_lcd_pixel, depth)(s, x, y, 0); \
 532                 } \
 533             } \
 534         } \
 535         break;
 536     LCD_REFRESH(8, rgb_to_pixel8)
 537     LCD_REFRESH(16, rgb_to_pixel16)
 538     LCD_REFRESH(32, (is_surface_bgr(surface) ?
 539                      rgb_to_pixel32bgr : rgb_to_pixel32))
 540     default:
 541         hw_error("unsupported colour depth %i\n",
 542                  surface_bits_per_pixel(surface));
 543     }
 544
 545     dpy_gfx_update(s->con, 0, 0, 128*3, 64*3);
 546 }
 547
 548 static void lcd_invalidate(void *opaque)
 549 {
 550 }
 551
 552 static void musicpal_lcd_gpio_brightness_in(void *opaque, int irq, int level)
 553 {
 554     musicpal_lcd_state *s = opaque;
 555     s->brightness &= ~(1 << irq);
 556     s->brightness |= level << irq;
 557 }
 558
 559 static uint64_t musicpal_lcd_read(void *opaque, hwaddr offset,
 560                                   unsigned size)
 561 {
 562     musicpal_lcd_state *s = opaque;
 563
 564     switch (offset) {
 565     case MP_LCD_IRQCTRL:
 566         return s->irqctrl;
 567
 568     default:
 569         return 0;
 570     }
 571 }
 572
 573 static void musicpal_lcd_write(void *opaque, hwaddr offset,
 574                                uint64_t value, unsigned size)
 575 {
 576     musicpal_lcd_state *s = opaque;
 577
 578     switch (offset) {
 579     case MP_LCD_IRQCTRL:
 580         s->irqctrl = value;
 581         break;
 582
 583     case MP_LCD_SPICTRL:
 584         if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) {
 585             s->mode = value;
 586         } else {
 587             s->mode = MP_LCD_SPI_INVALID;
 588         }
 589         break;
 590
 591     case MP_LCD_INST:
 592         if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
 593             s->page = value - MP_LCD_INST_SETPAGE0;
 594             s->page_off = 0;
 595         }
 596         break;
 597
 598     case MP_LCD_DATA:
 599         if (s->mode == MP_LCD_SPI_CMD) {
 600             if (value >= MP_LCD_INST_SETPAGE0 &&
 601                 value <= MP_LCD_INST_SETPAGE7) {
 602                 s->page = value - MP_LCD_INST_SETPAGE0;
 603                 s->page_off = 0;
 604             }
 605         } else if (s->mode == MP_LCD_SPI_DATA) {
 606             s->video_ram[s->page*128 + s->page_off] = value;
 607             s->page_off = (s->page_off + 1) & 127;
 608         }
 609         break;
 610     }
 611 }
 612
 613 static const MemoryRegionOps musicpal_lcd_ops = {
 614     .read = musicpal_lcd_read,
 615     .write = musicpal_lcd_write,
 616     .endianness = DEVICE_NATIVE_ENDIAN,
 617 };
 618
 619 static const GraphicHwOps musicpal_gfx_ops = {
 620     .invalidate  = lcd_invalidate,
 621     .gfx_update  = lcd_refresh,
 622 };
 623
 624 static void musicpal_lcd_realize(DeviceState *dev, Error **errp)
 625 {
 626     musicpal_lcd_state *s = MUSICPAL_LCD(dev);
 627     s->con = graphic_console_init(dev, 0, &musicpal_gfx_ops, s);
 628     qemu_console_resize(s->con, 128 * 3, 64 * 3);
 629 }
 630
 631 static void musicpal_lcd_init(Object *obj)
 632 {
 633     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 634     DeviceState *dev = DEVICE(sbd);
 635     musicpal_lcd_state *s = MUSICPAL_LCD(dev);
 636
 637     s->brightness = 7;
 638
 639     memory_region_init_io(&s->iomem, obj, &musicpal_lcd_ops, s,
 640                           "musicpal-lcd", MP_LCD_SIZE);
 641     sysbus_init_mmio(sbd, &s->iomem);
 642
 643     qdev_init_gpio_in(dev, musicpal_lcd_gpio_brightness_in, 3);
 644 }
 645
 646 static const VMStateDescription musicpal_lcd_vmsd = {
 647     .name = "musicpal_lcd",
 648     .version_id = 1,
 649     .minimum_version_id = 1,
 650     .fields = (VMStateField[]) {
 651         VMSTATE_UINT32(brightness, musicpal_lcd_state),
 652         VMSTATE_UINT32(mode, musicpal_lcd_state),
 653         VMSTATE_UINT32(irqctrl, musicpal_lcd_state),
 654         VMSTATE_UINT32(page, musicpal_lcd_state),
 655         VMSTATE_UINT32(page_off, musicpal_lcd_state),
 656         VMSTATE_BUFFER(video_ram, musicpal_lcd_state),
 657         VMSTATE_END_OF_LIST()
 658     }
 659 };
 660
 661 static void musicpal_lcd_class_init(ObjectClass *klass, void *data)
 662 {
 663     DeviceClass *dc = DEVICE_CLASS(klass);
 664
 665     dc->vmsd = &musicpal_lcd_vmsd;
 666     dc->realize = musicpal_lcd_realize;
 667 }
 668
 669 static const TypeInfo musicpal_lcd_info = {
 670     .name          = TYPE_MUSICPAL_LCD,
 671     .parent        = TYPE_SYS_BUS_DEVICE,
 672     .instance_size = sizeof(musicpal_lcd_state),
 673     .instance_init = musicpal_lcd_init,
 674     .class_init    = musicpal_lcd_class_init,
 675 };
 676
 677 /* PIC register offsets */
 678 #define MP_PIC_STATUS           0x00
 679 #define MP_PIC_ENABLE_SET       0x08
 680 #define MP_PIC_ENABLE_CLR       0x0C
 681
 682 #define TYPE_MV88W8618_PIC "mv88w8618_pic"
 683 #define MV88W8618_PIC(obj) \
 684     OBJECT_CHECK(mv88w8618_pic_state, (obj), TYPE_MV88W8618_PIC)
 685
 686 typedef struct mv88w8618_pic_state {
 687     /*< private >*/
 688     SysBusDevice parent_obj;
 689     /*< public >*/
 690
 691     MemoryRegion iomem;
 692     uint32_t level;
 693     uint32_t enabled;
 694     qemu_irq parent_irq;
 695 } mv88w8618_pic_state;
 696
 697 static void mv88w8618_pic_update(mv88w8618_pic_state *s)
 698 {
 699     qemu_set_irq(s->parent_irq, (s->level & s->enabled));
 700 }
 701
 702 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
 703 {
 704     mv88w8618_pic_state *s = opaque;
 705
 706     if (level) {
 707         s->level |= 1 << irq;
 708     } else {
 709         s->level &= ~(1 << irq);
 710     }
 711     mv88w8618_pic_update(s);
 712 }
 713
 714 static uint64_t mv88w8618_pic_read(void *opaque, hwaddr offset,
 715                                    unsigned size)
 716 {
 717     mv88w8618_pic_state *s = opaque;
 718
 719     switch (offset) {
 720     case MP_PIC_STATUS:
 721         return s->level & s->enabled;
 722
 723     default:
 724         return 0;
 725     }
 726 }
 727
 728 static void mv88w8618_pic_write(void *opaque, hwaddr offset,
 729                                 uint64_t value, unsigned size)
 730 {
 731     mv88w8618_pic_state *s = opaque;
 732
 733     switch (offset) {
 734     case MP_PIC_ENABLE_SET:
 735         s->enabled |= value;
 736         break;
 737
 738     case MP_PIC_ENABLE_CLR:
 739         s->enabled &= ~value;
 740         s->level &= ~value;
 741         break;
 742     }
 743     mv88w8618_pic_update(s);
 744 }
 745
 746 static void mv88w8618_pic_reset(DeviceState *d)
 747 {
 748     mv88w8618_pic_state *s = MV88W8618_PIC(d);
 749
 750     s->level = 0;
 751     s->enabled = 0;
 752 }
 753
 754 static const MemoryRegionOps mv88w8618_pic_ops = {
 755     .read = mv88w8618_pic_read,
 756     .write = mv88w8618_pic_write,
 757     .endianness = DEVICE_NATIVE_ENDIAN,
 758 };
 759
 760 static void mv88w8618_pic_init(Object *obj)
 761 {
 762     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 763     mv88w8618_pic_state *s = MV88W8618_PIC(dev);
 764
 765     qdev_init_gpio_in(DEVICE(dev), mv88w8618_pic_set_irq, 32);
 766     sysbus_init_irq(dev, &s->parent_irq);
 767     memory_region_init_io(&s->iomem, obj, &mv88w8618_pic_ops, s,
 768                           "musicpal-pic", MP_PIC_SIZE);
 769     sysbus_init_mmio(dev, &s->iomem);
 770 }
 771
 772 static const VMStateDescription mv88w8618_pic_vmsd = {
 773     .name = "mv88w8618_pic",
 774     .version_id = 1,
 775     .minimum_version_id = 1,
 776     .fields = (VMStateField[]) {
 777         VMSTATE_UINT32(level, mv88w8618_pic_state),
 778         VMSTATE_UINT32(enabled, mv88w8618_pic_state),
 779         VMSTATE_END_OF_LIST()
 780     }
 781 };
 782
 783 static void mv88w8618_pic_class_init(ObjectClass *klass, void *data)
 784 {
 785     DeviceClass *dc = DEVICE_CLASS(klass);
 786
 787     dc->reset = mv88w8618_pic_reset;
 788     dc->vmsd = &mv88w8618_pic_vmsd;
 789 }
 790
 791 static const TypeInfo mv88w8618_pic_info = {
 792     .name          = TYPE_MV88W8618_PIC,
 793     .parent        = TYPE_SYS_BUS_DEVICE,
 794     .instance_size = sizeof(mv88w8618_pic_state),
 795     .instance_init = mv88w8618_pic_init,
 796     .class_init    = mv88w8618_pic_class_init,
 797 };
 798
 799 /* PIT register offsets */
 800 #define MP_PIT_TIMER1_LENGTH    0x00
 801 /* ... */
 802 #define MP_PIT_TIMER4_LENGTH    0x0C
 803 #define MP_PIT_CONTROL          0x10
 804 #define MP_PIT_TIMER1_VALUE     0x14
 805 /* ... */
 806 #define MP_PIT_TIMER4_VALUE     0x20
 807 #define MP_BOARD_RESET          0x34
 808
 809 /* Magic board reset value (probably some watchdog behind it) */
 810 #define MP_BOARD_RESET_MAGIC    0x10000
 811
 812 typedef struct mv88w8618_timer_state {
 813     ptimer_state *ptimer;
 814     uint32_t limit;
 815     int freq;
 816     qemu_irq irq;
 817 } mv88w8618_timer_state;
 818
 819 #define TYPE_MV88W8618_PIT "mv88w8618_pit"
 820 #define MV88W8618_PIT(obj) \
 821     OBJECT_CHECK(mv88w8618_pit_state, (obj), TYPE_MV88W8618_PIT)
 822
 823 typedef struct mv88w8618_pit_state {
 824     /*< private >*/
 825     SysBusDevice parent_obj;
 826     /*< public >*/
 827
 828     MemoryRegion iomem;
 829     mv88w8618_timer_state timer[4];
 830 } mv88w8618_pit_state;
 831
 832 static void mv88w8618_timer_tick(void *opaque)
 833 {
 834     mv88w8618_timer_state *s = opaque;
 835
 836     qemu_irq_raise(s->irq);
 837 }
 838
 839 static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
 840                                  uint32_t freq)
 841 {
 842     QEMUBH *bh;
 843
 844     sysbus_init_irq(dev, &s->irq);
 845     s->freq = freq;
 846
 847     bh = qemu_bh_new(mv88w8618_timer_tick, s);
 848     s->ptimer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
 849 }
 850
 851 static uint64_t mv88w8618_pit_read(void *opaque, hwaddr offset,
 852                                    unsigned size)
 853 {
 854     mv88w8618_pit_state *s = opaque;
 855     mv88w8618_timer_state *t;
 856
 857     switch (offset) {
 858     case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
 859         t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
 860         return ptimer_get_count(t->ptimer);
 861
 862     default:
 863         return 0;
 864     }
 865 }
 866
 867 static void mv88w8618_pit_write(void *opaque, hwaddr offset,
 868                                 uint64_t value, unsigned size)
 869 {
 870     mv88w8618_pit_state *s = opaque;
 871     mv88w8618_timer_state *t;
 872     int i;
 873
 874     switch (offset) {
 875     case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
 876         t = &s->timer[offset >> 2];
 877         t->limit = value;
 878         if (t->limit > 0) {
 879             ptimer_set_limit(t->ptimer, t->limit, 1);
 880         } else {
 881             ptimer_stop(t->ptimer);
 882         }
 883         break;
 884
 885     case MP_PIT_CONTROL:
 886         for (i = 0; i < 4; i++) {
 887             t = &s->timer[i];
 888             if (value & 0xf && t->limit > 0) {
 889                 ptimer_set_limit(t->ptimer, t->limit, 0);
 890                 ptimer_set_freq(t->ptimer, t->freq);
 891                 ptimer_run(t->ptimer, 0);
 892             } else {
 893                 ptimer_stop(t->ptimer);
 894             }
 895             value >>= 4;
 896         }
 897         break;
 898
 899     case MP_BOARD_RESET:
 900         if (value == MP_BOARD_RESET_MAGIC) {
 901             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 902         }
 903         break;
 904     }
 905 }
 906
 907 static void mv88w8618_pit_reset(DeviceState *d)
 908 {
 909     mv88w8618_pit_state *s = MV88W8618_PIT(d);
 910     int i;
 911
 912     for (i = 0; i < 4; i++) {
 913         ptimer_stop(s->timer[i].ptimer);
 914         s->timer[i].limit = 0;
 915     }
 916 }
 917
 918 static const MemoryRegionOps mv88w8618_pit_ops = {
 919     .read = mv88w8618_pit_read,
 920     .write = mv88w8618_pit_write,
 921     .endianness = DEVICE_NATIVE_ENDIAN,
 922 };
 923
 924 static void mv88w8618_pit_init(Object *obj)
 925 {
 926     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 927     mv88w8618_pit_state *s = MV88W8618_PIT(dev);
 928     int i;
 929
 930     /* Letting them all run at 1 MHz is likely just a pragmatic
 931      * simplification. */
 932     for (i = 0; i < 4; i++) {
 933         mv88w8618_timer_init(dev, &s->timer[i], 1000000);
 934     }
 935
 936     memory_region_init_io(&s->iomem, obj, &mv88w8618_pit_ops, s,
 937                           "musicpal-pit", MP_PIT_SIZE);
 938     sysbus_init_mmio(dev, &s->iomem);
 939 }
 940
 941 static const VMStateDescription mv88w8618_timer_vmsd = {
 942     .name = "timer",
 943     .version_id = 1,
 944     .minimum_version_id = 1,
 945     .fields = (VMStateField[]) {
 946         VMSTATE_PTIMER(ptimer, mv88w8618_timer_state),
 947         VMSTATE_UINT32(limit, mv88w8618_timer_state),
 948         VMSTATE_END_OF_LIST()
 949     }
 950 };
 951
 952 static const VMStateDescription mv88w8618_pit_vmsd = {
 953     .name = "mv88w8618_pit",
 954     .version_id = 1,
 955     .minimum_version_id = 1,
 956     .fields = (VMStateField[]) {
 957         VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1,
 958                              mv88w8618_timer_vmsd, mv88w8618_timer_state),
 959         VMSTATE_END_OF_LIST()
 960     }
 961 };
 962
 963 static void mv88w8618_pit_class_init(ObjectClass *klass, void *data)
 964 {
 965     DeviceClass *dc = DEVICE_CLASS(klass);
 966
 967     dc->reset = mv88w8618_pit_reset;
 968     dc->vmsd = &mv88w8618_pit_vmsd;
 969 }
 970
 971 static const TypeInfo mv88w8618_pit_info = {
 972     .name          = TYPE_MV88W8618_PIT,
 973     .parent        = TYPE_SYS_BUS_DEVICE,
 974     .instance_size = sizeof(mv88w8618_pit_state),
 975     .instance_init = mv88w8618_pit_init,
 976     .class_init    = mv88w8618_pit_class_init,
 977 };
 978
 979 /* Flash config register offsets */
 980 #define MP_FLASHCFG_CFGR0    0x04
 981
 982 #define TYPE_MV88W8618_FLASHCFG "mv88w8618_flashcfg"
 983 #define MV88W8618_FLASHCFG(obj) \
 984     OBJECT_CHECK(mv88w8618_flashcfg_state, (obj), TYPE_MV88W8618_FLASHCFG)
 985
 986 typedef struct mv88w8618_flashcfg_state {
 987     /*< private >*/
 988     SysBusDevice parent_obj;
 989     /*< public >*/
 990
 991     MemoryRegion iomem;
 992     uint32_t cfgr0;
 993 } mv88w8618_flashcfg_state;
 994
 995 static uint64_t mv88w8618_flashcfg_read(void *opaque,
 996                                         hwaddr offset,
 997                                         unsigned size)
 998 {
 999     mv88w8618_flashcfg_state *s = opaque;
1000
1001     switch (offset) {
1002     case MP_FLASHCFG_CFGR0:
1003         return s->cfgr0;
1004
1005     default:
1006         return 0;
1007     }
1008 }
1009
1010 static void mv88w8618_flashcfg_write(void *opaque, hwaddr offset,
1011                                      uint64_t value, unsigned size)
1012 {
1013     mv88w8618_flashcfg_state *s = opaque;
1014
1015     switch (offset) {
1016     case MP_FLASHCFG_CFGR0:
1017         s->cfgr0 = value;
1018         break;
1019     }
1020 }
1021
1022 static const MemoryRegionOps mv88w8618_flashcfg_ops = {
1023     .read = mv88w8618_flashcfg_read,
1024     .write = mv88w8618_flashcfg_write,
1025     .endianness = DEVICE_NATIVE_ENDIAN,
1026 };
1027
1028 static void mv88w8618_flashcfg_init(Object *obj)
1029 {
1030     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
1031     mv88w8618_flashcfg_state *s = MV88W8618_FLASHCFG(dev);
1032
1033     s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
1034     memory_region_init_io(&s->iomem, obj, &mv88w8618_flashcfg_ops, s,
1035                           "musicpal-flashcfg", MP_FLASHCFG_SIZE);
1036     sysbus_init_mmio(dev, &s->iomem);
1037 }
1038
1039 static const VMStateDescription mv88w8618_flashcfg_vmsd = {
1040     .name = "mv88w8618_flashcfg",
1041     .version_id = 1,
1042     .minimum_version_id = 1,
1043     .fields = (VMStateField[]) {
1044         VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state),
1045         VMSTATE_END_OF_LIST()
1046     }
1047 };
1048
1049 static void mv88w8618_flashcfg_class_init(ObjectClass *klass, void *data)
1050 {
1051     DeviceClass *dc = DEVICE_CLASS(klass);
1052
1053     dc->vmsd = &mv88w8618_flashcfg_vmsd;
1054 }
1055
1056 static const TypeInfo mv88w8618_flashcfg_info = {
1057     .name          = TYPE_MV88W8618_FLASHCFG,
1058     .parent        = TYPE_SYS_BUS_DEVICE,
1059     .instance_size = sizeof(mv88w8618_flashcfg_state),
1060     .instance_init = mv88w8618_flashcfg_init,
1061     .class_init    = mv88w8618_flashcfg_class_init,
1062 };
1063
1064 /* Misc register offsets */
1065 #define MP_MISC_BOARD_REVISION  0x18
1066
1067 #define MP_BOARD_REVISION       0x31
1068
1069 typedef struct {
1070     SysBusDevice parent_obj;
1071     MemoryRegion iomem;
1072 } MusicPalMiscState;
1073
1074 #define TYPE_MUSICPAL_MISC "musicpal-misc"
1075 #define MUSICPAL_MISC(obj) \
1076      OBJECT_CHECK(MusicPalMiscState, (obj), TYPE_MUSICPAL_MISC)
1077
1078 static uint64_t musicpal_misc_read(void *opaque, hwaddr offset,
1079                                    unsigned size)
1080 {
1081     switch (offset) {
1082     case MP_MISC_BOARD_REVISION:
1083         return MP_BOARD_REVISION;
1084
1085     default:
1086         return 0;
1087     }
1088 }
1089
1090 static void musicpal_misc_write(void *opaque, hwaddr offset,
1091                                 uint64_t value, unsigned size)
1092 {
1093 }
1094
1095 static const MemoryRegionOps musicpal_misc_ops = {
1096     .read = musicpal_misc_read,
1097     .write = musicpal_misc_write,
1098     .endianness = DEVICE_NATIVE_ENDIAN,
1099 };
1100
1101 static void musicpal_misc_init(Object *obj)
1102 {
1103     SysBusDevice *sd = SYS_BUS_DEVICE(obj);
1104     MusicPalMiscState *s = MUSICPAL_MISC(obj);
1105
1106     memory_region_init_io(&s->iomem, OBJECT(s), &musicpal_misc_ops, NULL,
1107                           "musicpal-misc", MP_MISC_SIZE);
1108     sysbus_init_mmio(sd, &s->iomem);
1109 }
1110
1111 static const TypeInfo musicpal_misc_info = {
1112     .name = TYPE_MUSICPAL_MISC,
1113     .parent = TYPE_SYS_BUS_DEVICE,
1114     .instance_init = musicpal_misc_init,
1115     .instance_size = sizeof(MusicPalMiscState),
1116 };
1117
1118 /* WLAN register offsets */
1119 #define MP_WLAN_MAGIC1          0x11c
1120 #define MP_WLAN_MAGIC2          0x124
1121
1122 static uint64_t mv88w8618_wlan_read(void *opaque, hwaddr offset,
1123                                     unsigned size)
1124 {
1125     switch (offset) {
1126     /* Workaround to allow loading the binary-only wlandrv.ko crap
1127      * from the original Freecom firmware. */
1128     case MP_WLAN_MAGIC1:
1129         return ~3;
1130     case MP_WLAN_MAGIC2:
1131         return -1;
1132
1133     default:
1134         return 0;
1135     }
1136 }
1137
1138 static void mv88w8618_wlan_write(void *opaque, hwaddr offset,
1139                                  uint64_t value, unsigned size)
1140 {
1141 }
1142
1143 static const MemoryRegionOps mv88w8618_wlan_ops = {
1144     .read = mv88w8618_wlan_read,
1145     .write =mv88w8618_wlan_write,
1146     .endianness = DEVICE_NATIVE_ENDIAN,
1147 };
1148
1149 static int mv88w8618_wlan_init(SysBusDevice *dev)
1150 {
1151     MemoryRegion *iomem = g_new(MemoryRegion, 1);
1152
1153     memory_region_init_io(iomem, OBJECT(dev), &mv88w8618_wlan_ops, NULL,
1154                           "musicpal-wlan", MP_WLAN_SIZE);
1155     sysbus_init_mmio(dev, iomem);
1156     return 0;
1157 }
1158
1159 /* GPIO register offsets */
1160 #define MP_GPIO_OE_LO           0x008
1161 #define MP_GPIO_OUT_LO          0x00c
1162 #define MP_GPIO_IN_LO           0x010
1163 #define MP_GPIO_IER_LO          0x014
1164 #define MP_GPIO_IMR_LO          0x018
1165 #define MP_GPIO_ISR_LO          0x020
1166 #define MP_GPIO_OE_HI           0x508
1167 #define MP_GPIO_OUT_HI          0x50c
1168 #define MP_GPIO_IN_HI           0x510
1169 #define MP_GPIO_IER_HI          0x514
1170 #define MP_GPIO_IMR_HI          0x518
1171 #define MP_GPIO_ISR_HI          0x520
1172
1173 /* GPIO bits & masks */
1174 #define MP_GPIO_LCD_BRIGHTNESS  0x00070000
1175 #define MP_GPIO_I2C_DATA_BIT    29
1176 #define MP_GPIO_I2C_CLOCK_BIT   30
1177
1178 /* LCD brightness bits in GPIO_OE_HI */
1179 #define MP_OE_LCD_BRIGHTNESS    0x0007
1180
1181 #define TYPE_MUSICPAL_GPIO "musicpal_gpio"
1182 #define MUSICPAL_GPIO(obj) \
1183     OBJECT_CHECK(musicpal_gpio_state, (obj), TYPE_MUSICPAL_GPIO)
1184
1185 typedef struct musicpal_gpio_state {
1186     /*< private >*/
1187     SysBusDevice parent_obj;
1188     /*< public >*/
1189
1190     MemoryRegion iomem;
1191     uint32_t lcd_brightness;
1192     uint32_t out_state;
1193     uint32_t in_state;
1194     uint32_t ier;
1195     uint32_t imr;
1196     uint32_t isr;
1197     qemu_irq irq;
1198     qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */
1199 } musicpal_gpio_state;
1200
1201 static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) {
1202     int i;
1203     uint32_t brightness;
1204
1205     /* compute brightness ratio */
1206     switch (s->lcd_brightness) {
1207     case 0x00000007:
1208         brightness = 0;
1209         break;
1210
1211     case 0x00020000:
1212         brightness = 1;
1213         break;
1214
1215     case 0x00020001:
1216         brightness = 2;
1217         break;
1218
1219     case 0x00040000:
1220         brightness = 3;
1221         break;
1222
1223     case 0x00010006:
1224         brightness = 4;
1225         break;
1226
1227     case 0x00020005:
1228         brightness = 5;
1229         break;
1230
1231     case 0x00040003:
1232         brightness = 6;
1233         break;
1234
1235     case 0x00030004:
1236     default:
1237         brightness = 7;
1238     }
1239
1240     /* set lcd brightness GPIOs  */
1241     for (i = 0; i <= 2; i++) {
1242         qemu_set_irq(s->out[i], (brightness >> i) & 1);
1243     }
1244 }
1245
1246 static void musicpal_gpio_pin_event(void *opaque, int pin, int level)
1247 {
1248     musicpal_gpio_state *s = opaque;
1249     uint32_t mask = 1 << pin;
1250     uint32_t delta = level << pin;
1251     uint32_t old = s->in_state & mask;
1252
1253     s->in_state &= ~mask;
1254     s->in_state |= delta;
1255
1256     if ((old ^ delta) &&
1257         ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) {
1258         s->isr = mask;
1259         qemu_irq_raise(s->irq);
1260     }
1261 }
1262
1263 static uint64_t musicpal_gpio_read(void *opaque, hwaddr offset,
1264                                    unsigned size)
1265 {
1266     musicpal_gpio_state *s = opaque;
1267
1268     switch (offset) {
1269     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1270         return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1271
1272     case MP_GPIO_OUT_LO:
1273         return s->out_state & 0xFFFF;
1274     case MP_GPIO_OUT_HI:
1275         return s->out_state >> 16;
1276
1277     case MP_GPIO_IN_LO:
1278         return s->in_state & 0xFFFF;
1279     case MP_GPIO_IN_HI:
1280         return s->in_state >> 16;
1281
1282     case MP_GPIO_IER_LO:
1283         return s->ier & 0xFFFF;
1284     case MP_GPIO_IER_HI:
1285         return s->ier >> 16;
1286
1287     case MP_GPIO_IMR_LO:
1288         return s->imr & 0xFFFF;
1289     case MP_GPIO_IMR_HI:
1290         return s->imr >> 16;
1291
1292     case MP_GPIO_ISR_LO:
1293         return s->isr & 0xFFFF;
1294     case MP_GPIO_ISR_HI:
1295         return s->isr >> 16;
1296
1297     default:
1298         return 0;
1299     }
1300 }
1301
1302 static void musicpal_gpio_write(void *opaque, hwaddr offset,
1303                                 uint64_t value, unsigned size)
1304 {
1305     musicpal_gpio_state *s = opaque;
1306     switch (offset) {
1307     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1308         s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1309                          (value & MP_OE_LCD_BRIGHTNESS);
1310         musicpal_gpio_brightness_update(s);
1311         break;
1312
1313     case MP_GPIO_OUT_LO:
1314         s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF);
1315         break;
1316     case MP_GPIO_OUT_HI:
1317         s->out_state = (s->out_state & 0xFFFF) | (value << 16);
1318         s->lcd_brightness = (s->lcd_brightness & 0xFFFF) |
1319                             (s->out_state & MP_GPIO_LCD_BRIGHTNESS);
1320         musicpal_gpio_brightness_update(s);
1321         qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1);
1322         qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1323         break;
1324
1325     case MP_GPIO_IER_LO:
1326         s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF);
1327         break;
1328     case MP_GPIO_IER_HI:
1329         s->ier = (s->ier & 0xFFFF) | (value << 16);
1330         break;
1331
1332     case MP_GPIO_IMR_LO:
1333         s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF);
1334         break;
1335     case MP_GPIO_IMR_HI:
1336         s->imr = (s->imr & 0xFFFF) | (value << 16);
1337         break;
1338     }
1339 }
1340
1341 static const MemoryRegionOps musicpal_gpio_ops = {
1342     .read = musicpal_gpio_read,
1343     .write = musicpal_gpio_write,
1344     .endianness = DEVICE_NATIVE_ENDIAN,
1345 };
1346
1347 static void musicpal_gpio_reset(DeviceState *d)
1348 {
1349     musicpal_gpio_state *s = MUSICPAL_GPIO(d);
1350
1351     s->lcd_brightness = 0;
1352     s->out_state = 0;
1353     s->in_state = 0xffffffff;
1354     s->ier = 0;
1355     s->imr = 0;
1356     s->isr = 0;
1357 }
1358
1359 static void musicpal_gpio_init(Object *obj)
1360 {
1361     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1362     DeviceState *dev = DEVICE(sbd);
1363     musicpal_gpio_state *s = MUSICPAL_GPIO(dev);
1364
1365     sysbus_init_irq(sbd, &s->irq);
1366
1367     memory_region_init_io(&s->iomem, obj, &musicpal_gpio_ops, s,
1368                           "musicpal-gpio", MP_GPIO_SIZE);
1369     sysbus_init_mmio(sbd, &s->iomem);
1370
1371     qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out));
1372
1373     qdev_init_gpio_in(dev, musicpal_gpio_pin_event, 32);
1374 }
1375
1376 static const VMStateDescription musicpal_gpio_vmsd = {
1377     .name = "musicpal_gpio",
1378     .version_id = 1,
1379     .minimum_version_id = 1,
1380     .fields = (VMStateField[]) {
1381         VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state),
1382         VMSTATE_UINT32(out_state, musicpal_gpio_state),
1383         VMSTATE_UINT32(in_state, musicpal_gpio_state),
1384         VMSTATE_UINT32(ier, musicpal_gpio_state),
1385         VMSTATE_UINT32(imr, musicpal_gpio_state),
1386         VMSTATE_UINT32(isr, musicpal_gpio_state),
1387         VMSTATE_END_OF_LIST()
1388     }
1389 };
1390
1391 static void musicpal_gpio_class_init(ObjectClass *klass, void *data)
1392 {
1393     DeviceClass *dc = DEVICE_CLASS(klass);
1394
1395     dc->reset = musicpal_gpio_reset;
1396     dc->vmsd = &musicpal_gpio_vmsd;
1397 }
1398
1399 static const TypeInfo musicpal_gpio_info = {
1400     .name          = TYPE_MUSICPAL_GPIO,
1401     .parent        = TYPE_SYS_BUS_DEVICE,
1402     .instance_size = sizeof(musicpal_gpio_state),
1403     .instance_init = musicpal_gpio_init,
1404     .class_init    = musicpal_gpio_class_init,
1405 };
1406
1407 /* Keyboard codes & masks */
1408 #define KEY_RELEASED            0x80
1409 #define KEY_CODE                0x7f
1410
1411 #define KEYCODE_TAB             0x0f
1412 #define KEYCODE_ENTER           0x1c
1413 #define KEYCODE_F               0x21
1414 #define KEYCODE_M               0x32
1415
1416 #define KEYCODE_EXTENDED        0xe0
1417 #define KEYCODE_UP              0x48
1418 #define KEYCODE_DOWN            0x50
1419 #define KEYCODE_LEFT            0x4b
1420 #define KEYCODE_RIGHT           0x4d
1421
1422 #define MP_KEY_WHEEL_VOL       (1 << 0)
1423 #define MP_KEY_WHEEL_VOL_INV   (1 << 1)
1424 #define MP_KEY_WHEEL_NAV       (1 << 2)
1425 #define MP_KEY_WHEEL_NAV_INV   (1 << 3)
1426 #define MP_KEY_BTN_FAVORITS    (1 << 4)
1427 #define MP_KEY_BTN_MENU        (1 << 5)
1428 #define MP_KEY_BTN_VOLUME      (1 << 6)
1429 #define MP_KEY_BTN_NAVIGATION  (1 << 7)
1430
1431 #define TYPE_MUSICPAL_KEY "musicpal_key"
1432 #define MUSICPAL_KEY(obj) \
1433     OBJECT_CHECK(musicpal_key_state, (obj), TYPE_MUSICPAL_KEY)
1434
1435 typedef struct musicpal_key_state {
1436     /*< private >*/
1437     SysBusDevice parent_obj;
1438     /*< public >*/
1439
1440     MemoryRegion iomem;
1441     uint32_t kbd_extended;
1442     uint32_t pressed_keys;
1443     qemu_irq out[8];
1444 } musicpal_key_state;
1445
1446 static void musicpal_key_event(void *opaque, int keycode)
1447 {
1448     musicpal_key_state *s = opaque;
1449     uint32_t event = 0;
1450     int i;
1451
1452     if (keycode == KEYCODE_EXTENDED) {
1453         s->kbd_extended = 1;
1454         return;
1455     }
1456
1457     if (s->kbd_extended) {
1458         switch (keycode & KEY_CODE) {
1459         case KEYCODE_UP:
1460             event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV;
1461             break;
1462
1463         case KEYCODE_DOWN:
1464             event = MP_KEY_WHEEL_NAV;
1465             break;
1466
1467         case KEYCODE_LEFT:
1468             event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV;
1469             break;
1470
1471         case KEYCODE_RIGHT:
1472             event = MP_KEY_WHEEL_VOL;
1473             break;
1474         }
1475     } else {
1476         switch (keycode & KEY_CODE) {
1477         case KEYCODE_F:
1478             event = MP_KEY_BTN_FAVORITS;
1479             break;
1480
1481         case KEYCODE_TAB:
1482             event = MP_KEY_BTN_VOLUME;
1483             break;
1484
1485         case KEYCODE_ENTER:
1486             event = MP_KEY_BTN_NAVIGATION;
1487             break;
1488
1489         case KEYCODE_M:
1490             event = MP_KEY_BTN_MENU;
1491             break;
1492         }
1493         /* Do not repeat already pressed buttons */
1494         if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1495             event = 0;
1496         }
1497     }
1498
1499     if (event) {
1500         /* Raise GPIO pin first if repeating a key */
1501         if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1502             for (i = 0; i <= 7; i++) {
1503                 if (event & (1 << i)) {
1504                     qemu_set_irq(s->out[i], 1);
1505                 }
1506             }
1507         }
1508         for (i = 0; i <= 7; i++) {
1509             if (event & (1 << i)) {
1510                 qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED));
1511             }
1512         }
1513         if (keycode & KEY_RELEASED) {
1514             s->pressed_keys &= ~event;
1515         } else {
1516             s->pressed_keys |= event;
1517         }
1518     }
1519
1520     s->kbd_extended = 0;
1521 }
1522
1523 static void musicpal_key_init(Object *obj)
1524 {
1525     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1526     DeviceState *dev = DEVICE(sbd);
1527     musicpal_key_state *s = MUSICPAL_KEY(dev);
1528
1529     memory_region_init(&s->iomem, obj, "dummy", 0);
1530     sysbus_init_mmio(sbd, &s->iomem);
1531
1532     s->kbd_extended = 0;
1533     s->pressed_keys = 0;
1534
1535     qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out));
1536
1537     qemu_add_kbd_event_handler(musicpal_key_event, s);
1538 }
1539
1540 static const VMStateDescription musicpal_key_vmsd = {
1541     .name = "musicpal_key",
1542     .version_id = 1,
1543     .minimum_version_id = 1,
1544     .fields = (VMStateField[]) {
1545         VMSTATE_UINT32(kbd_extended, musicpal_key_state),
1546         VMSTATE_UINT32(pressed_keys, musicpal_key_state),
1547         VMSTATE_END_OF_LIST()
1548     }
1549 };
1550
1551 static void musicpal_key_class_init(ObjectClass *klass, void *data)
1552 {
1553     DeviceClass *dc = DEVICE_CLASS(klass);
1554
1555     dc->vmsd = &musicpal_key_vmsd;
1556 }
1557
1558 static const TypeInfo musicpal_key_info = {
1559     .name          = TYPE_MUSICPAL_KEY,
1560     .parent        = TYPE_SYS_BUS_DEVICE,
1561     .instance_size = sizeof(musicpal_key_state),
1562     .instance_init = musicpal_key_init,
1563     .class_init    = musicpal_key_class_init,
1564 };
1565
1566 static struct arm_boot_info musicpal_binfo = {
1567     .loader_start = 0x0,
1568     .board_id = 0x20e,
1569 };
1570
1571 static void musicpal_init(MachineState *machine)
1572 {
1573     const char *kernel_filename = machine->kernel_filename;
1574     const char *kernel_cmdline = machine->kernel_cmdline;
1575     const char *initrd_filename = machine->initrd_filename;
1576     ARMCPU *cpu;
1577     qemu_irq pic[32];
1578     DeviceState *dev;
1579     DeviceState *i2c_dev;
1580     DeviceState *lcd_dev;
1581     DeviceState *key_dev;
1582     DeviceState *wm8750_dev;
1583     SysBusDevice *s;
1584     I2CBus *i2c;
1585     int i;
1586     unsigned long flash_size;
1587     DriveInfo *dinfo;
1588     MemoryRegion *address_space_mem = get_system_memory();
1589     MemoryRegion *ram = g_new(MemoryRegion, 1);
1590     MemoryRegion *sram = g_new(MemoryRegion, 1);
1591
1592     cpu = ARM_CPU(cpu_create(machine->cpu_type));
1593
1594     /* For now we use a fixed - the original - RAM size */
1595     memory_region_allocate_system_memory(ram, NULL, "musicpal.ram",
1596                                          MP_RAM_DEFAULT_SIZE);
1597     memory_region_add_subregion(address_space_mem, 0, ram);
1598
1599     memory_region_init_ram(sram, NULL, "musicpal.sram", MP_SRAM_SIZE,
1600                            &error_fatal);
1601     memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
1602
1603     dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE,
1604                                qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
1605     for (i = 0; i < 32; i++) {
1606         pic[i] = qdev_get_gpio_in(dev, i);
1607     }
1608     sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ],
1609                           pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
1610                           pic[MP_TIMER4_IRQ], NULL);
1611
1612     if (serial_hds[0]) {
1613         serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
1614                        1825000, serial_hds[0], DEVICE_NATIVE_ENDIAN);
1615     }
1616     if (serial_hds[1]) {
1617         serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
1618                        1825000, serial_hds[1], DEVICE_NATIVE_ENDIAN);
1619     }
1620
1621     /* Register flash */
1622     dinfo = drive_get(IF_PFLASH, 0, 0);
1623     if (dinfo) {
1624         BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
1625
1626         flash_size = blk_getlength(blk);
1627         if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1628             flash_size != 32*1024*1024) {
1629             fprintf(stderr, "Invalid flash image size\n");
1630             exit(1);
1631         }
1632
1633         /*
1634          * The original U-Boot accesses the flash at 0xFE000000 instead of
1635          * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1636          * image is smaller than 32 MB.
1637          */
1638 #ifdef TARGET_WORDS_BIGENDIAN
1639         pflash_cfi02_register(0x100000000ULL-MP_FLASH_SIZE_MAX, NULL,
1640                               "musicpal.flash", flash_size,
1641                               blk, 0x10000, (flash_size + 0xffff) >> 16,
1642                               MP_FLASH_SIZE_MAX / flash_size,
1643                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1644                               0x5555, 0x2AAA, 1);
1645 #else
1646         pflash_cfi02_register(0x100000000ULL-MP_FLASH_SIZE_MAX, NULL,
1647                               "musicpal.flash", flash_size,
1648                               blk, 0x10000, (flash_size + 0xffff) >> 16,
1649                               MP_FLASH_SIZE_MAX / flash_size,
1650                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1651                               0x5555, 0x2AAA, 0);
1652 #endif
1653
1654     }
1655     sysbus_create_simple(TYPE_MV88W8618_FLASHCFG, MP_FLASHCFG_BASE, NULL);
1656
1657     qemu_check_nic_model(&nd_table[0], "mv88w8618");
1658     dev = qdev_create(NULL, TYPE_MV88W8618_ETH);
1659     qdev_set_nic_properties(dev, &nd_table[0]);
1660     qdev_init_nofail(dev);
1661     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE);
1662     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]);
1663
1664     sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
1665
1666     sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL);
1667
1668     dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE,
1669                                pic[MP_GPIO_IRQ]);
1670     i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
1671     i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c");
1672
1673     lcd_dev = sysbus_create_simple(TYPE_MUSICPAL_LCD, MP_LCD_BASE, NULL);
1674     key_dev = sysbus_create_simple(TYPE_MUSICPAL_KEY, -1, NULL);
1675
1676     /* I2C read data */
1677     qdev_connect_gpio_out(i2c_dev, 0,
1678                           qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT));
1679     /* I2C data */
1680     qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0));
1681     /* I2C clock */
1682     qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1));
1683
1684     for (i = 0; i < 3; i++) {
1685         qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i));
1686     }
1687     for (i = 0; i < 4; i++) {
1688         qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8));
1689     }
1690     for (i = 4; i < 8; i++) {
1691         qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15));
1692     }
1693
1694     wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR);
1695     dev = qdev_create(NULL, "mv88w8618_audio");
1696     s = SYS_BUS_DEVICE(dev);
1697     qdev_prop_set_ptr(dev, "wm8750", wm8750_dev);
1698     qdev_init_nofail(dev);
1699     sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
1700     sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
1701
1702     musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1703     musicpal_binfo.kernel_filename = kernel_filename;
1704     musicpal_binfo.kernel_cmdline = kernel_cmdline;
1705     musicpal_binfo.initrd_filename = initrd_filename;
1706     arm_load_kernel(cpu, &musicpal_binfo);
1707 }
1708
1709 static void musicpal_machine_init(MachineClass *mc)
1710 {
1711     mc->desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)";
1712     mc->init = musicpal_init;
1713     mc->ignore_memory_transaction_failures = true;
1714     mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
1715 }
1716
1717 DEFINE_MACHINE("musicpal", musicpal_machine_init)
1718
1719 static void mv88w8618_wlan_class_init(ObjectClass *klass, void *data)
1720 {
1721     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
1722
1723     sdc->init = mv88w8618_wlan_init;
1724 }
1725
1726 static const TypeInfo mv88w8618_wlan_info = {
1727     .name          = "mv88w8618_wlan",
1728     .parent        = TYPE_SYS_BUS_DEVICE,
1729     .instance_size = sizeof(SysBusDevice),
1730     .class_init    = mv88w8618_wlan_class_init,
1731 };
1732
1733 static void musicpal_register_types(void)
1734 {
1735     type_register_static(&mv88w8618_pic_info);
1736     type_register_static(&mv88w8618_pit_info);
1737     type_register_static(&mv88w8618_flashcfg_info);
1738     type_register_static(&mv88w8618_eth_info);
1739     type_register_static(&mv88w8618_wlan_info);
1740     type_register_static(&musicpal_lcd_info);
1741     type_register_static(&musicpal_gpio_info);
1742     type_register_static(&musicpal_key_info);
1743     type_register_static(&musicpal_misc_info);
1744 }
1745
1746 type_init(musicpal_register_types)