4 * Copyright (c) 2013 Kevin Wolf <kwolf@redhat.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
29 #include "libqos/libqos.h"
30 #include "libqos/pci-pc.h"
31 #include "libqos/malloc-pc.h"
33 #include "qemu-common.h"
34 #include "qemu/bswap.h"
35 #include "hw/pci/pci_ids.h"
36 #include "hw/pci/pci_regs.h"
38 #define TEST_IMAGE_SIZE 64 * 1024 * 1024
41 #define IDE_PCI_FUNC 1
43 #define IDE_BASE 0x1f0
44 #define IDE_PRIMARY_IRQ 14
46 #define ATAPI_BLOCK_SIZE 2048
48 /* How many bytes to receive via ATAPI PIO at one time.
49 * Must be less than 0xFFFF. */
50 #define BYTE_COUNT_LIMIT 5120
86 CMD_FLUSH_CACHE
= 0xe7,
96 BM_CMD_WRITE
= 0x8, /* write = from device to memory */
106 PRDT_EOT
= 0x80000000,
109 #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
110 #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0)
112 static QPCIBus
*pcibus
= NULL
;
113 static QGuestAllocator
*guest_malloc
;
115 static char tmp_path
[] = "/tmp/qtest.XXXXXX";
116 static char debug_path
[] = "/tmp/qtest-blkdebug.XXXXXX";
118 static void ide_test_start(const char *cmdline_fmt
, ...)
123 va_start(ap
, cmdline_fmt
);
124 cmdline
= g_strdup_vprintf(cmdline_fmt
, ap
);
127 qtest_start(cmdline
);
128 guest_malloc
= pc_alloc_init();
133 static void ide_test_quit(void)
135 pc_alloc_uninit(guest_malloc
);
140 static QPCIDevice
*get_pci_device(QPCIBar
*bmdma_bar
, QPCIBar
*ide_bar
)
143 uint16_t vendor_id
, device_id
;
146 pcibus
= qpci_init_pc(NULL
);
149 /* Find PCI device and verify it's the right one */
150 dev
= qpci_device_find(pcibus
, QPCI_DEVFN(IDE_PCI_DEV
, IDE_PCI_FUNC
));
151 g_assert(dev
!= NULL
);
153 vendor_id
= qpci_config_readw(dev
, PCI_VENDOR_ID
);
154 device_id
= qpci_config_readw(dev
, PCI_DEVICE_ID
);
155 g_assert(vendor_id
== PCI_VENDOR_ID_INTEL
);
156 g_assert(device_id
== PCI_DEVICE_ID_INTEL_82371SB_1
);
159 *bmdma_bar
= qpci_iomap(dev
, 4, NULL
);
161 *ide_bar
= qpci_legacy_iomap(dev
, IDE_BASE
);
163 qpci_device_enable(dev
);
168 static void free_pci_device(QPCIDevice
*dev
)
170 /* libqos doesn't have a function for this, so free it manually */
174 typedef struct PrdtEntry
{
177 } QEMU_PACKED PrdtEntry
;
179 #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
180 #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0)
182 static int send_dma_request(int cmd
, uint64_t sector
, int nb_sectors
,
183 PrdtEntry
*prdt
, int prdt_entries
,
184 void(*post_exec
)(QPCIDevice
*dev
, QPCIBar ide_bar
,
185 uint64_t sector
, int nb_sectors
))
188 QPCIBar bmdma_bar
, ide_bar
;
189 uintptr_t guest_prdt
;
195 dev
= get_pci_device(&bmdma_bar
, &ide_bar
);
203 /* Assuming we only test data reads w/ ATAPI, otherwise we need to know
204 * the SCSI command being sent in the packet, too. */
211 g_assert_not_reached();
214 if (flags
& CMDF_NO_BM
) {
215 qpci_config_writew(dev
, PCI_COMMAND
,
216 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
);
219 /* Select device 0 */
220 qpci_io_writeb(dev
, ide_bar
, reg_device
, 0 | LBA
);
222 /* Stop any running transfer, clear any pending interrupt */
223 qpci_io_writeb(dev
, bmdma_bar
, bmreg_cmd
, 0);
224 qpci_io_writeb(dev
, bmdma_bar
, bmreg_status
, BM_STS_INTR
);
227 len
= sizeof(*prdt
) * prdt_entries
;
228 guest_prdt
= guest_alloc(guest_malloc
, len
);
229 memwrite(guest_prdt
, prdt
, len
);
230 qpci_io_writel(dev
, bmdma_bar
, bmreg_prdt
, guest_prdt
);
232 /* ATA DMA command */
233 if (cmd
== CMD_PACKET
) {
234 /* Enables ATAPI DMA; otherwise PIO is attempted */
235 qpci_io_writeb(dev
, ide_bar
, reg_feature
, 0x01);
237 qpci_io_writeb(dev
, ide_bar
, reg_nsectors
, nb_sectors
);
238 qpci_io_writeb(dev
, ide_bar
, reg_lba_low
, sector
& 0xff);
239 qpci_io_writeb(dev
, ide_bar
, reg_lba_middle
, (sector
>> 8) & 0xff);
240 qpci_io_writeb(dev
, ide_bar
, reg_lba_high
, (sector
>> 16) & 0xff);
243 qpci_io_writeb(dev
, ide_bar
, reg_command
, cmd
);
246 post_exec(dev
, ide_bar
, sector
, nb_sectors
);
249 /* Start DMA transfer */
250 qpci_io_writeb(dev
, bmdma_bar
, bmreg_cmd
,
251 BM_CMD_START
| (from_dev
? BM_CMD_WRITE
: 0));
253 if (flags
& CMDF_ABORT
) {
254 qpci_io_writeb(dev
, bmdma_bar
, bmreg_cmd
, 0);
257 /* Wait for the DMA transfer to complete */
259 status
= qpci_io_readb(dev
, bmdma_bar
, bmreg_status
);
260 } while ((status
& (BM_STS_ACTIVE
| BM_STS_INTR
)) == BM_STS_ACTIVE
);
262 g_assert_cmpint(get_irq(IDE_PRIMARY_IRQ
), ==, !!(status
& BM_STS_INTR
));
264 /* Check IDE status code */
265 assert_bit_set(qpci_io_readb(dev
, ide_bar
, reg_status
), DRDY
);
266 assert_bit_clear(qpci_io_readb(dev
, ide_bar
, reg_status
), BSY
| DRQ
);
268 /* Reading the status register clears the IRQ */
269 g_assert(!get_irq(IDE_PRIMARY_IRQ
));
271 /* Stop DMA transfer if still active */
272 if (status
& BM_STS_ACTIVE
) {
273 qpci_io_writeb(dev
, bmdma_bar
, bmreg_cmd
, 0);
276 free_pci_device(dev
);
281 static void test_bmdma_simple_rw(void)
284 QPCIBar bmdma_bar
, ide_bar
;
289 uintptr_t guest_buf
= guest_alloc(guest_malloc
, len
);
293 .addr
= cpu_to_le32(guest_buf
),
294 .size
= cpu_to_le32(len
| PRDT_EOT
),
298 dev
= get_pci_device(&bmdma_bar
, &ide_bar
);
301 cmpbuf
= g_malloc(len
);
303 /* Write 0x55 pattern to sector 0 */
304 memset(buf
, 0x55, len
);
305 memwrite(guest_buf
, buf
, len
);
307 status
= send_dma_request(CMD_WRITE_DMA
, 0, 1, prdt
,
308 ARRAY_SIZE(prdt
), NULL
);
309 g_assert_cmphex(status
, ==, BM_STS_INTR
);
310 assert_bit_clear(qpci_io_readb(dev
, ide_bar
, reg_status
), DF
| ERR
);
312 /* Write 0xaa pattern to sector 1 */
313 memset(buf
, 0xaa, len
);
314 memwrite(guest_buf
, buf
, len
);
316 status
= send_dma_request(CMD_WRITE_DMA
, 1, 1, prdt
,
317 ARRAY_SIZE(prdt
), NULL
);
318 g_assert_cmphex(status
, ==, BM_STS_INTR
);
319 assert_bit_clear(qpci_io_readb(dev
, ide_bar
, reg_status
), DF
| ERR
);
321 /* Read and verify 0x55 pattern in sector 0 */
322 memset(cmpbuf
, 0x55, len
);
324 status
= send_dma_request(CMD_READ_DMA
, 0, 1, prdt
, ARRAY_SIZE(prdt
), NULL
);
325 g_assert_cmphex(status
, ==, BM_STS_INTR
);
326 assert_bit_clear(qpci_io_readb(dev
, ide_bar
, reg_status
), DF
| ERR
);
328 memread(guest_buf
, buf
, len
);
329 g_assert(memcmp(buf
, cmpbuf
, len
) == 0);
331 /* Read and verify 0xaa pattern in sector 1 */
332 memset(cmpbuf
, 0xaa, len
);
334 status
= send_dma_request(CMD_READ_DMA
, 1, 1, prdt
, ARRAY_SIZE(prdt
), NULL
);
335 g_assert_cmphex(status
, ==, BM_STS_INTR
);
336 assert_bit_clear(qpci_io_readb(dev
, ide_bar
, reg_status
), DF
| ERR
);
338 memread(guest_buf
, buf
, len
);
339 g_assert(memcmp(buf
, cmpbuf
, len
) == 0);
342 free_pci_device(dev
);
347 static void test_bmdma_short_prdt(void)
350 QPCIBar bmdma_bar
, ide_bar
;
356 .size
= cpu_to_le32(0x10 | PRDT_EOT
),
360 dev
= get_pci_device(&bmdma_bar
, &ide_bar
);
363 status
= send_dma_request(CMD_READ_DMA
, 0, 1,
364 prdt
, ARRAY_SIZE(prdt
), NULL
);
365 g_assert_cmphex(status
, ==, 0);
366 assert_bit_clear(qpci_io_readb(dev
, ide_bar
, reg_status
), DF
| ERR
);
368 /* Abort the request before it completes */
369 status
= send_dma_request(CMD_READ_DMA
| CMDF_ABORT
, 0, 1,
370 prdt
, ARRAY_SIZE(prdt
), NULL
);
371 g_assert_cmphex(status
, ==, 0);
372 assert_bit_clear(qpci_io_readb(dev
, ide_bar
, reg_status
), DF
| ERR
);
373 free_pci_device(dev
);
376 static void test_bmdma_one_sector_short_prdt(void)
379 QPCIBar bmdma_bar
, ide_bar
;
382 /* Read 2 sectors but only give 1 sector in PRDT */
386 .size
= cpu_to_le32(0x200 | PRDT_EOT
),
390 dev
= get_pci_device(&bmdma_bar
, &ide_bar
);
393 status
= send_dma_request(CMD_READ_DMA
, 0, 2,
394 prdt
, ARRAY_SIZE(prdt
), NULL
);
395 g_assert_cmphex(status
, ==, 0);
396 assert_bit_clear(qpci_io_readb(dev
, ide_bar
, reg_status
), DF
| ERR
);
398 /* Abort the request before it completes */
399 status
= send_dma_request(CMD_READ_DMA
| CMDF_ABORT
, 0, 2,
400 prdt
, ARRAY_SIZE(prdt
), NULL
);
401 g_assert_cmphex(status
, ==, 0);
402 assert_bit_clear(qpci_io_readb(dev
, ide_bar
, reg_status
), DF
| ERR
);
403 free_pci_device(dev
);
406 static void test_bmdma_long_prdt(void)
409 QPCIBar bmdma_bar
, ide_bar
;
415 .size
= cpu_to_le32(0x1000 | PRDT_EOT
),
419 dev
= get_pci_device(&bmdma_bar
, &ide_bar
);
422 status
= send_dma_request(CMD_READ_DMA
, 0, 1,
423 prdt
, ARRAY_SIZE(prdt
), NULL
);
424 g_assert_cmphex(status
, ==, BM_STS_ACTIVE
| BM_STS_INTR
);
425 assert_bit_clear(qpci_io_readb(dev
, ide_bar
, reg_status
), DF
| ERR
);
427 /* Abort the request before it completes */
428 status
= send_dma_request(CMD_READ_DMA
| CMDF_ABORT
, 0, 1,
429 prdt
, ARRAY_SIZE(prdt
), NULL
);
430 g_assert_cmphex(status
, ==, BM_STS_INTR
);
431 assert_bit_clear(qpci_io_readb(dev
, ide_bar
, reg_status
), DF
| ERR
);
432 free_pci_device(dev
);
435 static void test_bmdma_no_busmaster(void)
438 QPCIBar bmdma_bar
, ide_bar
;
441 dev
= get_pci_device(&bmdma_bar
, &ide_bar
);
443 /* No PRDT_EOT, each entry addr 0/size 64k, and in theory qemu shouldn't be
444 * able to access it anyway because the Bus Master bit in the PCI command
445 * register isn't set. This is complete nonsense, but it used to be pretty
446 * good at confusing and occasionally crashing qemu. */
447 PrdtEntry prdt
[4096] = { };
449 status
= send_dma_request(CMD_READ_DMA
| CMDF_NO_BM
, 0, 512,
450 prdt
, ARRAY_SIZE(prdt
), NULL
);
452 /* Not entirely clear what the expected result is, but this is what we get
453 * in practice. At least we want to be aware of any changes. */
454 g_assert_cmphex(status
, ==, BM_STS_ACTIVE
| BM_STS_INTR
);
455 assert_bit_clear(qpci_io_readb(dev
, ide_bar
, reg_status
), DF
| ERR
);
456 free_pci_device(dev
);
459 static void test_bmdma_setup(void)
462 "-drive file=%s,if=ide,serial=%s,cache=writeback,format=raw "
463 "-global ide-hd.ver=%s",
464 tmp_path
, "testdisk", "version");
465 qtest_irq_intercept_in(global_qtest
, "ioapic");
468 static void test_bmdma_teardown(void)
473 static void string_cpu_to_be16(uint16_t *s
, size_t bytes
)
475 g_assert((bytes
& 1) == 0);
479 *s
= cpu_to_be16(*s
);
484 static void test_identify(void)
487 QPCIBar bmdma_bar
, ide_bar
;
494 "-drive file=%s,if=ide,serial=%s,cache=writeback,format=raw "
495 "-global ide-hd.ver=%s",
496 tmp_path
, "testdisk", "version");
498 dev
= get_pci_device(&bmdma_bar
, &ide_bar
);
500 /* IDENTIFY command on device 0*/
501 qpci_io_writeb(dev
, ide_bar
, reg_device
, 0);
502 qpci_io_writeb(dev
, ide_bar
, reg_command
, CMD_IDENTIFY
);
504 /* Read in the IDENTIFY buffer and check registers */
505 data
= qpci_io_readb(dev
, ide_bar
, reg_device
);
506 g_assert_cmpint(data
& DEV
, ==, 0);
508 for (i
= 0; i
< 256; i
++) {
509 data
= qpci_io_readb(dev
, ide_bar
, reg_status
);
510 assert_bit_set(data
, DRDY
| DRQ
);
511 assert_bit_clear(data
, BSY
| DF
| ERR
);
513 buf
[i
] = qpci_io_readw(dev
, ide_bar
, reg_data
);
516 data
= qpci_io_readb(dev
, ide_bar
, reg_status
);
517 assert_bit_set(data
, DRDY
);
518 assert_bit_clear(data
, BSY
| DF
| ERR
| DRQ
);
520 /* Check serial number/version in the buffer */
521 string_cpu_to_be16(&buf
[10], 20);
522 ret
= memcmp(&buf
[10], "testdisk ", 20);
525 string_cpu_to_be16(&buf
[23], 8);
526 ret
= memcmp(&buf
[23], "version ", 8);
529 /* Write cache enabled bit */
530 assert_bit_set(buf
[85], 0x20);
533 free_pci_device(dev
);
537 * Write sector 1 with random data to make IDE storage dirty
538 * Needed for flush tests so that flushes actually go though the block layer
540 static void make_dirty(uint8_t device
)
543 QPCIBar bmdma_bar
, ide_bar
;
549 dev
= get_pci_device(&bmdma_bar
, &ide_bar
);
551 guest_buf
= guest_alloc(guest_malloc
, len
);
553 memset(buf
, rand() % 255 + 1, len
);
557 memwrite(guest_buf
, buf
, len
);
561 .addr
= cpu_to_le32(guest_buf
),
562 .size
= cpu_to_le32(len
| PRDT_EOT
),
566 status
= send_dma_request(CMD_WRITE_DMA
, 1, 1, prdt
,
567 ARRAY_SIZE(prdt
), NULL
);
568 g_assert_cmphex(status
, ==, BM_STS_INTR
);
569 assert_bit_clear(qpci_io_readb(dev
, ide_bar
, reg_status
), DF
| ERR
);
572 free_pci_device(dev
);
575 static void test_flush(void)
578 QPCIBar bmdma_bar
, ide_bar
;
582 "-drive file=blkdebug::%s,if=ide,cache=writeback,format=raw",
585 dev
= get_pci_device(&bmdma_bar
, &ide_bar
);
587 qtest_irq_intercept_in(global_qtest
, "ioapic");
589 /* Dirty media so that CMD_FLUSH_CACHE will actually go to disk */
592 /* Delay the completion of the flush request until we explicitly do it */
593 g_free(hmp("qemu-io ide0-hd0 \"break flush_to_os A\""));
595 /* FLUSH CACHE command on device 0*/
596 qpci_io_writeb(dev
, ide_bar
, reg_device
, 0);
597 qpci_io_writeb(dev
, ide_bar
, reg_command
, CMD_FLUSH_CACHE
);
599 /* Check status while request is in flight*/
600 data
= qpci_io_readb(dev
, ide_bar
, reg_status
);
601 assert_bit_set(data
, BSY
| DRDY
);
602 assert_bit_clear(data
, DF
| ERR
| DRQ
);
604 /* Complete the command */
605 g_free(hmp("qemu-io ide0-hd0 \"resume A\""));
607 /* Check registers */
608 data
= qpci_io_readb(dev
, ide_bar
, reg_device
);
609 g_assert_cmpint(data
& DEV
, ==, 0);
612 data
= qpci_io_readb(dev
, ide_bar
, reg_status
);
613 } while (data
& BSY
);
615 assert_bit_set(data
, DRDY
);
616 assert_bit_clear(data
, BSY
| DF
| ERR
| DRQ
);
619 free_pci_device(dev
);
622 static void test_retry_flush(const char *machine
)
625 QPCIBar bmdma_bar
, ide_bar
;
629 prepare_blkdebug_script(debug_path
, "flush_to_disk");
632 "-drive file=blkdebug:%s:%s,if=ide,cache=writeback,format=raw,"
633 "rerror=stop,werror=stop",
634 debug_path
, tmp_path
);
636 dev
= get_pci_device(&bmdma_bar
, &ide_bar
);
638 qtest_irq_intercept_in(global_qtest
, "ioapic");
640 /* Dirty media so that CMD_FLUSH_CACHE will actually go to disk */
643 /* FLUSH CACHE command on device 0*/
644 qpci_io_writeb(dev
, ide_bar
, reg_device
, 0);
645 qpci_io_writeb(dev
, ide_bar
, reg_command
, CMD_FLUSH_CACHE
);
647 /* Check status while request is in flight*/
648 data
= qpci_io_readb(dev
, ide_bar
, reg_status
);
649 assert_bit_set(data
, BSY
| DRDY
);
650 assert_bit_clear(data
, DF
| ERR
| DRQ
);
652 qmp_eventwait("STOP");
654 /* Complete the command */
655 s
= "{'execute':'cont' }";
656 qmp_discard_response(s
);
658 /* Check registers */
659 data
= qpci_io_readb(dev
, ide_bar
, reg_device
);
660 g_assert_cmpint(data
& DEV
, ==, 0);
663 data
= qpci_io_readb(dev
, ide_bar
, reg_status
);
664 } while (data
& BSY
);
666 assert_bit_set(data
, DRDY
);
667 assert_bit_clear(data
, BSY
| DF
| ERR
| DRQ
);
670 free_pci_device(dev
);
673 static void test_flush_nodev(void)
676 QPCIBar bmdma_bar
, ide_bar
;
680 dev
= get_pci_device(&bmdma_bar
, &ide_bar
);
682 /* FLUSH CACHE command on device 0*/
683 qpci_io_writeb(dev
, ide_bar
, reg_device
, 0);
684 qpci_io_writeb(dev
, ide_bar
, reg_command
, CMD_FLUSH_CACHE
);
686 /* Just testing that qemu doesn't crash... */
688 free_pci_device(dev
);
692 static void test_flush_empty_drive(void)
695 QPCIBar bmdma_bar
, ide_bar
;
697 ide_test_start("-device ide-cd,bus=ide.0");
698 dev
= get_pci_device(&bmdma_bar
, &ide_bar
);
700 /* FLUSH CACHE command on device 0 */
701 qpci_io_writeb(dev
, ide_bar
, reg_device
, 0);
702 qpci_io_writeb(dev
, ide_bar
, reg_command
, CMD_FLUSH_CACHE
);
704 /* Just testing that qemu doesn't crash... */
706 free_pci_device(dev
);
710 static void test_pci_retry_flush(void)
712 test_retry_flush("pc");
715 static void test_isa_retry_flush(void)
717 test_retry_flush("isapc");
720 typedef struct Read10CDB
{
728 } __attribute__((__packed__
)) Read10CDB
;
730 static void send_scsi_cdb_read10(QPCIDevice
*dev
, QPCIBar ide_bar
,
731 uint64_t lba
, int nblocks
)
733 Read10CDB pkt
= { .padding
= 0 };
736 g_assert_cmpint(lba
, <=, UINT32_MAX
);
737 g_assert_cmpint(nblocks
, <=, UINT16_MAX
);
738 g_assert_cmpint(nblocks
, >=, 0);
740 /* Construct SCSI CDB packet */
742 pkt
.lba
= cpu_to_be32(lba
);
743 pkt
.nblocks
= cpu_to_be16(nblocks
);
746 for (i
= 0; i
< sizeof(Read10CDB
)/2; i
++) {
747 qpci_io_writew(dev
, ide_bar
, reg_data
,
748 le16_to_cpu(((uint16_t *)&pkt
)[i
]));
752 static void nsleep(int64_t nsecs
)
754 const struct timespec val
= { .tv_nsec
= nsecs
};
755 nanosleep(&val
, NULL
);
759 static uint8_t ide_wait_clear(uint8_t flag
)
762 QPCIBar bmdma_bar
, ide_bar
;
766 dev
= get_pci_device(&bmdma_bar
, &ide_bar
);
768 /* Wait with a 5 second timeout */
771 data
= qpci_io_readb(dev
, ide_bar
, reg_status
);
772 if (!(data
& flag
)) {
773 free_pci_device(dev
);
776 if (difftime(time(NULL
), st
) > 5.0) {
781 g_assert_not_reached();
784 static void ide_wait_intr(int irq
)
795 if (difftime(time(NULL
), st
) > 5.0) {
801 g_assert_not_reached();
804 static void cdrom_pio_impl(int nblocks
)
807 QPCIBar bmdma_bar
, ide_bar
;
809 int patt_blocks
= MAX(16, nblocks
);
810 size_t patt_len
= ATAPI_BLOCK_SIZE
* patt_blocks
;
811 char *pattern
= g_malloc(patt_len
);
812 size_t rxsize
= ATAPI_BLOCK_SIZE
* nblocks
;
813 uint16_t *rx
= g_malloc0(rxsize
);
819 /* Prepopulate the CDROM with an interesting pattern */
820 generate_pattern(pattern
, patt_len
, ATAPI_BLOCK_SIZE
);
821 fh
= fopen(tmp_path
, "w+");
822 ret
= fwrite(pattern
, ATAPI_BLOCK_SIZE
, patt_blocks
, fh
);
823 g_assert_cmpint(ret
, ==, patt_blocks
);
826 ide_test_start("-drive if=none,file=%s,media=cdrom,format=raw,id=sr0,index=0 "
827 "-device ide-cd,drive=sr0,bus=ide.0", tmp_path
);
828 dev
= get_pci_device(&bmdma_bar
, &ide_bar
);
829 qtest_irq_intercept_in(global_qtest
, "ioapic");
831 /* PACKET command on device 0 */
832 qpci_io_writeb(dev
, ide_bar
, reg_device
, 0);
833 qpci_io_writeb(dev
, ide_bar
, reg_lba_middle
, BYTE_COUNT_LIMIT
& 0xFF);
834 qpci_io_writeb(dev
, ide_bar
, reg_lba_high
, (BYTE_COUNT_LIMIT
>> 8 & 0xFF));
835 qpci_io_writeb(dev
, ide_bar
, reg_command
, CMD_PACKET
);
836 /* HP0: Check_Status_A State */
838 data
= ide_wait_clear(BSY
);
839 /* HP1: Send_Packet State */
840 assert_bit_set(data
, DRQ
| DRDY
);
841 assert_bit_clear(data
, ERR
| DF
| BSY
);
843 /* SCSI CDB (READ10) -- read n*2048 bytes from block 0 */
844 send_scsi_cdb_read10(dev
, ide_bar
, 0, nblocks
);
846 /* Read data back: occurs in bursts of 'BYTE_COUNT_LIMIT' bytes.
847 * If BYTE_COUNT_LIMIT is odd, we transfer BYTE_COUNT_LIMIT - 1 bytes.
848 * We allow an odd limit only when the remaining transfer size is
849 * less than BYTE_COUNT_LIMIT. However, SCSI's read10 command can only
850 * request n blocks, so our request size is always even.
851 * For this reason, we assume there is never a hanging byte to fetch. */
852 g_assert(!(rxsize
& 1));
853 limit
= BYTE_COUNT_LIMIT
& ~1;
854 for (i
= 0; i
< DIV_ROUND_UP(rxsize
, limit
); i
++) {
855 size_t offset
= i
* (limit
/ 2);
856 size_t rem
= (rxsize
/ 2) - offset
;
858 /* HP3: INTRQ_Wait */
859 ide_wait_intr(IDE_PRIMARY_IRQ
);
861 /* HP2: Check_Status_B (and clear IRQ) */
862 data
= ide_wait_clear(BSY
);
863 assert_bit_set(data
, DRQ
| DRDY
);
864 assert_bit_clear(data
, ERR
| DF
| BSY
);
866 /* HP4: Transfer_Data */
867 for (j
= 0; j
< MIN((limit
/ 2), rem
); j
++) {
868 rx
[offset
+ j
] = cpu_to_le16(qpci_io_readw(dev
, ide_bar
,
873 /* Check for final completion IRQ */
874 ide_wait_intr(IDE_PRIMARY_IRQ
);
876 /* Sanity check final state */
877 data
= ide_wait_clear(DRQ
);
878 assert_bit_set(data
, DRDY
);
879 assert_bit_clear(data
, DRQ
| ERR
| DF
| BSY
);
881 g_assert_cmpint(memcmp(pattern
, rx
, rxsize
), ==, 0);
884 test_bmdma_teardown();
885 free_pci_device(dev
);
888 static void test_cdrom_pio(void)
893 static void test_cdrom_pio_large(void)
895 /* Test a few loops of the PIO DRQ mechanism. */
896 cdrom_pio_impl(BYTE_COUNT_LIMIT
* 4 / ATAPI_BLOCK_SIZE
);
900 static void test_cdrom_dma(void)
902 static const size_t len
= ATAPI_BLOCK_SIZE
;
904 char *pattern
= g_malloc(ATAPI_BLOCK_SIZE
* 16);
905 char *rx
= g_malloc0(len
);
910 ide_test_start("-drive if=none,file=%s,media=cdrom,format=raw,id=sr0,index=0 "
911 "-device ide-cd,drive=sr0,bus=ide.0", tmp_path
);
912 qtest_irq_intercept_in(global_qtest
, "ioapic");
914 guest_buf
= guest_alloc(guest_malloc
, len
);
915 prdt
[0].addr
= cpu_to_le32(guest_buf
);
916 prdt
[0].size
= cpu_to_le32(len
| PRDT_EOT
);
918 generate_pattern(pattern
, ATAPI_BLOCK_SIZE
* 16, ATAPI_BLOCK_SIZE
);
919 fh
= fopen(tmp_path
, "w+");
920 ret
= fwrite(pattern
, ATAPI_BLOCK_SIZE
, 16, fh
);
921 g_assert_cmpint(ret
, ==, 16);
924 send_dma_request(CMD_PACKET
, 0, 1, prdt
, 1, send_scsi_cdb_read10
);
926 /* Read back data from guest memory into local qtest memory */
927 memread(guest_buf
, rx
, len
);
928 g_assert_cmpint(memcmp(pattern
, rx
, len
), ==, 0);
932 test_bmdma_teardown();
935 int main(int argc
, char **argv
)
937 const char *arch
= qtest_get_arch();
941 /* Check architecture */
942 if (strcmp(arch
, "i386") && strcmp(arch
, "x86_64")) {
943 g_test_message("Skipping test for non-x86\n");
947 /* Create temporary blkdebug instructions */
948 fd
= mkstemp(debug_path
);
952 /* Create a temporary raw image */
953 fd
= mkstemp(tmp_path
);
955 ret
= ftruncate(fd
, TEST_IMAGE_SIZE
);
960 g_test_init(&argc
, &argv
, NULL
);
962 qtest_add_func("/ide/identify", test_identify
);
964 qtest_add_func("/ide/bmdma/setup", test_bmdma_setup
);
965 qtest_add_func("/ide/bmdma/simple_rw", test_bmdma_simple_rw
);
966 qtest_add_func("/ide/bmdma/short_prdt", test_bmdma_short_prdt
);
967 qtest_add_func("/ide/bmdma/one_sector_short_prdt",
968 test_bmdma_one_sector_short_prdt
);
969 qtest_add_func("/ide/bmdma/long_prdt", test_bmdma_long_prdt
);
970 qtest_add_func("/ide/bmdma/no_busmaster", test_bmdma_no_busmaster
);
971 qtest_add_func("/ide/bmdma/teardown", test_bmdma_teardown
);
973 qtest_add_func("/ide/flush", test_flush
);
974 qtest_add_func("/ide/flush/nodev", test_flush_nodev
);
975 qtest_add_func("/ide/flush/empty_drive", test_flush_empty_drive
);
976 qtest_add_func("/ide/flush/retry_pci", test_pci_retry_flush
);
977 qtest_add_func("/ide/flush/retry_isa", test_isa_retry_flush
);
979 qtest_add_func("/ide/cdrom/pio", test_cdrom_pio
);
980 qtest_add_func("/ide/cdrom/pio_large", test_cdrom_pio_large
);
981 qtest_add_func("/ide/cdrom/dma", test_cdrom_dma
);