hw/ide/macio.c

   1 /*
   2  * QEMU IDE Emulation: MacIO support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "qemu/osdep.h"
  26 #include "hw/hw.h"
  27 #include "hw/ppc/mac.h"
  28 #include "hw/ppc/mac_dbdma.h"
  29 #include "sysemu/block-backend.h"
  30 #include "sysemu/dma.h"
  31
  32 #include "hw/ide/internal.h"
  33
  34 /* debug MACIO */
  35 // #define DEBUG_MACIO
  36
  37 #ifdef DEBUG_MACIO
  38 static const int debug_macio = 1;
  39 #else
  40 static const int debug_macio = 0;
  41 #endif
  42
  43 #define MACIO_DPRINTF(fmt, ...) do { \
  44         if (debug_macio) { \
  45             printf(fmt , ## __VA_ARGS__); \
  46         } \
  47     } while (0)
  48
  49
  50 /***********************************************************/
  51 /* MacIO based PowerPC IDE */
  52
  53 #define MACIO_PAGE_SIZE 4096
  54
  55 static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
  56 {
  57     DBDMA_io *io = opaque;
  58     MACIOIDEState *m = io->opaque;
  59     IDEState *s = idebus_active_if(&m->bus);
  60     int64_t offset;
  61
  62     MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
  63
  64     if (ret < 0) {
  65         MACIO_DPRINTF("DMA error: %d\n", ret);
  66         qemu_sglist_destroy(&s->sg);
  67         ide_atapi_io_error(s, ret);
  68         goto done;
  69     }
  70
  71     if (!m->dma_active) {
  72         MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
  73                       s->nsector, io->len, s->status);
  74         /* data not ready yet, wait for the channel to get restarted */
  75         io->processing = false;
  76         return;
  77     }
  78
  79     if (s->io_buffer_size <= 0) {
  80         MACIO_DPRINTF("End of IDE transfer\n");
  81         qemu_sglist_destroy(&s->sg);
  82         ide_atapi_cmd_ok(s);
  83         m->dma_active = false;
  84         goto done;
  85     }
  86
  87     if (io->len == 0) {
  88         MACIO_DPRINTF("End of DMA transfer\n");
  89         goto done;
  90     }
  91
  92     if (s->lba == -1) {
  93         /* Non-block ATAPI transfer - just copy to RAM */
  94         s->io_buffer_size = MIN(s->io_buffer_size, io->len);
  95         dma_memory_write(&address_space_memory, io->addr, s->io_buffer,
  96                          s->io_buffer_size);
  97         io->len = 0;
  98         ide_atapi_cmd_ok(s);
  99         m->dma_active = false;
 100         goto done;
 101     }
 102
 103     /* Calculate current offset */
 104     offset = ((int64_t)s->lba << 11) + s->io_buffer_index;
 105
 106     qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
 107                      &address_space_memory);
 108     qemu_sglist_add(&s->sg, io->addr, io->len);
 109     s->io_buffer_size -= io->len;
 110     s->io_buffer_index += io->len;
 111     io->len = 0;
 112
 113     s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset, 0x1,
 114                                       pmac_ide_atapi_transfer_cb, io);
 115     return;
 116
 117 done:
 118     dma_memory_unmap(&address_space_memory, io->dma_mem, io->dma_len,
 119                      io->dir, io->dma_len);
 120
 121     if (ret < 0) {
 122         block_acct_failed(blk_get_stats(s->blk), &s->acct);
 123     } else {
 124         block_acct_done(blk_get_stats(s->blk), &s->acct);
 125     }
 126
 127     ide_set_inactive(s, false);
 128     io->dma_end(opaque);
 129 }
 130
 131 static void pmac_ide_transfer_cb(void *opaque, int ret)
 132 {
 133     DBDMA_io *io = opaque;
 134     MACIOIDEState *m = io->opaque;
 135     IDEState *s = idebus_active_if(&m->bus);
 136     int64_t offset;
 137
 138     MACIO_DPRINTF("pmac_ide_transfer_cb\n");
 139
 140     if (ret < 0) {
 141         MACIO_DPRINTF("DMA error: %d\n", ret);
 142         qemu_sglist_destroy(&s->sg);
 143         ide_dma_error(s);
 144         goto done;
 145     }
 146
 147     if (!m->dma_active) {
 148         MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
 149                       s->nsector, io->len, s->status);
 150         /* data not ready yet, wait for the channel to get restarted */
 151         io->processing = false;
 152         return;
 153     }
 154
 155     if (s->io_buffer_size <= 0) {
 156         MACIO_DPRINTF("End of IDE transfer\n");
 157         qemu_sglist_destroy(&s->sg);
 158         s->status = READY_STAT | SEEK_STAT;
 159         ide_set_irq(s->bus);
 160         m->dma_active = false;
 161         goto done;
 162     }
 163
 164     if (io->len == 0) {
 165         MACIO_DPRINTF("End of DMA transfer\n");
 166         goto done;
 167     }
 168
 169     /* Calculate number of sectors */
 170     offset = (ide_get_sector(s) << 9) + s->io_buffer_index;
 171
 172     qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
 173                      &address_space_memory);
 174     qemu_sglist_add(&s->sg, io->addr, io->len);
 175     s->io_buffer_size -= io->len;
 176     s->io_buffer_index += io->len;
 177     io->len = 0;
 178
 179     switch (s->dma_cmd) {
 180     case IDE_DMA_READ:
 181         s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, offset, 0x1,
 182                                           pmac_ide_atapi_transfer_cb, io);
 183         break;
 184     case IDE_DMA_WRITE:
 185         s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, offset, 0x1,
 186                                            pmac_ide_transfer_cb, io);
 187         break;
 188     case IDE_DMA_TRIM:
 189         s->bus->dma->aiocb = dma_blk_io(blk_get_aio_context(s->blk), &s->sg,
 190                                         offset, 0x1, ide_issue_trim, s->blk,
 191                                         pmac_ide_transfer_cb, io,
 192                                         DMA_DIRECTION_TO_DEVICE);
 193         break;
 194     default:
 195         abort();
 196     }
 197
 198     return;
 199
 200 done:
 201     dma_memory_unmap(&address_space_memory, io->dma_mem, io->dma_len,
 202                      io->dir, io->dma_len);
 203
 204     if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
 205         if (ret < 0) {
 206             block_acct_failed(blk_get_stats(s->blk), &s->acct);
 207         } else {
 208             block_acct_done(blk_get_stats(s->blk), &s->acct);
 209         }
 210     }
 211
 212     ide_set_inactive(s, false);
 213     io->dma_end(opaque);
 214 }
 215
 216 static void pmac_ide_transfer(DBDMA_io *io)
 217 {
 218     MACIOIDEState *m = io->opaque;
 219     IDEState *s = idebus_active_if(&m->bus);
 220
 221     MACIO_DPRINTF("\n");
 222
 223     if (s->drive_kind == IDE_CD) {
 224         block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
 225                          BLOCK_ACCT_READ);
 226
 227         pmac_ide_atapi_transfer_cb(io, 0);
 228         return;
 229     }
 230
 231     switch (s->dma_cmd) {
 232     case IDE_DMA_READ:
 233         block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
 234                          BLOCK_ACCT_READ);
 235         break;
 236     case IDE_DMA_WRITE:
 237         block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
 238                          BLOCK_ACCT_WRITE);
 239         break;
 240     default:
 241         break;
 242     }
 243
 244     pmac_ide_transfer_cb(io, 0);
 245 }
 246
 247 static void pmac_ide_flush(DBDMA_io *io)
 248 {
 249     MACIOIDEState *m = io->opaque;
 250     IDEState *s = idebus_active_if(&m->bus);
 251
 252     if (s->bus->dma->aiocb) {
 253         blk_drain(s->blk);
 254     }
 255 }
 256
 257 /* PowerMac IDE memory IO */
 258 static uint64_t pmac_ide_read(void *opaque, hwaddr addr, unsigned size)
 259 {
 260     MACIOIDEState *d = opaque;
 261     uint64_t retval = 0xffffffff;
 262     int reg = addr >> 4;
 263
 264     switch (reg) {
 265     case 0x0:
 266         if (size == 2) {
 267             retval = ide_data_readw(&d->bus, 0);
 268         } else if (size == 4) {
 269             retval = ide_data_readl(&d->bus, 0);
 270         }
 271         break;
 272     case 0x1 ... 0x7:
 273         if (size == 1) {
 274             retval = ide_ioport_read(&d->bus, reg);
 275         }
 276         break;
 277     case 0x8:
 278     case 0x16:
 279         if (size == 1) {
 280             retval = ide_status_read(&d->bus, 0);
 281         }
 282         break;
 283     case 0x20:
 284         if (size == 4) {
 285             retval = d->timing_reg;
 286         }
 287         break;
 288     case 0x30:
 289         /* This is an interrupt state register that only exists
 290          * in the KeyLargo and later variants. Bit 0x8000_0000
 291          * latches the DMA interrupt and has to be written to
 292          * clear. Bit 0x4000_0000 is an image of the disk
 293          * interrupt. MacOS X relies on this and will hang if
 294          * we don't provide at least the disk interrupt
 295          */
 296         if (size == 4) {
 297             retval = d->irq_reg;
 298         }
 299         break;
 300     }
 301
 302     return retval;
 303 }
 304
 305
 306 static void pmac_ide_write(void *opaque, hwaddr addr, uint64_t val,
 307                            unsigned size)
 308 {
 309     MACIOIDEState *d = opaque;
 310     int reg = addr >> 4;
 311
 312     switch (reg) {
 313     case 0x0:
 314         if (size == 2) {
 315             ide_data_writew(&d->bus, 0, val);
 316         } else if (size == 4) {
 317             ide_data_writel(&d->bus, 0, val);
 318         }
 319         break;
 320     case 0x1 ... 0x7:
 321         if (size == 1) {
 322             ide_ioport_write(&d->bus, reg, val);
 323         }
 324         break;
 325     case 0x8:
 326     case 0x16:
 327         if (size == 1) {
 328             ide_cmd_write(&d->bus, 0, val);
 329         }
 330         break;
 331     case 0x20:
 332         if (size == 4) {
 333             d->timing_reg = val;
 334         }
 335         break;
 336     case 0x30:
 337         if (size == 4) {
 338             if (val & 0x80000000u) {
 339                 d->irq_reg &= 0x7fffffff;
 340             }
 341         }
 342         break;
 343     }
 344 }
 345
 346 static const MemoryRegionOps pmac_ide_ops = {
 347     .read = pmac_ide_read,
 348     .write = pmac_ide_write,
 349     .valid.min_access_size = 1,
 350     .valid.max_access_size = 4,
 351     .endianness = DEVICE_LITTLE_ENDIAN,
 352 };
 353
 354 static const VMStateDescription vmstate_pmac = {
 355     .name = "ide",
 356     .version_id = 4,
 357     .minimum_version_id = 0,
 358     .fields = (VMStateField[]) {
 359         VMSTATE_IDE_BUS(bus, MACIOIDEState),
 360         VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
 361         VMSTATE_BOOL(dma_active, MACIOIDEState),
 362         VMSTATE_END_OF_LIST()
 363     }
 364 };
 365
 366 static void macio_ide_reset(DeviceState *dev)
 367 {
 368     MACIOIDEState *d = MACIO_IDE(dev);
 369
 370     ide_bus_reset(&d->bus);
 371 }
 372
 373 static int ide_nop_int(IDEDMA *dma, int x)
 374 {
 375     return 0;
 376 }
 377
 378 static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
 379 {
 380     return 0;
 381 }
 382
 383 static void ide_dbdma_start(IDEDMA *dma, IDEState *s,
 384                             BlockCompletionFunc *cb)
 385 {
 386     MACIOIDEState *m = container_of(dma, MACIOIDEState, dma);
 387
 388     s->io_buffer_index = 0;
 389     if (s->drive_kind == IDE_CD) {
 390         s->io_buffer_size = s->packet_transfer_size;
 391     } else {
 392         s->io_buffer_size = s->nsector * BDRV_SECTOR_SIZE;
 393     }
 394
 395     MACIO_DPRINTF("\n\n------------ IDE transfer\n");
 396     MACIO_DPRINTF("buffer_size: %x   buffer_index: %x\n",
 397                   s->io_buffer_size, s->io_buffer_index);
 398     MACIO_DPRINTF("lba: %x    size: %x\n", s->lba, s->io_buffer_size);
 399     MACIO_DPRINTF("-------------------------\n");
 400
 401     m->dma_active = true;
 402     DBDMA_kick(m->dbdma);
 403 }
 404
 405 static const IDEDMAOps dbdma_ops = {
 406     .start_dma      = ide_dbdma_start,
 407     .prepare_buf    = ide_nop_int32,
 408     .rw_buf         = ide_nop_int,
 409 };
 410
 411 static void macio_ide_realizefn(DeviceState *dev, Error **errp)
 412 {
 413     MACIOIDEState *s = MACIO_IDE(dev);
 414
 415     ide_init2(&s->bus, s->ide_irq);
 416
 417     /* Register DMA callbacks */
 418     s->dma.ops = &dbdma_ops;
 419     s->bus.dma = &s->dma;
 420 }
 421
 422 static void pmac_ide_irq(void *opaque, int n, int level)
 423 {
 424     MACIOIDEState *s = opaque;
 425     uint32_t mask = 0x80000000u >> n;
 426
 427     /* We need to reflect the IRQ state in the irq register */
 428     if (level) {
 429         s->irq_reg |= mask;
 430     } else {
 431         s->irq_reg &= ~mask;
 432     }
 433
 434     if (n) {
 435         qemu_set_irq(s->real_ide_irq, level);
 436     } else {
 437         qemu_set_irq(s->real_dma_irq, level);
 438     }
 439 }
 440
 441 static void macio_ide_initfn(Object *obj)
 442 {
 443     SysBusDevice *d = SYS_BUS_DEVICE(obj);
 444     MACIOIDEState *s = MACIO_IDE(obj);
 445
 446     ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
 447     memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
 448     sysbus_init_mmio(d, &s->mem);
 449     sysbus_init_irq(d, &s->real_ide_irq);
 450     sysbus_init_irq(d, &s->real_dma_irq);
 451     s->dma_irq = qemu_allocate_irq(pmac_ide_irq, s, 0);
 452     s->ide_irq = qemu_allocate_irq(pmac_ide_irq, s, 1);
 453
 454     object_property_add_link(obj, "dbdma", TYPE_MAC_DBDMA,
 455                              (Object **) &s->dbdma,
 456                              qdev_prop_allow_set_link_before_realize, 0, NULL);
 457 }
 458
 459 static Property macio_ide_properties[] = {
 460     DEFINE_PROP_UINT32("channel", MACIOIDEState, channel, 0),
 461     DEFINE_PROP_END_OF_LIST(),
 462 };
 463
 464 static void macio_ide_class_init(ObjectClass *oc, void *data)
 465 {
 466     DeviceClass *dc = DEVICE_CLASS(oc);
 467
 468     dc->realize = macio_ide_realizefn;
 469     dc->reset = macio_ide_reset;
 470     dc->props = macio_ide_properties;
 471     dc->vmsd = &vmstate_pmac;
 472     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 473 }
 474
 475 static const TypeInfo macio_ide_type_info = {
 476     .name = TYPE_MACIO_IDE,
 477     .parent = TYPE_SYS_BUS_DEVICE,
 478     .instance_size = sizeof(MACIOIDEState),
 479     .instance_init = macio_ide_initfn,
 480     .class_init = macio_ide_class_init,
 481 };
 482
 483 static void macio_ide_register_types(void)
 484 {
 485     type_register_static(&macio_ide_type_info);
 486 }
 487
 488 /* hd_table must contain 2 block drivers */
 489 void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
 490 {
 491     int i;
 492
 493     for (i = 0; i < 2; i++) {
 494         if (hd_table[i]) {
 495             ide_create_drive(&s->bus, i, hd_table[i]);
 496         }
 497     }
 498 }
 499
 500 void macio_ide_register_dma(MACIOIDEState *s)
 501 {
 502     DBDMA_register_channel(s->dbdma, s->channel, s->dma_irq,
 503                            pmac_ide_transfer, pmac_ide_flush, s);
 504 }
 505
 506 type_init(macio_ide_register_types)