user-exec.c

   1 /*
   2  *  User emulator execution
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "config.h"
  20 #include "cpu.h"
  21 #include "disas/disas.h"
  22 #include "tcg.h"
  23 #include "qemu/bitops.h"
  24
  25 #undef EAX
  26 #undef ECX
  27 #undef EDX
  28 #undef EBX
  29 #undef ESP
  30 #undef EBP
  31 #undef ESI
  32 #undef EDI
  33 #undef EIP
  34 #include <signal.h>
  35 #ifdef __linux__
  36 #include <sys/ucontext.h>
  37 #endif
  38
  39 //#define DEBUG_SIGNAL
  40
  41 static void exception_action(CPUArchState *env1)
  42 {
  43 #if defined(TARGET_I386)
  44     raise_exception_err(env1, env1->exception_index, env1->error_code);
  45 #else
  46     cpu_loop_exit(env1);
  47 #endif
  48 }
  49
  50 /* exit the current TB from a signal handler. The host registers are
  51    restored in a state compatible with the CPU emulator
  52  */
  53 void cpu_resume_from_signal(CPUArchState *env1, void *puc)
  54 {
  55 #ifdef __linux__
  56     struct ucontext *uc = puc;
  57 #elif defined(__OpenBSD__)
  58     struct sigcontext *uc = puc;
  59 #endif
  60
  61     if (puc) {
  62         /* XXX: use siglongjmp ? */
  63 #ifdef __linux__
  64 #ifdef __ia64
  65         sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
  66 #else
  67         sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
  68 #endif
  69 #elif defined(__OpenBSD__)
  70         sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
  71 #endif
  72     }
  73     env1->exception_index = -1;
  74     siglongjmp(env1->jmp_env, 1);
  75 }
  76
  77 /* 'pc' is the host PC at which the exception was raised. 'address' is
  78    the effective address of the memory exception. 'is_write' is 1 if a
  79    write caused the exception and otherwise 0'. 'old_set' is the
  80    signal set which should be restored */
  81 static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
  82                                     int is_write, sigset_t *old_set,
  83                                     void *puc)
  84 {
  85     CPUArchState *env;
  86     int ret;
  87
  88 #if defined(DEBUG_SIGNAL)
  89     qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
  90                 pc, address, is_write, *(unsigned long *)old_set);
  91 #endif
  92     /* XXX: locking issue */
  93     if (is_write && h2g_valid(address)
  94         && page_unprotect(h2g(address), pc, puc)) {
  95         return 1;
  96     }
  97
  98     /* Convert forcefully to guest address space, invalid addresses
  99        are still valid segv ones */
 100     address = h2g_nocheck(address);
 101
 102     env = current_cpu->env_ptr;
 103     /* see if it is an MMU fault */
 104     ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX);
 105     if (ret < 0) {
 106         return 0; /* not an MMU fault */
 107     }
 108     if (ret == 0) {
 109         return 1; /* the MMU fault was handled without causing real CPU fault */
 110     }
 111     /* now we have a real cpu fault */
 112     cpu_restore_state(env, pc);
 113
 114     /* we restore the process signal mask as the sigreturn should
 115        do it (XXX: use sigsetjmp) */
 116     sigprocmask(SIG_SETMASK, old_set, NULL);
 117     exception_action(env);
 118
 119     /* never comes here */
 120     return 1;
 121 }
 122
 123 #if defined(__i386__)
 124
 125 #if defined(__APPLE__)
 126 #include <sys/ucontext.h>
 127
 128 #define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext->ss.eip))
 129 #define TRAP_sig(context)    ((context)->uc_mcontext->es.trapno)
 130 #define ERROR_sig(context)   ((context)->uc_mcontext->es.err)
 131 #define MASK_sig(context)    ((context)->uc_sigmask)
 132 #elif defined(__NetBSD__)
 133 #include <ucontext.h>
 134
 135 #define EIP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_EIP])
 136 #define TRAP_sig(context)    ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 137 #define ERROR_sig(context)   ((context)->uc_mcontext.__gregs[_REG_ERR])
 138 #define MASK_sig(context)    ((context)->uc_sigmask)
 139 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 140 #include <ucontext.h>
 141
 142 #define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
 143 #define TRAP_sig(context)    ((context)->uc_mcontext.mc_trapno)
 144 #define ERROR_sig(context)   ((context)->uc_mcontext.mc_err)
 145 #define MASK_sig(context)    ((context)->uc_sigmask)
 146 #elif defined(__OpenBSD__)
 147 #define EIP_sig(context)     ((context)->sc_eip)
 148 #define TRAP_sig(context)    ((context)->sc_trapno)
 149 #define ERROR_sig(context)   ((context)->sc_err)
 150 #define MASK_sig(context)    ((context)->sc_mask)
 151 #else
 152 #define EIP_sig(context)     ((context)->uc_mcontext.gregs[REG_EIP])
 153 #define TRAP_sig(context)    ((context)->uc_mcontext.gregs[REG_TRAPNO])
 154 #define ERROR_sig(context)   ((context)->uc_mcontext.gregs[REG_ERR])
 155 #define MASK_sig(context)    ((context)->uc_sigmask)
 156 #endif
 157
 158 int cpu_signal_handler(int host_signum, void *pinfo,
 159                        void *puc)
 160 {
 161     siginfo_t *info = pinfo;
 162 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 163     ucontext_t *uc = puc;
 164 #elif defined(__OpenBSD__)
 165     struct sigcontext *uc = puc;
 166 #else
 167     struct ucontext *uc = puc;
 168 #endif
 169     unsigned long pc;
 170     int trapno;
 171
 172 #ifndef REG_EIP
 173 /* for glibc 2.1 */
 174 #define REG_EIP    EIP
 175 #define REG_ERR    ERR
 176 #define REG_TRAPNO TRAPNO
 177 #endif
 178     pc = EIP_sig(uc);
 179     trapno = TRAP_sig(uc);
 180     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 181                              trapno == 0xe ?
 182                              (ERROR_sig(uc) >> 1) & 1 : 0,
 183                              &MASK_sig(uc), puc);
 184 }
 185
 186 #elif defined(__x86_64__)
 187
 188 #ifdef __NetBSD__
 189 #define PC_sig(context)       _UC_MACHINE_PC(context)
 190 #define TRAP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 191 #define ERROR_sig(context)    ((context)->uc_mcontext.__gregs[_REG_ERR])
 192 #define MASK_sig(context)     ((context)->uc_sigmask)
 193 #elif defined(__OpenBSD__)
 194 #define PC_sig(context)       ((context)->sc_rip)
 195 #define TRAP_sig(context)     ((context)->sc_trapno)
 196 #define ERROR_sig(context)    ((context)->sc_err)
 197 #define MASK_sig(context)     ((context)->sc_mask)
 198 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 199 #include <ucontext.h>
 200
 201 #define PC_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
 202 #define TRAP_sig(context)     ((context)->uc_mcontext.mc_trapno)
 203 #define ERROR_sig(context)    ((context)->uc_mcontext.mc_err)
 204 #define MASK_sig(context)     ((context)->uc_sigmask)
 205 #else
 206 #define PC_sig(context)       ((context)->uc_mcontext.gregs[REG_RIP])
 207 #define TRAP_sig(context)     ((context)->uc_mcontext.gregs[REG_TRAPNO])
 208 #define ERROR_sig(context)    ((context)->uc_mcontext.gregs[REG_ERR])
 209 #define MASK_sig(context)     ((context)->uc_sigmask)
 210 #endif
 211
 212 int cpu_signal_handler(int host_signum, void *pinfo,
 213                        void *puc)
 214 {
 215     siginfo_t *info = pinfo;
 216     unsigned long pc;
 217 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 218     ucontext_t *uc = puc;
 219 #elif defined(__OpenBSD__)
 220     struct sigcontext *uc = puc;
 221 #else
 222     struct ucontext *uc = puc;
 223 #endif
 224
 225     pc = PC_sig(uc);
 226     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 227                              TRAP_sig(uc) == 0xe ?
 228                              (ERROR_sig(uc) >> 1) & 1 : 0,
 229                              &MASK_sig(uc), puc);
 230 }
 231
 232 #elif defined(_ARCH_PPC)
 233
 234 /***********************************************************************
 235  * signal context platform-specific definitions
 236  * From Wine
 237  */
 238 #ifdef linux
 239 /* All Registers access - only for local access */
 240 #define REG_sig(reg_name, context)              \
 241     ((context)->uc_mcontext.regs->reg_name)
 242 /* Gpr Registers access  */
 243 #define GPR_sig(reg_num, context)              REG_sig(gpr[reg_num], context)
 244 /* Program counter */
 245 #define IAR_sig(context)                       REG_sig(nip, context)
 246 /* Machine State Register (Supervisor) */
 247 #define MSR_sig(context)                       REG_sig(msr, context)
 248 /* Count register */
 249 #define CTR_sig(context)                       REG_sig(ctr, context)
 250 /* User's integer exception register */
 251 #define XER_sig(context)                       REG_sig(xer, context)
 252 /* Link register */
 253 #define LR_sig(context)                        REG_sig(link, context)
 254 /* Condition register */
 255 #define CR_sig(context)                        REG_sig(ccr, context)
 256
 257 /* Float Registers access  */
 258 #define FLOAT_sig(reg_num, context)                                     \
 259     (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
 260 #define FPSCR_sig(context) \
 261     (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
 262 /* Exception Registers access */
 263 #define DAR_sig(context)                       REG_sig(dar, context)
 264 #define DSISR_sig(context)                     REG_sig(dsisr, context)
 265 #define TRAP_sig(context)                      REG_sig(trap, context)
 266 #endif /* linux */
 267
 268 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 269 #include <ucontext.h>
 270 #define IAR_sig(context)               ((context)->uc_mcontext.mc_srr0)
 271 #define MSR_sig(context)               ((context)->uc_mcontext.mc_srr1)
 272 #define CTR_sig(context)               ((context)->uc_mcontext.mc_ctr)
 273 #define XER_sig(context)               ((context)->uc_mcontext.mc_xer)
 274 #define LR_sig(context)                ((context)->uc_mcontext.mc_lr)
 275 #define CR_sig(context)                ((context)->uc_mcontext.mc_cr)
 276 /* Exception Registers access */
 277 #define DAR_sig(context)               ((context)->uc_mcontext.mc_dar)
 278 #define DSISR_sig(context)             ((context)->uc_mcontext.mc_dsisr)
 279 #define TRAP_sig(context)              ((context)->uc_mcontext.mc_exc)
 280 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
 281
 282 #ifdef __APPLE__
 283 #include <sys/ucontext.h>
 284 typedef struct ucontext SIGCONTEXT;
 285 /* All Registers access - only for local access */
 286 #define REG_sig(reg_name, context)              \
 287     ((context)->uc_mcontext->ss.reg_name)
 288 #define FLOATREG_sig(reg_name, context)         \
 289     ((context)->uc_mcontext->fs.reg_name)
 290 #define EXCEPREG_sig(reg_name, context)         \
 291     ((context)->uc_mcontext->es.reg_name)
 292 #define VECREG_sig(reg_name, context)           \
 293     ((context)->uc_mcontext->vs.reg_name)
 294 /* Gpr Registers access */
 295 #define GPR_sig(reg_num, context)              REG_sig(r##reg_num, context)
 296 /* Program counter */
 297 #define IAR_sig(context)                       REG_sig(srr0, context)
 298 /* Machine State Register (Supervisor) */
 299 #define MSR_sig(context)                       REG_sig(srr1, context)
 300 #define CTR_sig(context)                       REG_sig(ctr, context)
 301 /* Link register */
 302 #define XER_sig(context)                       REG_sig(xer, context)
 303 /* User's integer exception register */
 304 #define LR_sig(context)                        REG_sig(lr, context)
 305 /* Condition register */
 306 #define CR_sig(context)                        REG_sig(cr, context)
 307 /* Float Registers access */
 308 #define FLOAT_sig(reg_num, context)             \
 309     FLOATREG_sig(fpregs[reg_num], context)
 310 #define FPSCR_sig(context)                      \
 311     ((double)FLOATREG_sig(fpscr, context))
 312 /* Exception Registers access */
 313 /* Fault registers for coredump */
 314 #define DAR_sig(context)                       EXCEPREG_sig(dar, context)
 315 #define DSISR_sig(context)                     EXCEPREG_sig(dsisr, context)
 316 /* number of powerpc exception taken */
 317 #define TRAP_sig(context)                      EXCEPREG_sig(exception, context)
 318 #endif /* __APPLE__ */
 319
 320 int cpu_signal_handler(int host_signum, void *pinfo,
 321                        void *puc)
 322 {
 323     siginfo_t *info = pinfo;
 324 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 325     ucontext_t *uc = puc;
 326 #else
 327     struct ucontext *uc = puc;
 328 #endif
 329     unsigned long pc;
 330     int is_write;
 331
 332     pc = IAR_sig(uc);
 333     is_write = 0;
 334 #if 0
 335     /* ppc 4xx case */
 336     if (DSISR_sig(uc) & 0x00800000) {
 337         is_write = 1;
 338     }
 339 #else
 340     if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
 341         is_write = 1;
 342     }
 343 #endif
 344     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 345                              is_write, &uc->uc_sigmask, puc);
 346 }
 347
 348 #elif defined(__alpha__)
 349
 350 int cpu_signal_handler(int host_signum, void *pinfo,
 351                            void *puc)
 352 {
 353     siginfo_t *info = pinfo;
 354     struct ucontext *uc = puc;
 355     uint32_t *pc = uc->uc_mcontext.sc_pc;
 356     uint32_t insn = *pc;
 357     int is_write = 0;
 358
 359     /* XXX: need kernel patch to get write flag faster */
 360     switch (insn >> 26) {
 361     case 0x0d: /* stw */
 362     case 0x0e: /* stb */
 363     case 0x0f: /* stq_u */
 364     case 0x24: /* stf */
 365     case 0x25: /* stg */
 366     case 0x26: /* sts */
 367     case 0x27: /* stt */
 368     case 0x2c: /* stl */
 369     case 0x2d: /* stq */
 370     case 0x2e: /* stl_c */
 371     case 0x2f: /* stq_c */
 372         is_write = 1;
 373     }
 374
 375     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 376                              is_write, &uc->uc_sigmask, puc);
 377 }
 378 #elif defined(__sparc__)
 379
 380 int cpu_signal_handler(int host_signum, void *pinfo,
 381                        void *puc)
 382 {
 383     siginfo_t *info = pinfo;
 384     int is_write;
 385     uint32_t insn;
 386 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
 387     uint32_t *regs = (uint32_t *)(info + 1);
 388     void *sigmask = (regs + 20);
 389     /* XXX: is there a standard glibc define ? */
 390     unsigned long pc = regs[1];
 391 #else
 392 #ifdef __linux__
 393     struct sigcontext *sc = puc;
 394     unsigned long pc = sc->sigc_regs.tpc;
 395     void *sigmask = (void *)sc->sigc_mask;
 396 #elif defined(__OpenBSD__)
 397     struct sigcontext *uc = puc;
 398     unsigned long pc = uc->sc_pc;
 399     void *sigmask = (void *)(long)uc->sc_mask;
 400 #endif
 401 #endif
 402
 403     /* XXX: need kernel patch to get write flag faster */
 404     is_write = 0;
 405     insn = *(uint32_t *)pc;
 406     if ((insn >> 30) == 3) {
 407         switch ((insn >> 19) & 0x3f) {
 408         case 0x05: /* stb */
 409         case 0x15: /* stba */
 410         case 0x06: /* sth */
 411         case 0x16: /* stha */
 412         case 0x04: /* st */
 413         case 0x14: /* sta */
 414         case 0x07: /* std */
 415         case 0x17: /* stda */
 416         case 0x0e: /* stx */
 417         case 0x1e: /* stxa */
 418         case 0x24: /* stf */
 419         case 0x34: /* stfa */
 420         case 0x27: /* stdf */
 421         case 0x37: /* stdfa */
 422         case 0x26: /* stqf */
 423         case 0x36: /* stqfa */
 424         case 0x25: /* stfsr */
 425         case 0x3c: /* casa */
 426         case 0x3e: /* casxa */
 427             is_write = 1;
 428             break;
 429         }
 430     }
 431     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 432                              is_write, sigmask, NULL);
 433 }
 434
 435 #elif defined(__arm__)
 436
 437 int cpu_signal_handler(int host_signum, void *pinfo,
 438                        void *puc)
 439 {
 440     siginfo_t *info = pinfo;
 441     struct ucontext *uc = puc;
 442     unsigned long pc;
 443     int is_write;
 444
 445 #if defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
 446     pc = uc->uc_mcontext.gregs[R15];
 447 #else
 448     pc = uc->uc_mcontext.arm_pc;
 449 #endif
 450
 451     /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
 452      * later processor; on v5 we will always report this as a read).
 453      */
 454     is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
 455     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 456                              is_write,
 457                              &uc->uc_sigmask, puc);
 458 }
 459
 460 #elif defined(__aarch64__)
 461
 462 int cpu_signal_handler(int host_signum, void *pinfo,
 463                        void *puc)
 464 {
 465     siginfo_t *info = pinfo;
 466     struct ucontext *uc = puc;
 467     uint64_t pc;
 468     int is_write = 0; /* XXX how to determine? */
 469
 470     pc = uc->uc_mcontext.pc;
 471     return handle_cpu_signal(pc, (uint64_t)info->si_addr,
 472                              is_write, &uc->uc_sigmask, puc);
 473 }
 474
 475 #elif defined(__mc68000)
 476
 477 int cpu_signal_handler(int host_signum, void *pinfo,
 478                        void *puc)
 479 {
 480     siginfo_t *info = pinfo;
 481     struct ucontext *uc = puc;
 482     unsigned long pc;
 483     int is_write;
 484
 485     pc = uc->uc_mcontext.gregs[16];
 486     /* XXX: compute is_write */
 487     is_write = 0;
 488     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 489                              is_write,
 490                              &uc->uc_sigmask, puc);
 491 }
 492
 493 #elif defined(__ia64)
 494
 495 #ifndef __ISR_VALID
 496   /* This ought to be in <bits/siginfo.h>... */
 497 # define __ISR_VALID    1
 498 #endif
 499
 500 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
 501 {
 502     siginfo_t *info = pinfo;
 503     struct ucontext *uc = puc;
 504     unsigned long ip;
 505     int is_write = 0;
 506
 507     ip = uc->uc_mcontext.sc_ip;
 508     switch (host_signum) {
 509     case SIGILL:
 510     case SIGFPE:
 511     case SIGSEGV:
 512     case SIGBUS:
 513     case SIGTRAP:
 514         if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
 515             /* ISR.W (write-access) is bit 33:  */
 516             is_write = (info->si_isr >> 33) & 1;
 517         }
 518         break;
 519
 520     default:
 521         break;
 522     }
 523     return handle_cpu_signal(ip, (unsigned long)info->si_addr,
 524                              is_write,
 525                              (sigset_t *)&uc->uc_sigmask, puc);
 526 }
 527
 528 #elif defined(__s390__)
 529
 530 int cpu_signal_handler(int host_signum, void *pinfo,
 531                        void *puc)
 532 {
 533     siginfo_t *info = pinfo;
 534     struct ucontext *uc = puc;
 535     unsigned long pc;
 536     uint16_t *pinsn;
 537     int is_write = 0;
 538
 539     pc = uc->uc_mcontext.psw.addr;
 540
 541     /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
 542        of the normal 2 arguments.  The 3rd argument contains the "int_code"
 543        from the hardware which does in fact contain the is_write value.
 544        The rt signal handler, as far as I can tell, does not give this value
 545        at all.  Not that we could get to it from here even if it were.  */
 546     /* ??? This is not even close to complete, since it ignores all
 547        of the read-modify-write instructions.  */
 548     pinsn = (uint16_t *)pc;
 549     switch (pinsn[0] >> 8) {
 550     case 0x50: /* ST */
 551     case 0x42: /* STC */
 552     case 0x40: /* STH */
 553         is_write = 1;
 554         break;
 555     case 0xc4: /* RIL format insns */
 556         switch (pinsn[0] & 0xf) {
 557         case 0xf: /* STRL */
 558         case 0xb: /* STGRL */
 559         case 0x7: /* STHRL */
 560             is_write = 1;
 561         }
 562         break;
 563     case 0xe3: /* RXY format insns */
 564         switch (pinsn[2] & 0xff) {
 565         case 0x50: /* STY */
 566         case 0x24: /* STG */
 567         case 0x72: /* STCY */
 568         case 0x70: /* STHY */
 569         case 0x8e: /* STPQ */
 570         case 0x3f: /* STRVH */
 571         case 0x3e: /* STRV */
 572         case 0x2f: /* STRVG */
 573             is_write = 1;
 574         }
 575         break;
 576     }
 577     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 578                              is_write, &uc->uc_sigmask, puc);
 579 }
 580
 581 #elif defined(__mips__)
 582
 583 int cpu_signal_handler(int host_signum, void *pinfo,
 584                        void *puc)
 585 {
 586     siginfo_t *info = pinfo;
 587     struct ucontext *uc = puc;
 588     greg_t pc = uc->uc_mcontext.pc;
 589     int is_write;
 590
 591     /* XXX: compute is_write */
 592     is_write = 0;
 593     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 594                              is_write, &uc->uc_sigmask, puc);
 595 }
 596
 597 #elif defined(__hppa__)
 598
 599 int cpu_signal_handler(int host_signum, void *pinfo,
 600                        void *puc)
 601 {
 602     siginfo_t *info = pinfo;
 603     struct ucontext *uc = puc;
 604     unsigned long pc = uc->uc_mcontext.sc_iaoq[0];
 605     uint32_t insn = *(uint32_t *)pc;
 606     int is_write = 0;
 607
 608     /* XXX: need kernel patch to get write flag faster.  */
 609     switch (insn >> 26) {
 610     case 0x1a: /* STW */
 611     case 0x19: /* STH */
 612     case 0x18: /* STB */
 613     case 0x1b: /* STWM */
 614         is_write = 1;
 615         break;
 616
 617     case 0x09: /* CSTWX, FSTWX, FSTWS */
 618     case 0x0b: /* CSTDX, FSTDX, FSTDS */
 619         /* Distinguish from coprocessor load ... */
 620         is_write = (insn >> 9) & 1;
 621         break;
 622
 623     case 0x03:
 624         switch ((insn >> 6) & 15) {
 625         case 0xa: /* STWS */
 626         case 0x9: /* STHS */
 627         case 0x8: /* STBS */
 628         case 0xe: /* STWAS */
 629         case 0xc: /* STBYS */
 630             is_write = 1;
 631         }
 632         break;
 633     }
 634
 635     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 636                              is_write, &uc->uc_sigmask, puc);
 637 }
 638
 639 #else
 640
 641 #error host CPU specific signal handler needed
 642
 643 #endif