hw/arm/highbank.c

   1 /*
   2  * Calxeda Highbank SoC emulation
   3  *
   4  * Copyright (c) 2010-2012 Calxeda
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  */
  19
  20 #include "hw/sysbus.h"
  21 #include "hw/arm/arm.h"
  22 #include "hw/devices.h"
  23 #include "hw/loader.h"
  24 #include "net/net.h"
  25 #include "sysemu/sysemu.h"
  26 #include "hw/boards.h"
  27 #include "sysemu/block-backend.h"
  28 #include "exec/address-spaces.h"
  29 #include "qemu/error-report.h"
  30
  31 #define SMP_BOOT_ADDR           0x100
  32 #define SMP_BOOT_REG            0x40
  33 #define MPCORE_PERIPHBASE       0xfff10000
  34
  35 #define NIRQ_GIC                160
  36
  37 /* Board init.  */
  38
  39 static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
  40 {
  41     int n;
  42     uint32_t smpboot[] = {
  43         0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
  44         0xe210000f, /* ands r0, r0, #0x0f */
  45         0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
  46         0xe0830200, /* add r0, r3, r0, lsl #4 */
  47         0xe59f2024, /* ldr r2, privbase */
  48         0xe3a01001, /* mov r1, #1 */
  49         0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
  50         0xe3a010ff, /* mov r1, #0xff */
  51         0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
  52         0xf57ff04f, /* dsb */
  53         0xe320f003, /* wfi */
  54         0xe5901000, /* ldr     r1, [r0] */
  55         0xe1110001, /* tst     r1, r1 */
  56         0x0afffffb, /* beq     <wfi> */
  57         0xe12fff11, /* bx      r1 */
  58         MPCORE_PERIPHBASE   /* privbase: MPCore peripheral base address.  */
  59     };
  60     for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
  61         smpboot[n] = tswap32(smpboot[n]);
  62     }
  63     rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
  64 }
  65
  66 static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
  67 {
  68     CPUARMState *env = &cpu->env;
  69
  70     switch (info->nb_cpus) {
  71     case 4:
  72         address_space_stl_notdirty(&address_space_memory,
  73                                    SMP_BOOT_REG + 0x30, 0,
  74                                    MEMTXATTRS_UNSPECIFIED, NULL);
  75     case 3:
  76         address_space_stl_notdirty(&address_space_memory,
  77                                    SMP_BOOT_REG + 0x20, 0,
  78                                    MEMTXATTRS_UNSPECIFIED, NULL);
  79     case 2:
  80         address_space_stl_notdirty(&address_space_memory,
  81                                    SMP_BOOT_REG + 0x10, 0,
  82                                    MEMTXATTRS_UNSPECIFIED, NULL);
  83         env->regs[15] = SMP_BOOT_ADDR;
  84         break;
  85     default:
  86         break;
  87     }
  88 }
  89
  90 #define NUM_REGS      0x200
  91 static void hb_regs_write(void *opaque, hwaddr offset,
  92                           uint64_t value, unsigned size)
  93 {
  94     uint32_t *regs = opaque;
  95
  96     if (offset == 0xf00) {
  97         if (value == 1 || value == 2) {
  98             qemu_system_reset_request();
  99         } else if (value == 3) {
 100             qemu_system_shutdown_request();
 101         }
 102     }
 103
 104     regs[offset/4] = value;
 105 }
 106
 107 static uint64_t hb_regs_read(void *opaque, hwaddr offset,
 108                              unsigned size)
 109 {
 110     uint32_t *regs = opaque;
 111     uint32_t value = regs[offset/4];
 112
 113     if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
 114         value |= 0x30000000;
 115     }
 116
 117     return value;
 118 }
 119
 120 static const MemoryRegionOps hb_mem_ops = {
 121     .read = hb_regs_read,
 122     .write = hb_regs_write,
 123     .endianness = DEVICE_NATIVE_ENDIAN,
 124 };
 125
 126 #define TYPE_HIGHBANK_REGISTERS "highbank-regs"
 127 #define HIGHBANK_REGISTERS(obj) \
 128     OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)
 129
 130 typedef struct {
 131     /*< private >*/
 132     SysBusDevice parent_obj;
 133     /*< public >*/
 134
 135     MemoryRegion iomem;
 136     uint32_t regs[NUM_REGS];
 137 } HighbankRegsState;
 138
 139 static VMStateDescription vmstate_highbank_regs = {
 140     .name = "highbank-regs",
 141     .version_id = 0,
 142     .minimum_version_id = 0,
 143     .fields = (VMStateField[]) {
 144         VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
 145         VMSTATE_END_OF_LIST(),
 146     },
 147 };
 148
 149 static void highbank_regs_reset(DeviceState *dev)
 150 {
 151     HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
 152
 153     s->regs[0x40] = 0x05F20121;
 154     s->regs[0x41] = 0x2;
 155     s->regs[0x42] = 0x05F30121;
 156     s->regs[0x43] = 0x05F40121;
 157 }
 158
 159 static int highbank_regs_init(SysBusDevice *dev)
 160 {
 161     HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
 162
 163     memory_region_init_io(&s->iomem, OBJECT(s), &hb_mem_ops, s->regs,
 164                           "highbank_regs", 0x1000);
 165     sysbus_init_mmio(dev, &s->iomem);
 166
 167     return 0;
 168 }
 169
 170 static void highbank_regs_class_init(ObjectClass *klass, void *data)
 171 {
 172     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
 173     DeviceClass *dc = DEVICE_CLASS(klass);
 174
 175     sbc->init = highbank_regs_init;
 176     dc->desc = "Calxeda Highbank registers";
 177     dc->vmsd = &vmstate_highbank_regs;
 178     dc->reset = highbank_regs_reset;
 179 }
 180
 181 static const TypeInfo highbank_regs_info = {
 182     .name          = TYPE_HIGHBANK_REGISTERS,
 183     .parent        = TYPE_SYS_BUS_DEVICE,
 184     .instance_size = sizeof(HighbankRegsState),
 185     .class_init    = highbank_regs_class_init,
 186 };
 187
 188 static void highbank_regs_register_types(void)
 189 {
 190     type_register_static(&highbank_regs_info);
 191 }
 192
 193 type_init(highbank_regs_register_types)
 194
 195 static struct arm_boot_info highbank_binfo;
 196
 197 enum cxmachines {
 198     CALXEDA_HIGHBANK,
 199     CALXEDA_MIDWAY,
 200 };
 201
 202 /* ram_size must be set to match the upper bound of memory in the
 203  * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
 204  * normally 0xff900000 or -m 4089. When running this board on a
 205  * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
 206  * device tree and pass -m 2047 to QEMU.
 207  */
 208 static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
 209 {
 210     ram_addr_t ram_size = machine->ram_size;
 211     const char *cpu_model = machine->cpu_model;
 212     const char *kernel_filename = machine->kernel_filename;
 213     const char *kernel_cmdline = machine->kernel_cmdline;
 214     const char *initrd_filename = machine->initrd_filename;
 215     DeviceState *dev = NULL;
 216     SysBusDevice *busdev;
 217     qemu_irq pic[128];
 218     int n;
 219     qemu_irq cpu_irq[4];
 220     MemoryRegion *sysram;
 221     MemoryRegion *dram;
 222     MemoryRegion *sysmem;
 223     char *sysboot_filename;
 224
 225     if (!cpu_model) {
 226         switch (machine_id) {
 227         case CALXEDA_HIGHBANK:
 228             cpu_model = "cortex-a9";
 229             break;
 230         case CALXEDA_MIDWAY:
 231             cpu_model = "cortex-a15";
 232             break;
 233         }
 234     }
 235
 236     for (n = 0; n < smp_cpus; n++) {
 237         ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
 238         Object *cpuobj;
 239         ARMCPU *cpu;
 240         Error *err = NULL;
 241
 242         if (!oc) {
 243             error_report("Unable to find CPU definition");
 244             exit(1);
 245         }
 246
 247         cpuobj = object_new(object_class_get_name(oc));
 248         cpu = ARM_CPU(cpuobj);
 249
 250         /* By default A9 and A15 CPUs have EL3 enabled.  This board does not
 251          * currently support EL3 so the CPU EL3 property is disabled before
 252          * realization.
 253          */
 254         if (object_property_find(cpuobj, "has_el3", NULL)) {
 255             object_property_set_bool(cpuobj, false, "has_el3", &err);
 256             if (err) {
 257                 error_report_err(err);
 258                 exit(1);
 259             }
 260         }
 261
 262         if (object_property_find(cpuobj, "reset-cbar", NULL)) {
 263             object_property_set_int(cpuobj, MPCORE_PERIPHBASE,
 264                                     "reset-cbar", &error_abort);
 265         }
 266         object_property_set_bool(cpuobj, true, "realized", &err);
 267         if (err) {
 268             error_report_err(err);
 269             exit(1);
 270         }
 271         cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
 272     }
 273
 274     sysmem = get_system_memory();
 275     dram = g_new(MemoryRegion, 1);
 276     memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size);
 277     /* SDRAM at address zero.  */
 278     memory_region_add_subregion(sysmem, 0, dram);
 279
 280     sysram = g_new(MemoryRegion, 1);
 281     memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000,
 282                            &error_abort);
 283     memory_region_add_subregion(sysmem, 0xfff88000, sysram);
 284     if (bios_name != NULL) {
 285         sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 286         if (sysboot_filename != NULL) {
 287             if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) {
 288                 hw_error("Unable to load %s\n", bios_name);
 289             }
 290             g_free(sysboot_filename);
 291         } else {
 292            hw_error("Unable to find %s\n", bios_name);
 293         }
 294     }
 295
 296     switch (machine_id) {
 297     case CALXEDA_HIGHBANK:
 298         dev = qdev_create(NULL, "l2x0");
 299         qdev_init_nofail(dev);
 300         busdev = SYS_BUS_DEVICE(dev);
 301         sysbus_mmio_map(busdev, 0, 0xfff12000);
 302
 303         dev = qdev_create(NULL, "a9mpcore_priv");
 304         break;
 305     case CALXEDA_MIDWAY:
 306         dev = qdev_create(NULL, "a15mpcore_priv");
 307         break;
 308     }
 309     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 310     qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
 311     qdev_init_nofail(dev);
 312     busdev = SYS_BUS_DEVICE(dev);
 313     sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
 314     for (n = 0; n < smp_cpus; n++) {
 315         sysbus_connect_irq(busdev, n, cpu_irq[n]);
 316     }
 317
 318     for (n = 0; n < 128; n++) {
 319         pic[n] = qdev_get_gpio_in(dev, n);
 320     }
 321
 322     dev = qdev_create(NULL, "sp804");
 323     qdev_prop_set_uint32(dev, "freq0", 150000000);
 324     qdev_prop_set_uint32(dev, "freq1", 150000000);
 325     qdev_init_nofail(dev);
 326     busdev = SYS_BUS_DEVICE(dev);
 327     sysbus_mmio_map(busdev, 0, 0xfff34000);
 328     sysbus_connect_irq(busdev, 0, pic[18]);
 329     sysbus_create_simple("pl011", 0xfff36000, pic[20]);
 330
 331     dev = qdev_create(NULL, "highbank-regs");
 332     qdev_init_nofail(dev);
 333     busdev = SYS_BUS_DEVICE(dev);
 334     sysbus_mmio_map(busdev, 0, 0xfff3c000);
 335
 336     sysbus_create_simple("pl061", 0xfff30000, pic[14]);
 337     sysbus_create_simple("pl061", 0xfff31000, pic[15]);
 338     sysbus_create_simple("pl061", 0xfff32000, pic[16]);
 339     sysbus_create_simple("pl061", 0xfff33000, pic[17]);
 340     sysbus_create_simple("pl031", 0xfff35000, pic[19]);
 341     sysbus_create_simple("pl022", 0xfff39000, pic[23]);
 342
 343     sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]);
 344
 345     if (nd_table[0].used) {
 346         qemu_check_nic_model(&nd_table[0], "xgmac");
 347         dev = qdev_create(NULL, "xgmac");
 348         qdev_set_nic_properties(dev, &nd_table[0]);
 349         qdev_init_nofail(dev);
 350         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
 351         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
 352         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
 353         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
 354
 355         qemu_check_nic_model(&nd_table[1], "xgmac");
 356         dev = qdev_create(NULL, "xgmac");
 357         qdev_set_nic_properties(dev, &nd_table[1]);
 358         qdev_init_nofail(dev);
 359         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
 360         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
 361         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
 362         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
 363     }
 364
 365     highbank_binfo.ram_size = ram_size;
 366     highbank_binfo.kernel_filename = kernel_filename;
 367     highbank_binfo.kernel_cmdline = kernel_cmdline;
 368     highbank_binfo.initrd_filename = initrd_filename;
 369     /* highbank requires a dtb in order to boot, and the dtb will override
 370      * the board ID. The following value is ignored, so set it to -1 to be
 371      * clear that the value is meaningless.
 372      */
 373     highbank_binfo.board_id = -1;
 374     highbank_binfo.nb_cpus = smp_cpus;
 375     highbank_binfo.loader_start = 0;
 376     highbank_binfo.write_secondary_boot = hb_write_secondary;
 377     highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
 378     arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo);
 379 }
 380
 381 static void highbank_init(MachineState *machine)
 382 {
 383     calxeda_init(machine, CALXEDA_HIGHBANK);
 384 }
 385
 386 static void midway_init(MachineState *machine)
 387 {
 388     calxeda_init(machine, CALXEDA_MIDWAY);
 389 }
 390
 391 static QEMUMachine highbank_machine = {
 392     .name = "highbank",
 393     .desc = "Calxeda Highbank (ECX-1000)",
 394     .init = highbank_init,
 395     .block_default_type = IF_SCSI,
 396     .max_cpus = 4,
 397 };
 398
 399 static QEMUMachine midway_machine = {
 400     .name = "midway",
 401     .desc = "Calxeda Midway (ECX-2000)",
 402     .init = midway_init,
 403     .block_default_type = IF_SCSI,
 404     .max_cpus = 4,
 405 };
 406
 407 static void calxeda_machines_init(void)
 408 {
 409     qemu_register_machine(&highbank_machine);
 410     qemu_register_machine(&midway_machine);
 411 }
 412
 413 machine_init(calxeda_machines_init);