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ppc: Improve emulation of THRM registers
[qemu/kevin.git] / target-ppc / translate_init.c
blobc847a3e56227a9404f6396b54afb6a75df15e635
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "disas/bfd.h"
23 #include "exec/gdbstub.h"
24 #include <sysemu/kvm.h>
25 #include "kvm_ppc.h"
26 #include "sysemu/arch_init.h"
27 #include "sysemu/cpus.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qapi/visitor.h"
33 #include "hw/qdev-properties.h"
34 #include "hw/ppc/ppc.h"
35
36 //#define PPC_DUMP_CPU
37 //#define PPC_DEBUG_SPR
38 //#define PPC_DUMP_SPR_ACCESSES
39 /* #define USE_APPLE_GDB */
40
41 /* Generic callbacks:
42 * do nothing but store/retrieve spr value
43 */
44 static void spr_load_dump_spr(int sprn)
45 {
46 #ifdef PPC_DUMP_SPR_ACCESSES
47 TCGv_i32 t0 = tcg_const_i32(sprn);
48 gen_helper_load_dump_spr(cpu_env, t0);
49 tcg_temp_free_i32(t0);
50 #endif
51 }
52
53 static void spr_read_generic (DisasContext *ctx, int gprn, int sprn)
54 {
55 gen_load_spr(cpu_gpr[gprn], sprn);
56 spr_load_dump_spr(sprn);
57 }
58
59 static void spr_store_dump_spr(int sprn)
60 {
61 #ifdef PPC_DUMP_SPR_ACCESSES
62 TCGv_i32 t0 = tcg_const_i32(sprn);
63 gen_helper_store_dump_spr(cpu_env, t0);
64 tcg_temp_free_i32(t0);
65 #endif
66 }
67
68 static void spr_write_generic (DisasContext *ctx, int sprn, int gprn)
69 {
70 gen_store_spr(sprn, cpu_gpr[gprn]);
71 spr_store_dump_spr(sprn);
72 }
73
74 #if !defined(CONFIG_USER_ONLY)
75 static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
76 {
77 #ifdef TARGET_PPC64
78 TCGv t0 = tcg_temp_new();
79 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
80 gen_store_spr(sprn, t0);
81 tcg_temp_free(t0);
82 spr_store_dump_spr(sprn);
83 #else
84 spr_write_generic(ctx, sprn, gprn);
85 #endif
86 }
87
88 static void spr_write_clear (DisasContext *ctx, int sprn, int gprn)
89 {
90 TCGv t0 = tcg_temp_new();
91 TCGv t1 = tcg_temp_new();
92 gen_load_spr(t0, sprn);
93 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
94 tcg_gen_and_tl(t0, t0, t1);
95 gen_store_spr(sprn, t0);
96 tcg_temp_free(t0);
97 tcg_temp_free(t1);
98 }
99
100 static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
101 {
102 }
103
104 #endif
105
106 /* SPR common to all PowerPC */
107 /* XER */
108 static void spr_read_xer (DisasContext *ctx, int gprn, int sprn)
109 {
110 gen_read_xer(cpu_gpr[gprn]);
111 }
112
113 static void spr_write_xer (DisasContext *ctx, int sprn, int gprn)
114 {
115 gen_write_xer(cpu_gpr[gprn]);
116 }
117
118 /* LR */
119 static void spr_read_lr (DisasContext *ctx, int gprn, int sprn)
120 {
121 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
122 }
123
124 static void spr_write_lr (DisasContext *ctx, int sprn, int gprn)
125 {
126 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
127 }
128
129 /* CFAR */
130 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
131 static void spr_read_cfar (DisasContext *ctx, int gprn, int sprn)
132 {
133 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
134 }
135
136 static void spr_write_cfar (DisasContext *ctx, int sprn, int gprn)
137 {
138 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
139 }
140 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
141
142 /* CTR */
143 static void spr_read_ctr (DisasContext *ctx, int gprn, int sprn)
144 {
145 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
146 }
147
148 static void spr_write_ctr (DisasContext *ctx, int sprn, int gprn)
149 {
150 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
151 }
152
153 /* User read access to SPR */
154 /* USPRx */
155 /* UMMCRx */
156 /* UPMCx */
157 /* USIA */
158 /* UDECR */
159 static void spr_read_ureg (DisasContext *ctx, int gprn, int sprn)
160 {
161 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
162 }
163
164 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
165 static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
166 {
167 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
168 }
169 #endif
170
171 /* SPR common to all non-embedded PowerPC */
172 /* DECR */
173 #if !defined(CONFIG_USER_ONLY)
174 static void spr_read_decr (DisasContext *ctx, int gprn, int sprn)
175 {
176 if (ctx->tb->cflags & CF_USE_ICOUNT) {
177 gen_io_start();
178 }
179 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
180 if (ctx->tb->cflags & CF_USE_ICOUNT) {
181 gen_io_end();
182 gen_stop_exception(ctx);
183 }
184 }
185
186 static void spr_write_decr (DisasContext *ctx, int sprn, int gprn)
187 {
188 if (ctx->tb->cflags & CF_USE_ICOUNT) {
189 gen_io_start();
190 }
191 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
192 if (ctx->tb->cflags & CF_USE_ICOUNT) {
193 gen_io_end();
194 gen_stop_exception(ctx);
195 }
196 }
197 #endif
198
199 /* SPR common to all non-embedded PowerPC, except 601 */
200 /* Time base */
201 static void spr_read_tbl (DisasContext *ctx, int gprn, int sprn)
202 {
203 if (ctx->tb->cflags & CF_USE_ICOUNT) {
204 gen_io_start();
205 }
206 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
207 if (ctx->tb->cflags & CF_USE_ICOUNT) {
208 gen_io_end();
209 gen_stop_exception(ctx);
210 }
211 }
212
213 static void spr_read_tbu (DisasContext *ctx, int gprn, int sprn)
214 {
215 if (ctx->tb->cflags & CF_USE_ICOUNT) {
216 gen_io_start();
217 }
218 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
219 if (ctx->tb->cflags & CF_USE_ICOUNT) {
220 gen_io_end();
221 gen_stop_exception(ctx);
222 }
223 }
224
225 __attribute__ (( unused ))
226 static void spr_read_atbl (DisasContext *ctx, int gprn, int sprn)
227 {
228 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
229 }
230
231 __attribute__ (( unused ))
232 static void spr_read_atbu (DisasContext *ctx, int gprn, int sprn)
233 {
234 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
235 }
236
237 #if !defined(CONFIG_USER_ONLY)
238 static void spr_write_tbl (DisasContext *ctx, int sprn, int gprn)
239 {
240 if (ctx->tb->cflags & CF_USE_ICOUNT) {
241 gen_io_start();
242 }
243 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
244 if (ctx->tb->cflags & CF_USE_ICOUNT) {
245 gen_io_end();
246 gen_stop_exception(ctx);
247 }
248 }
249
250 static void spr_write_tbu (DisasContext *ctx, int sprn, int gprn)
251 {
252 if (ctx->tb->cflags & CF_USE_ICOUNT) {
253 gen_io_start();
254 }
255 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
256 if (ctx->tb->cflags & CF_USE_ICOUNT) {
257 gen_io_end();
258 gen_stop_exception(ctx);
259 }
260 }
261
262 __attribute__ (( unused ))
263 static void spr_write_atbl (DisasContext *ctx, int sprn, int gprn)
264 {
265 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
266 }
267
268 __attribute__ (( unused ))
269 static void spr_write_atbu (DisasContext *ctx, int sprn, int gprn)
270 {
271 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
272 }
273
274 #if defined(TARGET_PPC64)
275 __attribute__ (( unused ))
276 static void spr_read_purr (DisasContext *ctx, int gprn, int sprn)
277 {
278 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
279 }
280 #endif
281 #endif
282
283 #if !defined(CONFIG_USER_ONLY)
284 /* IBAT0U...IBAT0U */
285 /* IBAT0L...IBAT7L */
286 static void spr_read_ibat (DisasContext *ctx, int gprn, int sprn)
287 {
288 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
289 }
290
291 static void spr_read_ibat_h (DisasContext *ctx, int gprn, int sprn)
292 {
293 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
294 }
295
296 static void spr_write_ibatu (DisasContext *ctx, int sprn, int gprn)
297 {
298 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
299 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
300 tcg_temp_free_i32(t0);
301 }
302
303 static void spr_write_ibatu_h (DisasContext *ctx, int sprn, int gprn)
304 {
305 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
306 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
307 tcg_temp_free_i32(t0);
308 }
309
310 static void spr_write_ibatl (DisasContext *ctx, int sprn, int gprn)
311 {
312 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
313 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
314 tcg_temp_free_i32(t0);
315 }
316
317 static void spr_write_ibatl_h (DisasContext *ctx, int sprn, int gprn)
318 {
319 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
320 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
321 tcg_temp_free_i32(t0);
322 }
323
324 /* DBAT0U...DBAT7U */
325 /* DBAT0L...DBAT7L */
326 static void spr_read_dbat (DisasContext *ctx, int gprn, int sprn)
327 {
328 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
329 }
330
331 static void spr_read_dbat_h (DisasContext *ctx, int gprn, int sprn)
332 {
333 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
334 }
335
336 static void spr_write_dbatu (DisasContext *ctx, int sprn, int gprn)
337 {
338 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
339 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
340 tcg_temp_free_i32(t0);
341 }
342
343 static void spr_write_dbatu_h (DisasContext *ctx, int sprn, int gprn)
344 {
345 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
346 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
347 tcg_temp_free_i32(t0);
348 }
349
350 static void spr_write_dbatl (DisasContext *ctx, int sprn, int gprn)
351 {
352 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
353 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
354 tcg_temp_free_i32(t0);
355 }
356
357 static void spr_write_dbatl_h (DisasContext *ctx, int sprn, int gprn)
358 {
359 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
360 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
361 tcg_temp_free_i32(t0);
362 }
363
364 /* SDR1 */
365 static void spr_write_sdr1 (DisasContext *ctx, int sprn, int gprn)
366 {
367 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
368 }
369
370 /* 64 bits PowerPC specific SPRs */
371 #if defined(TARGET_PPC64)
372 static void spr_read_hior (DisasContext *ctx, int gprn, int sprn)
373 {
374 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
375 }
376
377 static void spr_write_hior (DisasContext *ctx, int sprn, int gprn)
378 {
379 TCGv t0 = tcg_temp_new();
380 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
381 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
382 tcg_temp_free(t0);
383 }
384 #endif
385 #endif
386
387 /* PowerPC 601 specific registers */
388 /* RTC */
389 static void spr_read_601_rtcl (DisasContext *ctx, int gprn, int sprn)
390 {
391 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
392 }
393
394 static void spr_read_601_rtcu (DisasContext *ctx, int gprn, int sprn)
395 {
396 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
397 }
398
399 #if !defined(CONFIG_USER_ONLY)
400 static void spr_write_601_rtcu (DisasContext *ctx, int sprn, int gprn)
401 {
402 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
403 }
404
405 static void spr_write_601_rtcl (DisasContext *ctx, int sprn, int gprn)
406 {
407 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
408 }
409
410 static void spr_write_hid0_601 (DisasContext *ctx, int sprn, int gprn)
411 {
412 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
413 /* Must stop the translation as endianness may have changed */
414 gen_stop_exception(ctx);
415 }
416 #endif
417
418 /* Unified bats */
419 #if !defined(CONFIG_USER_ONLY)
420 static void spr_read_601_ubat (DisasContext *ctx, int gprn, int sprn)
421 {
422 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
423 }
424
425 static void spr_write_601_ubatu (DisasContext *ctx, int sprn, int gprn)
426 {
427 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
428 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
429 tcg_temp_free_i32(t0);
430 }
431
432 static void spr_write_601_ubatl (DisasContext *ctx, int sprn, int gprn)
433 {
434 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
435 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
436 tcg_temp_free_i32(t0);
437 }
438 #endif
439
440 /* PowerPC 40x specific registers */
441 #if !defined(CONFIG_USER_ONLY)
442 static void spr_read_40x_pit (DisasContext *ctx, int gprn, int sprn)
443 {
444 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
445 }
446
447 static void spr_write_40x_pit (DisasContext *ctx, int sprn, int gprn)
448 {
449 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
450 }
451
452 static void spr_write_40x_dbcr0 (DisasContext *ctx, int sprn, int gprn)
453 {
454 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
455 /* We must stop translation as we may have rebooted */
456 gen_stop_exception(ctx);
457 }
458
459 static void spr_write_40x_sler (DisasContext *ctx, int sprn, int gprn)
460 {
461 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
462 }
463
464 static void spr_write_booke_tcr (DisasContext *ctx, int sprn, int gprn)
465 {
466 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
467 }
468
469 static void spr_write_booke_tsr (DisasContext *ctx, int sprn, int gprn)
470 {
471 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
472 }
473 #endif
474
475 /* PowerPC 403 specific registers */
476 /* PBL1 / PBU1 / PBL2 / PBU2 */
477 #if !defined(CONFIG_USER_ONLY)
478 static void spr_read_403_pbr (DisasContext *ctx, int gprn, int sprn)
479 {
480 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
481 }
482
483 static void spr_write_403_pbr (DisasContext *ctx, int sprn, int gprn)
484 {
485 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
486 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
487 tcg_temp_free_i32(t0);
488 }
489
490 static void spr_write_pir (DisasContext *ctx, int sprn, int gprn)
491 {
492 TCGv t0 = tcg_temp_new();
493 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
494 gen_store_spr(SPR_PIR, t0);
495 tcg_temp_free(t0);
496 }
497 #endif
498
499 /* SPE specific registers */
500 static void spr_read_spefscr (DisasContext *ctx, int gprn, int sprn)
501 {
502 TCGv_i32 t0 = tcg_temp_new_i32();
503 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
504 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
505 tcg_temp_free_i32(t0);
506 }
507
508 static void spr_write_spefscr (DisasContext *ctx, int sprn, int gprn)
509 {
510 TCGv_i32 t0 = tcg_temp_new_i32();
511 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
512 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
513 tcg_temp_free_i32(t0);
514 }
515
516 #if !defined(CONFIG_USER_ONLY)
517 /* Callback used to write the exception vector base */
518 static void spr_write_excp_prefix (DisasContext *ctx, int sprn, int gprn)
519 {
520 TCGv t0 = tcg_temp_new();
521 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
522 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
523 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
524 gen_store_spr(sprn, t0);
525 tcg_temp_free(t0);
526 }
527
528 static void spr_write_excp_vector (DisasContext *ctx, int sprn, int gprn)
529 {
530 int sprn_offs;
531
532 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
533 sprn_offs = sprn - SPR_BOOKE_IVOR0;
534 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
535 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
536 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
537 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
538 } else {
539 printf("Trying to write an unknown exception vector %d %03x\n",
540 sprn, sprn);
541 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
542 return;
543 }
544
545 TCGv t0 = tcg_temp_new();
546 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
547 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
548 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
549 gen_store_spr(sprn, t0);
550 tcg_temp_free(t0);
551 }
552 #endif
553
554 static inline void vscr_init (CPUPPCState *env, uint32_t val)
555 {
556 env->vscr = val;
557 /* Altivec always uses round-to-nearest */
558 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
559 set_flush_to_zero(vscr_nj, &env->vec_status);
560 }
561
562 #ifdef CONFIG_USER_ONLY
563 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
564 oea_read, oea_write, one_reg_id, initial_value) \
565 _spr_register(env, num, name, uea_read, uea_write, initial_value)
566 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
567 oea_read, oea_write, hea_read, hea_write, \
568 one_reg_id, initial_value) \
569 _spr_register(env, num, name, uea_read, uea_write, initial_value)
570 #else
571 #if !defined(CONFIG_KVM)
572 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
573 oea_read, oea_write, one_reg_id, initial_value) \
574 _spr_register(env, num, name, uea_read, uea_write, \
575 oea_read, oea_write, oea_read, oea_write, initial_value)
576 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
577 oea_read, oea_write, hea_read, hea_write, \
578 one_reg_id, initial_value) \
579 _spr_register(env, num, name, uea_read, uea_write, \
580 oea_read, oea_write, hea_read, hea_write, initial_value)
581 #else
582 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
583 oea_read, oea_write, one_reg_id, initial_value) \
584 _spr_register(env, num, name, uea_read, uea_write, \
585 oea_read, oea_write, oea_read, oea_write, \
586 one_reg_id, initial_value)
587 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
588 oea_read, oea_write, hea_read, hea_write, \
589 one_reg_id, initial_value) \
590 _spr_register(env, num, name, uea_read, uea_write, \
591 oea_read, oea_write, hea_read, hea_write, \
592 one_reg_id, initial_value)
593 #endif
594 #endif
595
596 #define spr_register(env, num, name, uea_read, uea_write, \
597 oea_read, oea_write, initial_value) \
598 spr_register_kvm(env, num, name, uea_read, uea_write, \
599 oea_read, oea_write, 0, initial_value)
600
601 #define spr_register_hv(env, num, name, uea_read, uea_write, \
602 oea_read, oea_write, hea_read, hea_write, \
603 initial_value) \
604 spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
605 oea_read, oea_write, hea_read, hea_write, \
606 0, initial_value)
607
608 static inline void _spr_register(CPUPPCState *env, int num,
609 const char *name,
610 void (*uea_read)(DisasContext *ctx, int gprn, int sprn),
611 void (*uea_write)(DisasContext *ctx, int sprn, int gprn),
612 #if !defined(CONFIG_USER_ONLY)
613
614 void (*oea_read)(DisasContext *ctx, int gprn, int sprn),
615 void (*oea_write)(DisasContext *ctx, int sprn, int gprn),
616 void (*hea_read)(DisasContext *opaque, int gprn, int sprn),
617 void (*hea_write)(DisasContext *opaque, int sprn, int gprn),
618 #endif
619 #if defined(CONFIG_KVM)
620 uint64_t one_reg_id,
621 #endif
622 target_ulong initial_value)
623 {
624 ppc_spr_t *spr;
625
626 spr = &env->spr_cb[num];
627 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
628 #if !defined(CONFIG_USER_ONLY)
629 spr->oea_read != NULL || spr->oea_write != NULL ||
630 #endif
631 spr->uea_read != NULL || spr->uea_write != NULL) {
632 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
633 exit(1);
634 }
635 #if defined(PPC_DEBUG_SPR)
636 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
637 name, initial_value);
638 #endif
639 spr->name = name;
640 spr->uea_read = uea_read;
641 spr->uea_write = uea_write;
642 #if !defined(CONFIG_USER_ONLY)
643 spr->oea_read = oea_read;
644 spr->oea_write = oea_write;
645 spr->hea_read = hea_read;
646 spr->hea_write = hea_write;
647 #endif
648 #if defined(CONFIG_KVM)
649 spr->one_reg_id = one_reg_id,
650 #endif
651 env->spr[num] = spr->default_value = initial_value;
652 }
653
654 /* Generic PowerPC SPRs */
655 static void gen_spr_generic (CPUPPCState *env)
656 {
657 /* Integer processing */
658 spr_register(env, SPR_XER, "XER",
659 &spr_read_xer, &spr_write_xer,
660 &spr_read_xer, &spr_write_xer,
661 0x00000000);
662 /* Branch contol */
663 spr_register(env, SPR_LR, "LR",
664 &spr_read_lr, &spr_write_lr,
665 &spr_read_lr, &spr_write_lr,
666 0x00000000);
667 spr_register(env, SPR_CTR, "CTR",
668 &spr_read_ctr, &spr_write_ctr,
669 &spr_read_ctr, &spr_write_ctr,
670 0x00000000);
671 /* Interrupt processing */
672 spr_register(env, SPR_SRR0, "SRR0",
673 SPR_NOACCESS, SPR_NOACCESS,
674 &spr_read_generic, &spr_write_generic,
675 0x00000000);
676 spr_register(env, SPR_SRR1, "SRR1",
677 SPR_NOACCESS, SPR_NOACCESS,
678 &spr_read_generic, &spr_write_generic,
679 0x00000000);
680 /* Processor control */
681 spr_register(env, SPR_SPRG0, "SPRG0",
682 SPR_NOACCESS, SPR_NOACCESS,
683 &spr_read_generic, &spr_write_generic,
684 0x00000000);
685 spr_register(env, SPR_SPRG1, "SPRG1",
686 SPR_NOACCESS, SPR_NOACCESS,
687 &spr_read_generic, &spr_write_generic,
688 0x00000000);
689 spr_register(env, SPR_SPRG2, "SPRG2",
690 SPR_NOACCESS, SPR_NOACCESS,
691 &spr_read_generic, &spr_write_generic,
692 0x00000000);
693 spr_register(env, SPR_SPRG3, "SPRG3",
694 SPR_NOACCESS, SPR_NOACCESS,
695 &spr_read_generic, &spr_write_generic,
696 0x00000000);
697 }
698
699 /* SPR common to all non-embedded PowerPC, including 601 */
700 static void gen_spr_ne_601 (CPUPPCState *env)
701 {
702 /* Exception processing */
703 spr_register_kvm(env, SPR_DSISR, "DSISR",
704 SPR_NOACCESS, SPR_NOACCESS,
705 &spr_read_generic, &spr_write_generic,
706 KVM_REG_PPC_DSISR, 0x00000000);
707 spr_register_kvm(env, SPR_DAR, "DAR",
708 SPR_NOACCESS, SPR_NOACCESS,
709 &spr_read_generic, &spr_write_generic,
710 KVM_REG_PPC_DAR, 0x00000000);
711 /* Timer */
712 spr_register(env, SPR_DECR, "DECR",
713 SPR_NOACCESS, SPR_NOACCESS,
714 &spr_read_decr, &spr_write_decr,
715 0x00000000);
716 /* Memory management */
717 spr_register(env, SPR_SDR1, "SDR1",
718 SPR_NOACCESS, SPR_NOACCESS,
719 &spr_read_generic, &spr_write_sdr1,
720 0x00000000);
721 }
722
723 /* BATs 0-3 */
724 static void gen_low_BATs (CPUPPCState *env)
725 {
726 #if !defined(CONFIG_USER_ONLY)
727 spr_register(env, SPR_IBAT0U, "IBAT0U",
728 SPR_NOACCESS, SPR_NOACCESS,
729 &spr_read_ibat, &spr_write_ibatu,
730 0x00000000);
731 spr_register(env, SPR_IBAT0L, "IBAT0L",
732 SPR_NOACCESS, SPR_NOACCESS,
733 &spr_read_ibat, &spr_write_ibatl,
734 0x00000000);
735 spr_register(env, SPR_IBAT1U, "IBAT1U",
736 SPR_NOACCESS, SPR_NOACCESS,
737 &spr_read_ibat, &spr_write_ibatu,
738 0x00000000);
739 spr_register(env, SPR_IBAT1L, "IBAT1L",
740 SPR_NOACCESS, SPR_NOACCESS,
741 &spr_read_ibat, &spr_write_ibatl,
742 0x00000000);
743 spr_register(env, SPR_IBAT2U, "IBAT2U",
744 SPR_NOACCESS, SPR_NOACCESS,
745 &spr_read_ibat, &spr_write_ibatu,
746 0x00000000);
747 spr_register(env, SPR_IBAT2L, "IBAT2L",
748 SPR_NOACCESS, SPR_NOACCESS,
749 &spr_read_ibat, &spr_write_ibatl,
750 0x00000000);
751 spr_register(env, SPR_IBAT3U, "IBAT3U",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_ibat, &spr_write_ibatu,
754 0x00000000);
755 spr_register(env, SPR_IBAT3L, "IBAT3L",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_ibat, &spr_write_ibatl,
758 0x00000000);
759 spr_register(env, SPR_DBAT0U, "DBAT0U",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_dbat, &spr_write_dbatu,
762 0x00000000);
763 spr_register(env, SPR_DBAT0L, "DBAT0L",
764 SPR_NOACCESS, SPR_NOACCESS,
765 &spr_read_dbat, &spr_write_dbatl,
766 0x00000000);
767 spr_register(env, SPR_DBAT1U, "DBAT1U",
768 SPR_NOACCESS, SPR_NOACCESS,
769 &spr_read_dbat, &spr_write_dbatu,
770 0x00000000);
771 spr_register(env, SPR_DBAT1L, "DBAT1L",
772 SPR_NOACCESS, SPR_NOACCESS,
773 &spr_read_dbat, &spr_write_dbatl,
774 0x00000000);
775 spr_register(env, SPR_DBAT2U, "DBAT2U",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_dbat, &spr_write_dbatu,
778 0x00000000);
779 spr_register(env, SPR_DBAT2L, "DBAT2L",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_dbat, &spr_write_dbatl,
782 0x00000000);
783 spr_register(env, SPR_DBAT3U, "DBAT3U",
784 SPR_NOACCESS, SPR_NOACCESS,
785 &spr_read_dbat, &spr_write_dbatu,
786 0x00000000);
787 spr_register(env, SPR_DBAT3L, "DBAT3L",
788 SPR_NOACCESS, SPR_NOACCESS,
789 &spr_read_dbat, &spr_write_dbatl,
790 0x00000000);
791 env->nb_BATs += 4;
792 #endif
793 }
794
795 /* BATs 4-7 */
796 static void gen_high_BATs (CPUPPCState *env)
797 {
798 #if !defined(CONFIG_USER_ONLY)
799 spr_register(env, SPR_IBAT4U, "IBAT4U",
800 SPR_NOACCESS, SPR_NOACCESS,
801 &spr_read_ibat_h, &spr_write_ibatu_h,
802 0x00000000);
803 spr_register(env, SPR_IBAT4L, "IBAT4L",
804 SPR_NOACCESS, SPR_NOACCESS,
805 &spr_read_ibat_h, &spr_write_ibatl_h,
806 0x00000000);
807 spr_register(env, SPR_IBAT5U, "IBAT5U",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_ibat_h, &spr_write_ibatu_h,
810 0x00000000);
811 spr_register(env, SPR_IBAT5L, "IBAT5L",
812 SPR_NOACCESS, SPR_NOACCESS,
813 &spr_read_ibat_h, &spr_write_ibatl_h,
814 0x00000000);
815 spr_register(env, SPR_IBAT6U, "IBAT6U",
816 SPR_NOACCESS, SPR_NOACCESS,
817 &spr_read_ibat_h, &spr_write_ibatu_h,
818 0x00000000);
819 spr_register(env, SPR_IBAT6L, "IBAT6L",
820 SPR_NOACCESS, SPR_NOACCESS,
821 &spr_read_ibat_h, &spr_write_ibatl_h,
822 0x00000000);
823 spr_register(env, SPR_IBAT7U, "IBAT7U",
824 SPR_NOACCESS, SPR_NOACCESS,
825 &spr_read_ibat_h, &spr_write_ibatu_h,
826 0x00000000);
827 spr_register(env, SPR_IBAT7L, "IBAT7L",
828 SPR_NOACCESS, SPR_NOACCESS,
829 &spr_read_ibat_h, &spr_write_ibatl_h,
830 0x00000000);
831 spr_register(env, SPR_DBAT4U, "DBAT4U",
832 SPR_NOACCESS, SPR_NOACCESS,
833 &spr_read_dbat_h, &spr_write_dbatu_h,
834 0x00000000);
835 spr_register(env, SPR_DBAT4L, "DBAT4L",
836 SPR_NOACCESS, SPR_NOACCESS,
837 &spr_read_dbat_h, &spr_write_dbatl_h,
838 0x00000000);
839 spr_register(env, SPR_DBAT5U, "DBAT5U",
840 SPR_NOACCESS, SPR_NOACCESS,
841 &spr_read_dbat_h, &spr_write_dbatu_h,
842 0x00000000);
843 spr_register(env, SPR_DBAT5L, "DBAT5L",
844 SPR_NOACCESS, SPR_NOACCESS,
845 &spr_read_dbat_h, &spr_write_dbatl_h,
846 0x00000000);
847 spr_register(env, SPR_DBAT6U, "DBAT6U",
848 SPR_NOACCESS, SPR_NOACCESS,
849 &spr_read_dbat_h, &spr_write_dbatu_h,
850 0x00000000);
851 spr_register(env, SPR_DBAT6L, "DBAT6L",
852 SPR_NOACCESS, SPR_NOACCESS,
853 &spr_read_dbat_h, &spr_write_dbatl_h,
854 0x00000000);
855 spr_register(env, SPR_DBAT7U, "DBAT7U",
856 SPR_NOACCESS, SPR_NOACCESS,
857 &spr_read_dbat_h, &spr_write_dbatu_h,
858 0x00000000);
859 spr_register(env, SPR_DBAT7L, "DBAT7L",
860 SPR_NOACCESS, SPR_NOACCESS,
861 &spr_read_dbat_h, &spr_write_dbatl_h,
862 0x00000000);
863 env->nb_BATs += 4;
864 #endif
865 }
866
867 /* Generic PowerPC time base */
868 static void gen_tbl (CPUPPCState *env)
869 {
870 spr_register(env, SPR_VTBL, "TBL",
871 &spr_read_tbl, SPR_NOACCESS,
872 &spr_read_tbl, SPR_NOACCESS,
873 0x00000000);
874 spr_register(env, SPR_TBL, "TBL",
875 &spr_read_tbl, SPR_NOACCESS,
876 &spr_read_tbl, &spr_write_tbl,
877 0x00000000);
878 spr_register(env, SPR_VTBU, "TBU",
879 &spr_read_tbu, SPR_NOACCESS,
880 &spr_read_tbu, SPR_NOACCESS,
881 0x00000000);
882 spr_register(env, SPR_TBU, "TBU",
883 &spr_read_tbu, SPR_NOACCESS,
884 &spr_read_tbu, &spr_write_tbu,
885 0x00000000);
886 }
887
888 /* Softare table search registers */
889 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
890 {
891 #if !defined(CONFIG_USER_ONLY)
892 env->nb_tlb = nb_tlbs;
893 env->nb_ways = nb_ways;
894 env->id_tlbs = 1;
895 env->tlb_type = TLB_6XX;
896 spr_register(env, SPR_DMISS, "DMISS",
897 SPR_NOACCESS, SPR_NOACCESS,
898 &spr_read_generic, SPR_NOACCESS,
899 0x00000000);
900 spr_register(env, SPR_DCMP, "DCMP",
901 SPR_NOACCESS, SPR_NOACCESS,
902 &spr_read_generic, SPR_NOACCESS,
903 0x00000000);
904 spr_register(env, SPR_HASH1, "HASH1",
905 SPR_NOACCESS, SPR_NOACCESS,
906 &spr_read_generic, SPR_NOACCESS,
907 0x00000000);
908 spr_register(env, SPR_HASH2, "HASH2",
909 SPR_NOACCESS, SPR_NOACCESS,
910 &spr_read_generic, SPR_NOACCESS,
911 0x00000000);
912 spr_register(env, SPR_IMISS, "IMISS",
913 SPR_NOACCESS, SPR_NOACCESS,
914 &spr_read_generic, SPR_NOACCESS,
915 0x00000000);
916 spr_register(env, SPR_ICMP, "ICMP",
917 SPR_NOACCESS, SPR_NOACCESS,
918 &spr_read_generic, SPR_NOACCESS,
919 0x00000000);
920 spr_register(env, SPR_RPA, "RPA",
921 SPR_NOACCESS, SPR_NOACCESS,
922 &spr_read_generic, &spr_write_generic,
923 0x00000000);
924 #endif
925 }
926
927 /* SPR common to MPC755 and G2 */
928 static void gen_spr_G2_755 (CPUPPCState *env)
929 {
930 /* SGPRs */
931 spr_register(env, SPR_SPRG4, "SPRG4",
932 SPR_NOACCESS, SPR_NOACCESS,
933 &spr_read_generic, &spr_write_generic,
934 0x00000000);
935 spr_register(env, SPR_SPRG5, "SPRG5",
936 SPR_NOACCESS, SPR_NOACCESS,
937 &spr_read_generic, &spr_write_generic,
938 0x00000000);
939 spr_register(env, SPR_SPRG6, "SPRG6",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 0x00000000);
943 spr_register(env, SPR_SPRG7, "SPRG7",
944 SPR_NOACCESS, SPR_NOACCESS,
945 &spr_read_generic, &spr_write_generic,
946 0x00000000);
947 }
948
949 /* SPR common to all 7xx PowerPC implementations */
950 static void gen_spr_7xx (CPUPPCState *env)
951 {
952 /* Breakpoints */
953 /* XXX : not implemented */
954 spr_register_kvm(env, SPR_DABR, "DABR",
955 SPR_NOACCESS, SPR_NOACCESS,
956 &spr_read_generic, &spr_write_generic,
957 KVM_REG_PPC_DABR, 0x00000000);
958 /* XXX : not implemented */
959 spr_register(env, SPR_IABR, "IABR",
960 SPR_NOACCESS, SPR_NOACCESS,
961 &spr_read_generic, &spr_write_generic,
962 0x00000000);
963 /* Cache management */
964 /* XXX : not implemented */
965 spr_register(env, SPR_ICTC, "ICTC",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, &spr_write_generic,
968 0x00000000);
969 /* Performance monitors */
970 /* XXX : not implemented */
971 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
972 SPR_NOACCESS, SPR_NOACCESS,
973 &spr_read_generic, &spr_write_generic,
974 0x00000000);
975 /* XXX : not implemented */
976 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
977 SPR_NOACCESS, SPR_NOACCESS,
978 &spr_read_generic, &spr_write_generic,
979 0x00000000);
980 /* XXX : not implemented */
981 spr_register(env, SPR_7XX_PMC1, "PMC1",
982 SPR_NOACCESS, SPR_NOACCESS,
983 &spr_read_generic, &spr_write_generic,
984 0x00000000);
985 /* XXX : not implemented */
986 spr_register(env, SPR_7XX_PMC2, "PMC2",
987 SPR_NOACCESS, SPR_NOACCESS,
988 &spr_read_generic, &spr_write_generic,
989 0x00000000);
990 /* XXX : not implemented */
991 spr_register(env, SPR_7XX_PMC3, "PMC3",
992 SPR_NOACCESS, SPR_NOACCESS,
993 &spr_read_generic, &spr_write_generic,
994 0x00000000);
995 /* XXX : not implemented */
996 spr_register(env, SPR_7XX_PMC4, "PMC4",
997 SPR_NOACCESS, SPR_NOACCESS,
998 &spr_read_generic, &spr_write_generic,
999 0x00000000);
1000 /* XXX : not implemented */
1001 spr_register(env, SPR_7XX_SIAR, "SIAR",
1002 SPR_NOACCESS, SPR_NOACCESS,
1003 &spr_read_generic, SPR_NOACCESS,
1004 0x00000000);
1005 /* XXX : not implemented */
1006 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
1007 &spr_read_ureg, SPR_NOACCESS,
1008 &spr_read_ureg, SPR_NOACCESS,
1009 0x00000000);
1010 /* XXX : not implemented */
1011 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
1012 &spr_read_ureg, SPR_NOACCESS,
1013 &spr_read_ureg, SPR_NOACCESS,
1014 0x00000000);
1015 /* XXX : not implemented */
1016 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
1017 &spr_read_ureg, SPR_NOACCESS,
1018 &spr_read_ureg, SPR_NOACCESS,
1019 0x00000000);
1020 /* XXX : not implemented */
1021 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
1022 &spr_read_ureg, SPR_NOACCESS,
1023 &spr_read_ureg, SPR_NOACCESS,
1024 0x00000000);
1025 /* XXX : not implemented */
1026 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
1027 &spr_read_ureg, SPR_NOACCESS,
1028 &spr_read_ureg, SPR_NOACCESS,
1029 0x00000000);
1030 /* XXX : not implemented */
1031 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
1032 &spr_read_ureg, SPR_NOACCESS,
1033 &spr_read_ureg, SPR_NOACCESS,
1034 0x00000000);
1035 /* XXX : not implemented */
1036 spr_register(env, SPR_7XX_USIAR, "USIAR",
1037 &spr_read_ureg, SPR_NOACCESS,
1038 &spr_read_ureg, SPR_NOACCESS,
1039 0x00000000);
1040 /* External access control */
1041 /* XXX : not implemented */
1042 spr_register(env, SPR_EAR, "EAR",
1043 SPR_NOACCESS, SPR_NOACCESS,
1044 &spr_read_generic, &spr_write_generic,
1045 0x00000000);
1046 }
1047
1048 #ifdef TARGET_PPC64
1049 #ifndef CONFIG_USER_ONLY
1050 static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
1051 {
1052 TCGv t0 = tcg_temp_new();
1053 TCGv t1 = tcg_temp_new();
1054 TCGv t2 = tcg_temp_new();
1055
1056 /* Note, the HV=1 PR=0 case is handled earlier by simply using
1057 * spr_write_generic for HV mode in the SPR table
1058 */
1059
1060 /* Build insertion mask into t1 based on context */
1061 if (ctx->pr) {
1062 gen_load_spr(t1, SPR_UAMOR);
1063 } else {
1064 gen_load_spr(t1, SPR_AMOR);
1065 }
1066
1067 /* Mask new bits into t2 */
1068 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1069
1070 /* Load AMR and clear new bits in t0 */
1071 gen_load_spr(t0, SPR_AMR);
1072 tcg_gen_andc_tl(t0, t0, t1);
1073
1074 /* Or'in new bits and write it out */
1075 tcg_gen_or_tl(t0, t0, t2);
1076 gen_store_spr(SPR_AMR, t0);
1077 spr_store_dump_spr(SPR_AMR);
1078
1079 tcg_temp_free(t0);
1080 tcg_temp_free(t1);
1081 tcg_temp_free(t2);
1082 }
1083
1084 static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
1085 {
1086 TCGv t0 = tcg_temp_new();
1087 TCGv t1 = tcg_temp_new();
1088 TCGv t2 = tcg_temp_new();
1089
1090 /* Note, the HV=1 case is handled earlier by simply using
1091 * spr_write_generic for HV mode in the SPR table
1092 */
1093
1094 /* Build insertion mask into t1 based on context */
1095 gen_load_spr(t1, SPR_AMOR);
1096
1097 /* Mask new bits into t2 */
1098 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1099
1100 /* Load AMR and clear new bits in t0 */
1101 gen_load_spr(t0, SPR_UAMOR);
1102 tcg_gen_andc_tl(t0, t0, t1);
1103
1104 /* Or'in new bits and write it out */
1105 tcg_gen_or_tl(t0, t0, t2);
1106 gen_store_spr(SPR_UAMOR, t0);
1107 spr_store_dump_spr(SPR_UAMOR);
1108
1109 tcg_temp_free(t0);
1110 tcg_temp_free(t1);
1111 tcg_temp_free(t2);
1112 }
1113
1114 static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1115 {
1116 TCGv t0 = tcg_temp_new();
1117 TCGv t1 = tcg_temp_new();
1118 TCGv t2 = tcg_temp_new();
1119
1120 /* Note, the HV=1 case is handled earlier by simply using
1121 * spr_write_generic for HV mode in the SPR table
1122 */
1123
1124 /* Build insertion mask into t1 based on context */
1125 gen_load_spr(t1, SPR_AMOR);
1126
1127 /* Mask new bits into t2 */
1128 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1129
1130 /* Load AMR and clear new bits in t0 */
1131 gen_load_spr(t0, SPR_IAMR);
1132 tcg_gen_andc_tl(t0, t0, t1);
1133
1134 /* Or'in new bits and write it out */
1135 tcg_gen_or_tl(t0, t0, t2);
1136 gen_store_spr(SPR_IAMR, t0);
1137 spr_store_dump_spr(SPR_IAMR);
1138
1139 tcg_temp_free(t0);
1140 tcg_temp_free(t1);
1141 tcg_temp_free(t2);
1142 }
1143 #endif /* CONFIG_USER_ONLY */
1144
1145 static void gen_spr_amr(CPUPPCState *env, bool has_iamr)
1146 {
1147 #ifndef CONFIG_USER_ONLY
1148 /* Virtual Page Class Key protection */
1149 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1150 * userspace accessible, 29 is privileged. So we only need to set
1151 * the kvm ONE_REG id on one of them, we use 29 */
1152 spr_register(env, SPR_UAMR, "UAMR",
1153 &spr_read_generic, &spr_write_amr,
1154 &spr_read_generic, &spr_write_amr,
1155 0);
1156 spr_register_kvm_hv(env, SPR_AMR, "AMR",
1157 SPR_NOACCESS, SPR_NOACCESS,
1158 &spr_read_generic, &spr_write_amr,
1159 &spr_read_generic, &spr_write_generic,
1160 KVM_REG_PPC_AMR, 0);
1161 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
1162 SPR_NOACCESS, SPR_NOACCESS,
1163 &spr_read_generic, &spr_write_uamor,
1164 &spr_read_generic, &spr_write_generic,
1165 KVM_REG_PPC_UAMOR, 0);
1166 spr_register_hv(env, SPR_AMOR, "AMOR",
1167 SPR_NOACCESS, SPR_NOACCESS,
1168 SPR_NOACCESS, SPR_NOACCESS,
1169 &spr_read_generic, &spr_write_generic,
1170 0);
1171 if (has_iamr) {
1172 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
1173 SPR_NOACCESS, SPR_NOACCESS,
1174 &spr_read_generic, &spr_write_iamr,
1175 &spr_read_generic, &spr_write_generic,
1176 KVM_REG_PPC_IAMR, 0);
1177 }
1178 #endif /* !CONFIG_USER_ONLY */
1179 }
1180 #endif /* TARGET_PPC64 */
1181
1182 #ifndef CONFIG_USER_ONLY
1183 static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
1184 {
1185 gen_helper_fixup_thrm(cpu_env);
1186 gen_load_spr(cpu_gpr[gprn], sprn);
1187 spr_load_dump_spr(sprn);
1188 }
1189 #endif /* !CONFIG_USER_ONLY */
1190
1191 static void gen_spr_thrm (CPUPPCState *env)
1192 {
1193 /* Thermal management */
1194 /* XXX : not implemented */
1195 spr_register(env, SPR_THRM1, "THRM1",
1196 SPR_NOACCESS, SPR_NOACCESS,
1197 &spr_read_thrm, &spr_write_generic,
1198 0x00000000);
1199 /* XXX : not implemented */
1200 spr_register(env, SPR_THRM2, "THRM2",
1201 SPR_NOACCESS, SPR_NOACCESS,
1202 &spr_read_thrm, &spr_write_generic,
1203 0x00000000);
1204 /* XXX : not implemented */
1205 spr_register(env, SPR_THRM3, "THRM3",
1206 SPR_NOACCESS, SPR_NOACCESS,
1207 &spr_read_thrm, &spr_write_generic,
1208 0x00000000);
1209 }
1210
1211 /* SPR specific to PowerPC 604 implementation */
1212 static void gen_spr_604 (CPUPPCState *env)
1213 {
1214 /* Processor identification */
1215 spr_register(env, SPR_PIR, "PIR",
1216 SPR_NOACCESS, SPR_NOACCESS,
1217 &spr_read_generic, &spr_write_pir,
1218 0x00000000);
1219 /* Breakpoints */
1220 /* XXX : not implemented */
1221 spr_register(env, SPR_IABR, "IABR",
1222 SPR_NOACCESS, SPR_NOACCESS,
1223 &spr_read_generic, &spr_write_generic,
1224 0x00000000);
1225 /* XXX : not implemented */
1226 spr_register_kvm(env, SPR_DABR, "DABR",
1227 SPR_NOACCESS, SPR_NOACCESS,
1228 &spr_read_generic, &spr_write_generic,
1229 KVM_REG_PPC_DABR, 0x00000000);
1230 /* Performance counters */
1231 /* XXX : not implemented */
1232 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 &spr_read_generic, &spr_write_generic,
1235 0x00000000);
1236 /* XXX : not implemented */
1237 spr_register(env, SPR_7XX_PMC1, "PMC1",
1238 SPR_NOACCESS, SPR_NOACCESS,
1239 &spr_read_generic, &spr_write_generic,
1240 0x00000000);
1241 /* XXX : not implemented */
1242 spr_register(env, SPR_7XX_PMC2, "PMC2",
1243 SPR_NOACCESS, SPR_NOACCESS,
1244 &spr_read_generic, &spr_write_generic,
1245 0x00000000);
1246 /* XXX : not implemented */
1247 spr_register(env, SPR_7XX_SIAR, "SIAR",
1248 SPR_NOACCESS, SPR_NOACCESS,
1249 &spr_read_generic, SPR_NOACCESS,
1250 0x00000000);
1251 /* XXX : not implemented */
1252 spr_register(env, SPR_SDA, "SDA",
1253 SPR_NOACCESS, SPR_NOACCESS,
1254 &spr_read_generic, SPR_NOACCESS,
1255 0x00000000);
1256 /* External access control */
1257 /* XXX : not implemented */
1258 spr_register(env, SPR_EAR, "EAR",
1259 SPR_NOACCESS, SPR_NOACCESS,
1260 &spr_read_generic, &spr_write_generic,
1261 0x00000000);
1262 }
1263
1264 /* SPR specific to PowerPC 603 implementation */
1265 static void gen_spr_603 (CPUPPCState *env)
1266 {
1267 /* External access control */
1268 /* XXX : not implemented */
1269 spr_register(env, SPR_EAR, "EAR",
1270 SPR_NOACCESS, SPR_NOACCESS,
1271 &spr_read_generic, &spr_write_generic,
1272 0x00000000);
1273 /* Breakpoints */
1274 /* XXX : not implemented */
1275 spr_register(env, SPR_IABR, "IABR",
1276 SPR_NOACCESS, SPR_NOACCESS,
1277 &spr_read_generic, &spr_write_generic,
1278 0x00000000);
1279
1280 }
1281
1282 /* SPR specific to PowerPC G2 implementation */
1283 static void gen_spr_G2 (CPUPPCState *env)
1284 {
1285 /* Memory base address */
1286 /* MBAR */
1287 /* XXX : not implemented */
1288 spr_register(env, SPR_MBAR, "MBAR",
1289 SPR_NOACCESS, SPR_NOACCESS,
1290 &spr_read_generic, &spr_write_generic,
1291 0x00000000);
1292 /* Exception processing */
1293 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1294 SPR_NOACCESS, SPR_NOACCESS,
1295 &spr_read_generic, &spr_write_generic,
1296 0x00000000);
1297 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1298 SPR_NOACCESS, SPR_NOACCESS,
1299 &spr_read_generic, &spr_write_generic,
1300 0x00000000);
1301 /* Breakpoints */
1302 /* XXX : not implemented */
1303 spr_register(env, SPR_DABR, "DABR",
1304 SPR_NOACCESS, SPR_NOACCESS,
1305 &spr_read_generic, &spr_write_generic,
1306 0x00000000);
1307 /* XXX : not implemented */
1308 spr_register(env, SPR_DABR2, "DABR2",
1309 SPR_NOACCESS, SPR_NOACCESS,
1310 &spr_read_generic, &spr_write_generic,
1311 0x00000000);
1312 /* XXX : not implemented */
1313 spr_register(env, SPR_IABR, "IABR",
1314 SPR_NOACCESS, SPR_NOACCESS,
1315 &spr_read_generic, &spr_write_generic,
1316 0x00000000);
1317 /* XXX : not implemented */
1318 spr_register(env, SPR_IABR2, "IABR2",
1319 SPR_NOACCESS, SPR_NOACCESS,
1320 &spr_read_generic, &spr_write_generic,
1321 0x00000000);
1322 /* XXX : not implemented */
1323 spr_register(env, SPR_IBCR, "IBCR",
1324 SPR_NOACCESS, SPR_NOACCESS,
1325 &spr_read_generic, &spr_write_generic,
1326 0x00000000);
1327 /* XXX : not implemented */
1328 spr_register(env, SPR_DBCR, "DBCR",
1329 SPR_NOACCESS, SPR_NOACCESS,
1330 &spr_read_generic, &spr_write_generic,
1331 0x00000000);
1332 }
1333
1334 /* SPR specific to PowerPC 602 implementation */
1335 static void gen_spr_602 (CPUPPCState *env)
1336 {
1337 /* ESA registers */
1338 /* XXX : not implemented */
1339 spr_register(env, SPR_SER, "SER",
1340 SPR_NOACCESS, SPR_NOACCESS,
1341 &spr_read_generic, &spr_write_generic,
1342 0x00000000);
1343 /* XXX : not implemented */
1344 spr_register(env, SPR_SEBR, "SEBR",
1345 SPR_NOACCESS, SPR_NOACCESS,
1346 &spr_read_generic, &spr_write_generic,
1347 0x00000000);
1348 /* XXX : not implemented */
1349 spr_register(env, SPR_ESASRR, "ESASRR",
1350 SPR_NOACCESS, SPR_NOACCESS,
1351 &spr_read_generic, &spr_write_generic,
1352 0x00000000);
1353 /* Floating point status */
1354 /* XXX : not implemented */
1355 spr_register(env, SPR_SP, "SP",
1356 SPR_NOACCESS, SPR_NOACCESS,
1357 &spr_read_generic, &spr_write_generic,
1358 0x00000000);
1359 /* XXX : not implemented */
1360 spr_register(env, SPR_LT, "LT",
1361 SPR_NOACCESS, SPR_NOACCESS,
1362 &spr_read_generic, &spr_write_generic,
1363 0x00000000);
1364 /* Watchdog timer */
1365 /* XXX : not implemented */
1366 spr_register(env, SPR_TCR, "TCR",
1367 SPR_NOACCESS, SPR_NOACCESS,
1368 &spr_read_generic, &spr_write_generic,
1369 0x00000000);
1370 /* Interrupt base */
1371 spr_register(env, SPR_IBR, "IBR",
1372 SPR_NOACCESS, SPR_NOACCESS,
1373 &spr_read_generic, &spr_write_generic,
1374 0x00000000);
1375 /* XXX : not implemented */
1376 spr_register(env, SPR_IABR, "IABR",
1377 SPR_NOACCESS, SPR_NOACCESS,
1378 &spr_read_generic, &spr_write_generic,
1379 0x00000000);
1380 }
1381
1382 /* SPR specific to PowerPC 601 implementation */
1383 static void gen_spr_601 (CPUPPCState *env)
1384 {
1385 /* Multiplication/division register */
1386 /* MQ */
1387 spr_register(env, SPR_MQ, "MQ",
1388 &spr_read_generic, &spr_write_generic,
1389 &spr_read_generic, &spr_write_generic,
1390 0x00000000);
1391 /* RTC registers */
1392 spr_register(env, SPR_601_RTCU, "RTCU",
1393 SPR_NOACCESS, SPR_NOACCESS,
1394 SPR_NOACCESS, &spr_write_601_rtcu,
1395 0x00000000);
1396 spr_register(env, SPR_601_VRTCU, "RTCU",
1397 &spr_read_601_rtcu, SPR_NOACCESS,
1398 &spr_read_601_rtcu, SPR_NOACCESS,
1399 0x00000000);
1400 spr_register(env, SPR_601_RTCL, "RTCL",
1401 SPR_NOACCESS, SPR_NOACCESS,
1402 SPR_NOACCESS, &spr_write_601_rtcl,
1403 0x00000000);
1404 spr_register(env, SPR_601_VRTCL, "RTCL",
1405 &spr_read_601_rtcl, SPR_NOACCESS,
1406 &spr_read_601_rtcl, SPR_NOACCESS,
1407 0x00000000);
1408 /* Timer */
1409 #if 0 /* ? */
1410 spr_register(env, SPR_601_UDECR, "UDECR",
1411 &spr_read_decr, SPR_NOACCESS,
1412 &spr_read_decr, SPR_NOACCESS,
1413 0x00000000);
1414 #endif
1415 /* External access control */
1416 /* XXX : not implemented */
1417 spr_register(env, SPR_EAR, "EAR",
1418 SPR_NOACCESS, SPR_NOACCESS,
1419 &spr_read_generic, &spr_write_generic,
1420 0x00000000);
1421 /* Memory management */
1422 #if !defined(CONFIG_USER_ONLY)
1423 spr_register(env, SPR_IBAT0U, "IBAT0U",
1424 SPR_NOACCESS, SPR_NOACCESS,
1425 &spr_read_601_ubat, &spr_write_601_ubatu,
1426 0x00000000);
1427 spr_register(env, SPR_IBAT0L, "IBAT0L",
1428 SPR_NOACCESS, SPR_NOACCESS,
1429 &spr_read_601_ubat, &spr_write_601_ubatl,
1430 0x00000000);
1431 spr_register(env, SPR_IBAT1U, "IBAT1U",
1432 SPR_NOACCESS, SPR_NOACCESS,
1433 &spr_read_601_ubat, &spr_write_601_ubatu,
1434 0x00000000);
1435 spr_register(env, SPR_IBAT1L, "IBAT1L",
1436 SPR_NOACCESS, SPR_NOACCESS,
1437 &spr_read_601_ubat, &spr_write_601_ubatl,
1438 0x00000000);
1439 spr_register(env, SPR_IBAT2U, "IBAT2U",
1440 SPR_NOACCESS, SPR_NOACCESS,
1441 &spr_read_601_ubat, &spr_write_601_ubatu,
1442 0x00000000);
1443 spr_register(env, SPR_IBAT2L, "IBAT2L",
1444 SPR_NOACCESS, SPR_NOACCESS,
1445 &spr_read_601_ubat, &spr_write_601_ubatl,
1446 0x00000000);
1447 spr_register(env, SPR_IBAT3U, "IBAT3U",
1448 SPR_NOACCESS, SPR_NOACCESS,
1449 &spr_read_601_ubat, &spr_write_601_ubatu,
1450 0x00000000);
1451 spr_register(env, SPR_IBAT3L, "IBAT3L",
1452 SPR_NOACCESS, SPR_NOACCESS,
1453 &spr_read_601_ubat, &spr_write_601_ubatl,
1454 0x00000000);
1455 env->nb_BATs = 4;
1456 #endif
1457 }
1458
1459 static void gen_spr_74xx (CPUPPCState *env)
1460 {
1461 /* Processor identification */
1462 spr_register(env, SPR_PIR, "PIR",
1463 SPR_NOACCESS, SPR_NOACCESS,
1464 &spr_read_generic, &spr_write_pir,
1465 0x00000000);
1466 /* XXX : not implemented */
1467 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
1468 SPR_NOACCESS, SPR_NOACCESS,
1469 &spr_read_generic, &spr_write_generic,
1470 0x00000000);
1471 /* XXX : not implemented */
1472 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
1473 &spr_read_ureg, SPR_NOACCESS,
1474 &spr_read_ureg, SPR_NOACCESS,
1475 0x00000000);
1476 /* XXX: not implemented */
1477 spr_register(env, SPR_BAMR, "BAMR",
1478 SPR_NOACCESS, SPR_NOACCESS,
1479 &spr_read_generic, &spr_write_generic,
1480 0x00000000);
1481 /* XXX : not implemented */
1482 spr_register(env, SPR_MSSCR0, "MSSCR0",
1483 SPR_NOACCESS, SPR_NOACCESS,
1484 &spr_read_generic, &spr_write_generic,
1485 0x00000000);
1486 /* Hardware implementation registers */
1487 /* XXX : not implemented */
1488 spr_register(env, SPR_HID0, "HID0",
1489 SPR_NOACCESS, SPR_NOACCESS,
1490 &spr_read_generic, &spr_write_generic,
1491 0x00000000);
1492 /* XXX : not implemented */
1493 spr_register(env, SPR_HID1, "HID1",
1494 SPR_NOACCESS, SPR_NOACCESS,
1495 &spr_read_generic, &spr_write_generic,
1496 0x00000000);
1497 /* Altivec */
1498 spr_register(env, SPR_VRSAVE, "VRSAVE",
1499 &spr_read_generic, &spr_write_generic,
1500 &spr_read_generic, &spr_write_generic,
1501 0x00000000);
1502 /* XXX : not implemented */
1503 spr_register(env, SPR_L2CR, "L2CR",
1504 SPR_NOACCESS, SPR_NOACCESS,
1505 &spr_read_generic, spr_access_nop,
1506 0x00000000);
1507 /* Not strictly an SPR */
1508 vscr_init(env, 0x00010000);
1509 }
1510
1511 static void gen_l3_ctrl (CPUPPCState *env)
1512 {
1513 /* L3CR */
1514 /* XXX : not implemented */
1515 spr_register(env, SPR_L3CR, "L3CR",
1516 SPR_NOACCESS, SPR_NOACCESS,
1517 &spr_read_generic, &spr_write_generic,
1518 0x00000000);
1519 /* L3ITCR0 */
1520 /* XXX : not implemented */
1521 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1522 SPR_NOACCESS, SPR_NOACCESS,
1523 &spr_read_generic, &spr_write_generic,
1524 0x00000000);
1525 /* L3PM */
1526 /* XXX : not implemented */
1527 spr_register(env, SPR_L3PM, "L3PM",
1528 SPR_NOACCESS, SPR_NOACCESS,
1529 &spr_read_generic, &spr_write_generic,
1530 0x00000000);
1531 }
1532
1533 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1534 {
1535 #if !defined(CONFIG_USER_ONLY)
1536 env->nb_tlb = nb_tlbs;
1537 env->nb_ways = nb_ways;
1538 env->id_tlbs = 1;
1539 env->tlb_type = TLB_6XX;
1540 /* XXX : not implemented */
1541 spr_register(env, SPR_PTEHI, "PTEHI",
1542 SPR_NOACCESS, SPR_NOACCESS,
1543 &spr_read_generic, &spr_write_generic,
1544 0x00000000);
1545 /* XXX : not implemented */
1546 spr_register(env, SPR_PTELO, "PTELO",
1547 SPR_NOACCESS, SPR_NOACCESS,
1548 &spr_read_generic, &spr_write_generic,
1549 0x00000000);
1550 /* XXX : not implemented */
1551 spr_register(env, SPR_TLBMISS, "TLBMISS",
1552 SPR_NOACCESS, SPR_NOACCESS,
1553 &spr_read_generic, &spr_write_generic,
1554 0x00000000);
1555 #endif
1556 }
1557
1558 #if !defined(CONFIG_USER_ONLY)
1559 static void spr_write_e500_l1csr0 (DisasContext *ctx, int sprn, int gprn)
1560 {
1561 TCGv t0 = tcg_temp_new();
1562
1563 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1564 gen_store_spr(sprn, t0);
1565 tcg_temp_free(t0);
1566 }
1567
1568 static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1569 {
1570 TCGv t0 = tcg_temp_new();
1571
1572 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1573 gen_store_spr(sprn, t0);
1574 tcg_temp_free(t0);
1575 }
1576
1577 static void spr_write_booke206_mmucsr0 (DisasContext *ctx, int sprn, int gprn)
1578 {
1579 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1580 }
1581
1582 static void spr_write_booke_pid (DisasContext *ctx, int sprn, int gprn)
1583 {
1584 TCGv_i32 t0 = tcg_const_i32(sprn);
1585 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1586 tcg_temp_free_i32(t0);
1587 }
1588 #endif
1589
1590 static void gen_spr_usprgh (CPUPPCState *env)
1591 {
1592 spr_register(env, SPR_USPRG4, "USPRG4",
1593 &spr_read_ureg, SPR_NOACCESS,
1594 &spr_read_ureg, SPR_NOACCESS,
1595 0x00000000);
1596 spr_register(env, SPR_USPRG5, "USPRG5",
1597 &spr_read_ureg, SPR_NOACCESS,
1598 &spr_read_ureg, SPR_NOACCESS,
1599 0x00000000);
1600 spr_register(env, SPR_USPRG6, "USPRG6",
1601 &spr_read_ureg, SPR_NOACCESS,
1602 &spr_read_ureg, SPR_NOACCESS,
1603 0x00000000);
1604 spr_register(env, SPR_USPRG7, "USPRG7",
1605 &spr_read_ureg, SPR_NOACCESS,
1606 &spr_read_ureg, SPR_NOACCESS,
1607 0x00000000);
1608 }
1609
1610 /* PowerPC BookE SPR */
1611 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1612 {
1613 const char *ivor_names[64] = {
1614 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1615 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1616 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1617 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1618 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1619 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1620 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1621 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1622 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1623 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1624 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1625 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1626 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1627 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1628 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1629 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1630 };
1631 #define SPR_BOOKE_IVORxx (-1)
1632 int ivor_sprn[64] = {
1633 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1634 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1635 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1636 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1637 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1638 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1639 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1640 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1641 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1642 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1643 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1644 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1645 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1646 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1647 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1648 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1649 };
1650 int i;
1651
1652 /* Interrupt processing */
1653 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1654 SPR_NOACCESS, SPR_NOACCESS,
1655 &spr_read_generic, &spr_write_generic,
1656 0x00000000);
1657 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1658 SPR_NOACCESS, SPR_NOACCESS,
1659 &spr_read_generic, &spr_write_generic,
1660 0x00000000);
1661 /* Debug */
1662 /* XXX : not implemented */
1663 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1664 SPR_NOACCESS, SPR_NOACCESS,
1665 &spr_read_generic, &spr_write_generic,
1666 0x00000000);
1667 /* XXX : not implemented */
1668 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1669 SPR_NOACCESS, SPR_NOACCESS,
1670 &spr_read_generic, &spr_write_generic,
1671 0x00000000);
1672 /* XXX : not implemented */
1673 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1674 SPR_NOACCESS, SPR_NOACCESS,
1675 &spr_read_generic, &spr_write_generic,
1676 0x00000000);
1677 /* XXX : not implemented */
1678 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1679 SPR_NOACCESS, SPR_NOACCESS,
1680 &spr_read_generic, &spr_write_generic,
1681 0x00000000);
1682 /* XXX : not implemented */
1683 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1684 SPR_NOACCESS, SPR_NOACCESS,
1685 &spr_read_generic, &spr_write_40x_dbcr0,
1686 0x00000000);
1687 /* XXX : not implemented */
1688 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1689 SPR_NOACCESS, SPR_NOACCESS,
1690 &spr_read_generic, &spr_write_generic,
1691 0x00000000);
1692 /* XXX : not implemented */
1693 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1694 SPR_NOACCESS, SPR_NOACCESS,
1695 &spr_read_generic, &spr_write_generic,
1696 0x00000000);
1697 /* XXX : not implemented */
1698 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1699 SPR_NOACCESS, SPR_NOACCESS,
1700 &spr_read_generic, &spr_write_clear,
1701 0x00000000);
1702 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1703 SPR_NOACCESS, SPR_NOACCESS,
1704 &spr_read_generic, &spr_write_generic,
1705 0x00000000);
1706 spr_register(env, SPR_BOOKE_ESR, "ESR",
1707 SPR_NOACCESS, SPR_NOACCESS,
1708 &spr_read_generic, &spr_write_generic,
1709 0x00000000);
1710 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1711 SPR_NOACCESS, SPR_NOACCESS,
1712 &spr_read_generic, &spr_write_excp_prefix,
1713 0x00000000);
1714 /* Exception vectors */
1715 for (i = 0; i < 64; i++) {
1716 if (ivor_mask & (1ULL << i)) {
1717 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1718 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1719 exit(1);
1720 }
1721 spr_register(env, ivor_sprn[i], ivor_names[i],
1722 SPR_NOACCESS, SPR_NOACCESS,
1723 &spr_read_generic, &spr_write_excp_vector,
1724 0x00000000);
1725 }
1726 }
1727 spr_register(env, SPR_BOOKE_PID, "PID",
1728 SPR_NOACCESS, SPR_NOACCESS,
1729 &spr_read_generic, &spr_write_booke_pid,
1730 0x00000000);
1731 spr_register(env, SPR_BOOKE_TCR, "TCR",
1732 SPR_NOACCESS, SPR_NOACCESS,
1733 &spr_read_generic, &spr_write_booke_tcr,
1734 0x00000000);
1735 spr_register(env, SPR_BOOKE_TSR, "TSR",
1736 SPR_NOACCESS, SPR_NOACCESS,
1737 &spr_read_generic, &spr_write_booke_tsr,
1738 0x00000000);
1739 /* Timer */
1740 spr_register(env, SPR_DECR, "DECR",
1741 SPR_NOACCESS, SPR_NOACCESS,
1742 &spr_read_decr, &spr_write_decr,
1743 0x00000000);
1744 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1745 SPR_NOACCESS, SPR_NOACCESS,
1746 SPR_NOACCESS, &spr_write_generic,
1747 0x00000000);
1748 /* SPRGs */
1749 spr_register(env, SPR_USPRG0, "USPRG0",
1750 &spr_read_generic, &spr_write_generic,
1751 &spr_read_generic, &spr_write_generic,
1752 0x00000000);
1753 spr_register(env, SPR_SPRG4, "SPRG4",
1754 SPR_NOACCESS, SPR_NOACCESS,
1755 &spr_read_generic, &spr_write_generic,
1756 0x00000000);
1757 spr_register(env, SPR_SPRG5, "SPRG5",
1758 SPR_NOACCESS, SPR_NOACCESS,
1759 &spr_read_generic, &spr_write_generic,
1760 0x00000000);
1761 spr_register(env, SPR_SPRG6, "SPRG6",
1762 SPR_NOACCESS, SPR_NOACCESS,
1763 &spr_read_generic, &spr_write_generic,
1764 0x00000000);
1765 spr_register(env, SPR_SPRG7, "SPRG7",
1766 SPR_NOACCESS, SPR_NOACCESS,
1767 &spr_read_generic, &spr_write_generic,
1768 0x00000000);
1769 }
1770
1771 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1772 uint32_t maxsize, uint32_t flags,
1773 uint32_t nentries)
1774 {
1775 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1776 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1777 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1778 flags | nentries;
1779 }
1780
1781 /* BookE 2.06 storage control registers */
1782 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1783 uint32_t *tlbncfg)
1784 {
1785 #if !defined(CONFIG_USER_ONLY)
1786 const char *mas_names[8] = {
1787 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1788 };
1789 int mas_sprn[8] = {
1790 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1791 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1792 };
1793 int i;
1794
1795 /* TLB assist registers */
1796 /* XXX : not implemented */
1797 for (i = 0; i < 8; i++) {
1798 void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = &spr_write_generic32;
1799 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1800 uea_write = &spr_write_generic;
1801 }
1802 if (mas_mask & (1 << i)) {
1803 spr_register(env, mas_sprn[i], mas_names[i],
1804 SPR_NOACCESS, SPR_NOACCESS,
1805 &spr_read_generic, uea_write,
1806 0x00000000);
1807 }
1808 }
1809 if (env->nb_pids > 1) {
1810 /* XXX : not implemented */
1811 spr_register(env, SPR_BOOKE_PID1, "PID1",
1812 SPR_NOACCESS, SPR_NOACCESS,
1813 &spr_read_generic, &spr_write_booke_pid,
1814 0x00000000);
1815 }
1816 if (env->nb_pids > 2) {
1817 /* XXX : not implemented */
1818 spr_register(env, SPR_BOOKE_PID2, "PID2",
1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_generic, &spr_write_booke_pid,
1821 0x00000000);
1822 }
1823 /* XXX : not implemented */
1824 spr_register(env, SPR_MMUCFG, "MMUCFG",
1825 SPR_NOACCESS, SPR_NOACCESS,
1826 &spr_read_generic, SPR_NOACCESS,
1827 0x00000000); /* TOFIX */
1828 switch (env->nb_ways) {
1829 case 4:
1830 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1831 SPR_NOACCESS, SPR_NOACCESS,
1832 &spr_read_generic, SPR_NOACCESS,
1833 tlbncfg[3]);
1834 /* Fallthru */
1835 case 3:
1836 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1837 SPR_NOACCESS, SPR_NOACCESS,
1838 &spr_read_generic, SPR_NOACCESS,
1839 tlbncfg[2]);
1840 /* Fallthru */
1841 case 2:
1842 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1843 SPR_NOACCESS, SPR_NOACCESS,
1844 &spr_read_generic, SPR_NOACCESS,
1845 tlbncfg[1]);
1846 /* Fallthru */
1847 case 1:
1848 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1849 SPR_NOACCESS, SPR_NOACCESS,
1850 &spr_read_generic, SPR_NOACCESS,
1851 tlbncfg[0]);
1852 /* Fallthru */
1853 case 0:
1854 default:
1855 break;
1856 }
1857 #endif
1858
1859 gen_spr_usprgh(env);
1860 }
1861
1862 /* SPR specific to PowerPC 440 implementation */
1863 static void gen_spr_440 (CPUPPCState *env)
1864 {
1865 /* Cache control */
1866 /* XXX : not implemented */
1867 spr_register(env, SPR_440_DNV0, "DNV0",
1868 SPR_NOACCESS, SPR_NOACCESS,
1869 &spr_read_generic, &spr_write_generic,
1870 0x00000000);
1871 /* XXX : not implemented */
1872 spr_register(env, SPR_440_DNV1, "DNV1",
1873 SPR_NOACCESS, SPR_NOACCESS,
1874 &spr_read_generic, &spr_write_generic,
1875 0x00000000);
1876 /* XXX : not implemented */
1877 spr_register(env, SPR_440_DNV2, "DNV2",
1878 SPR_NOACCESS, SPR_NOACCESS,
1879 &spr_read_generic, &spr_write_generic,
1880 0x00000000);
1881 /* XXX : not implemented */
1882 spr_register(env, SPR_440_DNV3, "DNV3",
1883 SPR_NOACCESS, SPR_NOACCESS,
1884 &spr_read_generic, &spr_write_generic,
1885 0x00000000);
1886 /* XXX : not implemented */
1887 spr_register(env, SPR_440_DTV0, "DTV0",
1888 SPR_NOACCESS, SPR_NOACCESS,
1889 &spr_read_generic, &spr_write_generic,
1890 0x00000000);
1891 /* XXX : not implemented */
1892 spr_register(env, SPR_440_DTV1, "DTV1",
1893 SPR_NOACCESS, SPR_NOACCESS,
1894 &spr_read_generic, &spr_write_generic,
1895 0x00000000);
1896 /* XXX : not implemented */
1897 spr_register(env, SPR_440_DTV2, "DTV2",
1898 SPR_NOACCESS, SPR_NOACCESS,
1899 &spr_read_generic, &spr_write_generic,
1900 0x00000000);
1901 /* XXX : not implemented */
1902 spr_register(env, SPR_440_DTV3, "DTV3",
1903 SPR_NOACCESS, SPR_NOACCESS,
1904 &spr_read_generic, &spr_write_generic,
1905 0x00000000);
1906 /* XXX : not implemented */
1907 spr_register(env, SPR_440_DVLIM, "DVLIM",
1908 SPR_NOACCESS, SPR_NOACCESS,
1909 &spr_read_generic, &spr_write_generic,
1910 0x00000000);
1911 /* XXX : not implemented */
1912 spr_register(env, SPR_440_INV0, "INV0",
1913 SPR_NOACCESS, SPR_NOACCESS,
1914 &spr_read_generic, &spr_write_generic,
1915 0x00000000);
1916 /* XXX : not implemented */
1917 spr_register(env, SPR_440_INV1, "INV1",
1918 SPR_NOACCESS, SPR_NOACCESS,
1919 &spr_read_generic, &spr_write_generic,
1920 0x00000000);
1921 /* XXX : not implemented */
1922 spr_register(env, SPR_440_INV2, "INV2",
1923 SPR_NOACCESS, SPR_NOACCESS,
1924 &spr_read_generic, &spr_write_generic,
1925 0x00000000);
1926 /* XXX : not implemented */
1927 spr_register(env, SPR_440_INV3, "INV3",
1928 SPR_NOACCESS, SPR_NOACCESS,
1929 &spr_read_generic, &spr_write_generic,
1930 0x00000000);
1931 /* XXX : not implemented */
1932 spr_register(env, SPR_440_ITV0, "ITV0",
1933 SPR_NOACCESS, SPR_NOACCESS,
1934 &spr_read_generic, &spr_write_generic,
1935 0x00000000);
1936 /* XXX : not implemented */
1937 spr_register(env, SPR_440_ITV1, "ITV1",
1938 SPR_NOACCESS, SPR_NOACCESS,
1939 &spr_read_generic, &spr_write_generic,
1940 0x00000000);
1941 /* XXX : not implemented */
1942 spr_register(env, SPR_440_ITV2, "ITV2",
1943 SPR_NOACCESS, SPR_NOACCESS,
1944 &spr_read_generic, &spr_write_generic,
1945 0x00000000);
1946 /* XXX : not implemented */
1947 spr_register(env, SPR_440_ITV3, "ITV3",
1948 SPR_NOACCESS, SPR_NOACCESS,
1949 &spr_read_generic, &spr_write_generic,
1950 0x00000000);
1951 /* XXX : not implemented */
1952 spr_register(env, SPR_440_IVLIM, "IVLIM",
1953 SPR_NOACCESS, SPR_NOACCESS,
1954 &spr_read_generic, &spr_write_generic,
1955 0x00000000);
1956 /* Cache debug */
1957 /* XXX : not implemented */
1958 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1959 SPR_NOACCESS, SPR_NOACCESS,
1960 &spr_read_generic, SPR_NOACCESS,
1961 0x00000000);
1962 /* XXX : not implemented */
1963 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1964 SPR_NOACCESS, SPR_NOACCESS,
1965 &spr_read_generic, SPR_NOACCESS,
1966 0x00000000);
1967 /* XXX : not implemented */
1968 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1969 SPR_NOACCESS, SPR_NOACCESS,
1970 &spr_read_generic, SPR_NOACCESS,
1971 0x00000000);
1972 /* XXX : not implemented */
1973 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1974 SPR_NOACCESS, SPR_NOACCESS,
1975 &spr_read_generic, SPR_NOACCESS,
1976 0x00000000);
1977 /* XXX : not implemented */
1978 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1979 SPR_NOACCESS, SPR_NOACCESS,
1980 &spr_read_generic, SPR_NOACCESS,
1981 0x00000000);
1982 /* XXX : not implemented */
1983 spr_register(env, SPR_440_DBDR, "DBDR",
1984 SPR_NOACCESS, SPR_NOACCESS,
1985 &spr_read_generic, &spr_write_generic,
1986 0x00000000);
1987 /* Processor control */
1988 spr_register(env, SPR_4xx_CCR0, "CCR0",
1989 SPR_NOACCESS, SPR_NOACCESS,
1990 &spr_read_generic, &spr_write_generic,
1991 0x00000000);
1992 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1993 SPR_NOACCESS, SPR_NOACCESS,
1994 &spr_read_generic, SPR_NOACCESS,
1995 0x00000000);
1996 /* Storage control */
1997 spr_register(env, SPR_440_MMUCR, "MMUCR",
1998 SPR_NOACCESS, SPR_NOACCESS,
1999 &spr_read_generic, &spr_write_generic,
2000 0x00000000);
2001 }
2002
2003 /* SPR shared between PowerPC 40x implementations */
2004 static void gen_spr_40x (CPUPPCState *env)
2005 {
2006 /* Cache */
2007 /* not emulated, as QEMU do not emulate caches */
2008 spr_register(env, SPR_40x_DCCR, "DCCR",
2009 SPR_NOACCESS, SPR_NOACCESS,
2010 &spr_read_generic, &spr_write_generic,
2011 0x00000000);
2012 /* not emulated, as QEMU do not emulate caches */
2013 spr_register(env, SPR_40x_ICCR, "ICCR",
2014 SPR_NOACCESS, SPR_NOACCESS,
2015 &spr_read_generic, &spr_write_generic,
2016 0x00000000);
2017 /* not emulated, as QEMU do not emulate caches */
2018 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2019 SPR_NOACCESS, SPR_NOACCESS,
2020 &spr_read_generic, SPR_NOACCESS,
2021 0x00000000);
2022 /* Exception */
2023 spr_register(env, SPR_40x_DEAR, "DEAR",
2024 SPR_NOACCESS, SPR_NOACCESS,
2025 &spr_read_generic, &spr_write_generic,
2026 0x00000000);
2027 spr_register(env, SPR_40x_ESR, "ESR",
2028 SPR_NOACCESS, SPR_NOACCESS,
2029 &spr_read_generic, &spr_write_generic,
2030 0x00000000);
2031 spr_register(env, SPR_40x_EVPR, "EVPR",
2032 SPR_NOACCESS, SPR_NOACCESS,
2033 &spr_read_generic, &spr_write_excp_prefix,
2034 0x00000000);
2035 spr_register(env, SPR_40x_SRR2, "SRR2",
2036 &spr_read_generic, &spr_write_generic,
2037 &spr_read_generic, &spr_write_generic,
2038 0x00000000);
2039 spr_register(env, SPR_40x_SRR3, "SRR3",
2040 &spr_read_generic, &spr_write_generic,
2041 &spr_read_generic, &spr_write_generic,
2042 0x00000000);
2043 /* Timers */
2044 spr_register(env, SPR_40x_PIT, "PIT",
2045 SPR_NOACCESS, SPR_NOACCESS,
2046 &spr_read_40x_pit, &spr_write_40x_pit,
2047 0x00000000);
2048 spr_register(env, SPR_40x_TCR, "TCR",
2049 SPR_NOACCESS, SPR_NOACCESS,
2050 &spr_read_generic, &spr_write_booke_tcr,
2051 0x00000000);
2052 spr_register(env, SPR_40x_TSR, "TSR",
2053 SPR_NOACCESS, SPR_NOACCESS,
2054 &spr_read_generic, &spr_write_booke_tsr,
2055 0x00000000);
2056 }
2057
2058 /* SPR specific to PowerPC 405 implementation */
2059 static void gen_spr_405 (CPUPPCState *env)
2060 {
2061 /* MMU */
2062 spr_register(env, SPR_40x_PID, "PID",
2063 SPR_NOACCESS, SPR_NOACCESS,
2064 &spr_read_generic, &spr_write_generic,
2065 0x00000000);
2066 spr_register(env, SPR_4xx_CCR0, "CCR0",
2067 SPR_NOACCESS, SPR_NOACCESS,
2068 &spr_read_generic, &spr_write_generic,
2069 0x00700000);
2070 /* Debug interface */
2071 /* XXX : not implemented */
2072 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2073 SPR_NOACCESS, SPR_NOACCESS,
2074 &spr_read_generic, &spr_write_40x_dbcr0,
2075 0x00000000);
2076 /* XXX : not implemented */
2077 spr_register(env, SPR_405_DBCR1, "DBCR1",
2078 SPR_NOACCESS, SPR_NOACCESS,
2079 &spr_read_generic, &spr_write_generic,
2080 0x00000000);
2081 /* XXX : not implemented */
2082 spr_register(env, SPR_40x_DBSR, "DBSR",
2083 SPR_NOACCESS, SPR_NOACCESS,
2084 &spr_read_generic, &spr_write_clear,
2085 /* Last reset was system reset */
2086 0x00000300);
2087 /* XXX : not implemented */
2088 spr_register(env, SPR_40x_DAC1, "DAC1",
2089 SPR_NOACCESS, SPR_NOACCESS,
2090 &spr_read_generic, &spr_write_generic,
2091 0x00000000);
2092 spr_register(env, SPR_40x_DAC2, "DAC2",
2093 SPR_NOACCESS, SPR_NOACCESS,
2094 &spr_read_generic, &spr_write_generic,
2095 0x00000000);
2096 /* XXX : not implemented */
2097 spr_register(env, SPR_405_DVC1, "DVC1",
2098 SPR_NOACCESS, SPR_NOACCESS,
2099 &spr_read_generic, &spr_write_generic,
2100 0x00000000);
2101 /* XXX : not implemented */
2102 spr_register(env, SPR_405_DVC2, "DVC2",
2103 SPR_NOACCESS, SPR_NOACCESS,
2104 &spr_read_generic, &spr_write_generic,
2105 0x00000000);
2106 /* XXX : not implemented */
2107 spr_register(env, SPR_40x_IAC1, "IAC1",
2108 SPR_NOACCESS, SPR_NOACCESS,
2109 &spr_read_generic, &spr_write_generic,
2110 0x00000000);
2111 spr_register(env, SPR_40x_IAC2, "IAC2",
2112 SPR_NOACCESS, SPR_NOACCESS,
2113 &spr_read_generic, &spr_write_generic,
2114 0x00000000);
2115 /* XXX : not implemented */
2116 spr_register(env, SPR_405_IAC3, "IAC3",
2117 SPR_NOACCESS, SPR_NOACCESS,
2118 &spr_read_generic, &spr_write_generic,
2119 0x00000000);
2120 /* XXX : not implemented */
2121 spr_register(env, SPR_405_IAC4, "IAC4",
2122 SPR_NOACCESS, SPR_NOACCESS,
2123 &spr_read_generic, &spr_write_generic,
2124 0x00000000);
2125 /* Storage control */
2126 /* XXX: TODO: not implemented */
2127 spr_register(env, SPR_405_SLER, "SLER",
2128 SPR_NOACCESS, SPR_NOACCESS,
2129 &spr_read_generic, &spr_write_40x_sler,
2130 0x00000000);
2131 spr_register(env, SPR_40x_ZPR, "ZPR",
2132 SPR_NOACCESS, SPR_NOACCESS,
2133 &spr_read_generic, &spr_write_generic,
2134 0x00000000);
2135 /* XXX : not implemented */
2136 spr_register(env, SPR_405_SU0R, "SU0R",
2137 SPR_NOACCESS, SPR_NOACCESS,
2138 &spr_read_generic, &spr_write_generic,
2139 0x00000000);
2140 /* SPRG */
2141 spr_register(env, SPR_USPRG0, "USPRG0",
2142 &spr_read_ureg, SPR_NOACCESS,
2143 &spr_read_ureg, SPR_NOACCESS,
2144 0x00000000);
2145 spr_register(env, SPR_SPRG4, "SPRG4",
2146 SPR_NOACCESS, SPR_NOACCESS,
2147 &spr_read_generic, &spr_write_generic,
2148 0x00000000);
2149 spr_register(env, SPR_SPRG5, "SPRG5",
2150 SPR_NOACCESS, SPR_NOACCESS,
2151 spr_read_generic, &spr_write_generic,
2152 0x00000000);
2153 spr_register(env, SPR_SPRG6, "SPRG6",
2154 SPR_NOACCESS, SPR_NOACCESS,
2155 spr_read_generic, &spr_write_generic,
2156 0x00000000);
2157 spr_register(env, SPR_SPRG7, "SPRG7",
2158 SPR_NOACCESS, SPR_NOACCESS,
2159 spr_read_generic, &spr_write_generic,
2160 0x00000000);
2161 gen_spr_usprgh(env);
2162 }
2163
2164 /* SPR shared between PowerPC 401 & 403 implementations */
2165 static void gen_spr_401_403 (CPUPPCState *env)
2166 {
2167 /* Time base */
2168 spr_register(env, SPR_403_VTBL, "TBL",
2169 &spr_read_tbl, SPR_NOACCESS,
2170 &spr_read_tbl, SPR_NOACCESS,
2171 0x00000000);
2172 spr_register(env, SPR_403_TBL, "TBL",
2173 SPR_NOACCESS, SPR_NOACCESS,
2174 SPR_NOACCESS, &spr_write_tbl,
2175 0x00000000);
2176 spr_register(env, SPR_403_VTBU, "TBU",
2177 &spr_read_tbu, SPR_NOACCESS,
2178 &spr_read_tbu, SPR_NOACCESS,
2179 0x00000000);
2180 spr_register(env, SPR_403_TBU, "TBU",
2181 SPR_NOACCESS, SPR_NOACCESS,
2182 SPR_NOACCESS, &spr_write_tbu,
2183 0x00000000);
2184 /* Debug */
2185 /* not emulated, as QEMU do not emulate caches */
2186 spr_register(env, SPR_403_CDBCR, "CDBCR",
2187 SPR_NOACCESS, SPR_NOACCESS,
2188 &spr_read_generic, &spr_write_generic,
2189 0x00000000);
2190 }
2191
2192 /* SPR specific to PowerPC 401 implementation */
2193 static void gen_spr_401 (CPUPPCState *env)
2194 {
2195 /* Debug interface */
2196 /* XXX : not implemented */
2197 spr_register(env, SPR_40x_DBCR0, "DBCR",
2198 SPR_NOACCESS, SPR_NOACCESS,
2199 &spr_read_generic, &spr_write_40x_dbcr0,
2200 0x00000000);
2201 /* XXX : not implemented */
2202 spr_register(env, SPR_40x_DBSR, "DBSR",
2203 SPR_NOACCESS, SPR_NOACCESS,
2204 &spr_read_generic, &spr_write_clear,
2205 /* Last reset was system reset */
2206 0x00000300);
2207 /* XXX : not implemented */
2208 spr_register(env, SPR_40x_DAC1, "DAC",
2209 SPR_NOACCESS, SPR_NOACCESS,
2210 &spr_read_generic, &spr_write_generic,
2211 0x00000000);
2212 /* XXX : not implemented */
2213 spr_register(env, SPR_40x_IAC1, "IAC",
2214 SPR_NOACCESS, SPR_NOACCESS,
2215 &spr_read_generic, &spr_write_generic,
2216 0x00000000);
2217 /* Storage control */
2218 /* XXX: TODO: not implemented */
2219 spr_register(env, SPR_405_SLER, "SLER",
2220 SPR_NOACCESS, SPR_NOACCESS,
2221 &spr_read_generic, &spr_write_40x_sler,
2222 0x00000000);
2223 /* not emulated, as QEMU never does speculative access */
2224 spr_register(env, SPR_40x_SGR, "SGR",
2225 SPR_NOACCESS, SPR_NOACCESS,
2226 &spr_read_generic, &spr_write_generic,
2227 0xFFFFFFFF);
2228 /* not emulated, as QEMU do not emulate caches */
2229 spr_register(env, SPR_40x_DCWR, "DCWR",
2230 SPR_NOACCESS, SPR_NOACCESS,
2231 &spr_read_generic, &spr_write_generic,
2232 0x00000000);
2233 }
2234
2235 static void gen_spr_401x2 (CPUPPCState *env)
2236 {
2237 gen_spr_401(env);
2238 spr_register(env, SPR_40x_PID, "PID",
2239 SPR_NOACCESS, SPR_NOACCESS,
2240 &spr_read_generic, &spr_write_generic,
2241 0x00000000);
2242 spr_register(env, SPR_40x_ZPR, "ZPR",
2243 SPR_NOACCESS, SPR_NOACCESS,
2244 &spr_read_generic, &spr_write_generic,
2245 0x00000000);
2246 }
2247
2248 /* SPR specific to PowerPC 403 implementation */
2249 static void gen_spr_403 (CPUPPCState *env)
2250 {
2251 /* Debug interface */
2252 /* XXX : not implemented */
2253 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2254 SPR_NOACCESS, SPR_NOACCESS,
2255 &spr_read_generic, &spr_write_40x_dbcr0,
2256 0x00000000);
2257 /* XXX : not implemented */
2258 spr_register(env, SPR_40x_DBSR, "DBSR",
2259 SPR_NOACCESS, SPR_NOACCESS,
2260 &spr_read_generic, &spr_write_clear,
2261 /* Last reset was system reset */
2262 0x00000300);
2263 /* XXX : not implemented */
2264 spr_register(env, SPR_40x_DAC1, "DAC1",
2265 SPR_NOACCESS, SPR_NOACCESS,
2266 &spr_read_generic, &spr_write_generic,
2267 0x00000000);
2268 /* XXX : not implemented */
2269 spr_register(env, SPR_40x_DAC2, "DAC2",
2270 SPR_NOACCESS, SPR_NOACCESS,
2271 &spr_read_generic, &spr_write_generic,
2272 0x00000000);
2273 /* XXX : not implemented */
2274 spr_register(env, SPR_40x_IAC1, "IAC1",
2275 SPR_NOACCESS, SPR_NOACCESS,
2276 &spr_read_generic, &spr_write_generic,
2277 0x00000000);
2278 /* XXX : not implemented */
2279 spr_register(env, SPR_40x_IAC2, "IAC2",
2280 SPR_NOACCESS, SPR_NOACCESS,
2281 &spr_read_generic, &spr_write_generic,
2282 0x00000000);
2283 }
2284
2285 static void gen_spr_403_real (CPUPPCState *env)
2286 {
2287 spr_register(env, SPR_403_PBL1, "PBL1",
2288 SPR_NOACCESS, SPR_NOACCESS,
2289 &spr_read_403_pbr, &spr_write_403_pbr,
2290 0x00000000);
2291 spr_register(env, SPR_403_PBU1, "PBU1",
2292 SPR_NOACCESS, SPR_NOACCESS,
2293 &spr_read_403_pbr, &spr_write_403_pbr,
2294 0x00000000);
2295 spr_register(env, SPR_403_PBL2, "PBL2",
2296 SPR_NOACCESS, SPR_NOACCESS,
2297 &spr_read_403_pbr, &spr_write_403_pbr,
2298 0x00000000);
2299 spr_register(env, SPR_403_PBU2, "PBU2",
2300 SPR_NOACCESS, SPR_NOACCESS,
2301 &spr_read_403_pbr, &spr_write_403_pbr,
2302 0x00000000);
2303 }
2304
2305 static void gen_spr_403_mmu (CPUPPCState *env)
2306 {
2307 /* MMU */
2308 spr_register(env, SPR_40x_PID, "PID",
2309 SPR_NOACCESS, SPR_NOACCESS,
2310 &spr_read_generic, &spr_write_generic,
2311 0x00000000);
2312 spr_register(env, SPR_40x_ZPR, "ZPR",
2313 SPR_NOACCESS, SPR_NOACCESS,
2314 &spr_read_generic, &spr_write_generic,
2315 0x00000000);
2316 }
2317
2318 /* SPR specific to PowerPC compression coprocessor extension */
2319 static void gen_spr_compress (CPUPPCState *env)
2320 {
2321 /* XXX : not implemented */
2322 spr_register(env, SPR_401_SKR, "SKR",
2323 SPR_NOACCESS, SPR_NOACCESS,
2324 &spr_read_generic, &spr_write_generic,
2325 0x00000000);
2326 }
2327
2328 static void gen_spr_5xx_8xx (CPUPPCState *env)
2329 {
2330 /* Exception processing */
2331 spr_register_kvm(env, SPR_DSISR, "DSISR",
2332 SPR_NOACCESS, SPR_NOACCESS,
2333 &spr_read_generic, &spr_write_generic,
2334 KVM_REG_PPC_DSISR, 0x00000000);
2335 spr_register_kvm(env, SPR_DAR, "DAR",
2336 SPR_NOACCESS, SPR_NOACCESS,
2337 &spr_read_generic, &spr_write_generic,
2338 KVM_REG_PPC_DAR, 0x00000000);
2339 /* Timer */
2340 spr_register(env, SPR_DECR, "DECR",
2341 SPR_NOACCESS, SPR_NOACCESS,
2342 &spr_read_decr, &spr_write_decr,
2343 0x00000000);
2344 /* XXX : not implemented */
2345 spr_register(env, SPR_MPC_EIE, "EIE",
2346 SPR_NOACCESS, SPR_NOACCESS,
2347 &spr_read_generic, &spr_write_generic,
2348 0x00000000);
2349 /* XXX : not implemented */
2350 spr_register(env, SPR_MPC_EID, "EID",
2351 SPR_NOACCESS, SPR_NOACCESS,
2352 &spr_read_generic, &spr_write_generic,
2353 0x00000000);
2354 /* XXX : not implemented */
2355 spr_register(env, SPR_MPC_NRI, "NRI",
2356 SPR_NOACCESS, SPR_NOACCESS,
2357 &spr_read_generic, &spr_write_generic,
2358 0x00000000);
2359 /* XXX : not implemented */
2360 spr_register(env, SPR_MPC_CMPA, "CMPA",
2361 SPR_NOACCESS, SPR_NOACCESS,
2362 &spr_read_generic, &spr_write_generic,
2363 0x00000000);
2364 /* XXX : not implemented */
2365 spr_register(env, SPR_MPC_CMPB, "CMPB",
2366 SPR_NOACCESS, SPR_NOACCESS,
2367 &spr_read_generic, &spr_write_generic,
2368 0x00000000);
2369 /* XXX : not implemented */
2370 spr_register(env, SPR_MPC_CMPC, "CMPC",
2371 SPR_NOACCESS, SPR_NOACCESS,
2372 &spr_read_generic, &spr_write_generic,
2373 0x00000000);
2374 /* XXX : not implemented */
2375 spr_register(env, SPR_MPC_CMPD, "CMPD",
2376 SPR_NOACCESS, SPR_NOACCESS,
2377 &spr_read_generic, &spr_write_generic,
2378 0x00000000);
2379 /* XXX : not implemented */
2380 spr_register(env, SPR_MPC_ECR, "ECR",
2381 SPR_NOACCESS, SPR_NOACCESS,
2382 &spr_read_generic, &spr_write_generic,
2383 0x00000000);
2384 /* XXX : not implemented */
2385 spr_register(env, SPR_MPC_DER, "DER",
2386 SPR_NOACCESS, SPR_NOACCESS,
2387 &spr_read_generic, &spr_write_generic,
2388 0x00000000);
2389 /* XXX : not implemented */
2390 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2391 SPR_NOACCESS, SPR_NOACCESS,
2392 &spr_read_generic, &spr_write_generic,
2393 0x00000000);
2394 /* XXX : not implemented */
2395 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2396 SPR_NOACCESS, SPR_NOACCESS,
2397 &spr_read_generic, &spr_write_generic,
2398 0x00000000);
2399 /* XXX : not implemented */
2400 spr_register(env, SPR_MPC_CMPE, "CMPE",
2401 SPR_NOACCESS, SPR_NOACCESS,
2402 &spr_read_generic, &spr_write_generic,
2403 0x00000000);
2404 /* XXX : not implemented */
2405 spr_register(env, SPR_MPC_CMPF, "CMPF",
2406 SPR_NOACCESS, SPR_NOACCESS,
2407 &spr_read_generic, &spr_write_generic,
2408 0x00000000);
2409 /* XXX : not implemented */
2410 spr_register(env, SPR_MPC_CMPG, "CMPG",
2411 SPR_NOACCESS, SPR_NOACCESS,
2412 &spr_read_generic, &spr_write_generic,
2413 0x00000000);
2414 /* XXX : not implemented */
2415 spr_register(env, SPR_MPC_CMPH, "CMPH",
2416 SPR_NOACCESS, SPR_NOACCESS,
2417 &spr_read_generic, &spr_write_generic,
2418 0x00000000);
2419 /* XXX : not implemented */
2420 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2421 SPR_NOACCESS, SPR_NOACCESS,
2422 &spr_read_generic, &spr_write_generic,
2423 0x00000000);
2424 /* XXX : not implemented */
2425 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2426 SPR_NOACCESS, SPR_NOACCESS,
2427 &spr_read_generic, &spr_write_generic,
2428 0x00000000);
2429 /* XXX : not implemented */
2430 spr_register(env, SPR_MPC_BAR, "BAR",
2431 SPR_NOACCESS, SPR_NOACCESS,
2432 &spr_read_generic, &spr_write_generic,
2433 0x00000000);
2434 /* XXX : not implemented */
2435 spr_register(env, SPR_MPC_DPDR, "DPDR",
2436 SPR_NOACCESS, SPR_NOACCESS,
2437 &spr_read_generic, &spr_write_generic,
2438 0x00000000);
2439 /* XXX : not implemented */
2440 spr_register(env, SPR_MPC_IMMR, "IMMR",
2441 SPR_NOACCESS, SPR_NOACCESS,
2442 &spr_read_generic, &spr_write_generic,
2443 0x00000000);
2444 }
2445
2446 static void gen_spr_5xx (CPUPPCState *env)
2447 {
2448 /* XXX : not implemented */
2449 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2450 SPR_NOACCESS, SPR_NOACCESS,
2451 &spr_read_generic, &spr_write_generic,
2452 0x00000000);
2453 /* XXX : not implemented */
2454 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2455 SPR_NOACCESS, SPR_NOACCESS,
2456 &spr_read_generic, &spr_write_generic,
2457 0x00000000);
2458 /* XXX : not implemented */
2459 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2460 SPR_NOACCESS, SPR_NOACCESS,
2461 &spr_read_generic, &spr_write_generic,
2462 0x00000000);
2463 /* XXX : not implemented */
2464 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2465 SPR_NOACCESS, SPR_NOACCESS,
2466 &spr_read_generic, &spr_write_generic,
2467 0x00000000);
2468 /* XXX : not implemented */
2469 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2470 SPR_NOACCESS, SPR_NOACCESS,
2471 &spr_read_generic, &spr_write_generic,
2472 0x00000000);
2473 /* XXX : not implemented */
2474 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2475 SPR_NOACCESS, SPR_NOACCESS,
2476 &spr_read_generic, &spr_write_generic,
2477 0x00000000);
2478 /* XXX : not implemented */
2479 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2480 SPR_NOACCESS, SPR_NOACCESS,
2481 &spr_read_generic, &spr_write_generic,
2482 0x00000000);
2483 /* XXX : not implemented */
2484 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2485 SPR_NOACCESS, SPR_NOACCESS,
2486 &spr_read_generic, &spr_write_generic,
2487 0x00000000);
2488 /* XXX : not implemented */
2489 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2490 SPR_NOACCESS, SPR_NOACCESS,
2491 &spr_read_generic, &spr_write_generic,
2492 0x00000000);
2493 /* XXX : not implemented */
2494 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2495 SPR_NOACCESS, SPR_NOACCESS,
2496 &spr_read_generic, &spr_write_generic,
2497 0x00000000);
2498 /* XXX : not implemented */
2499 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2500 SPR_NOACCESS, SPR_NOACCESS,
2501 &spr_read_generic, &spr_write_generic,
2502 0x00000000);
2503 /* XXX : not implemented */
2504 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2505 SPR_NOACCESS, SPR_NOACCESS,
2506 &spr_read_generic, &spr_write_generic,
2507 0x00000000);
2508 /* XXX : not implemented */
2509 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2510 SPR_NOACCESS, SPR_NOACCESS,
2511 &spr_read_generic, &spr_write_generic,
2512 0x00000000);
2513 /* XXX : not implemented */
2514 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2515 SPR_NOACCESS, SPR_NOACCESS,
2516 &spr_read_generic, &spr_write_generic,
2517 0x00000000);
2518 /* XXX : not implemented */
2519 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2520 SPR_NOACCESS, SPR_NOACCESS,
2521 &spr_read_generic, &spr_write_generic,
2522 0x00000000);
2523 /* XXX : not implemented */
2524 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2525 SPR_NOACCESS, SPR_NOACCESS,
2526 &spr_read_generic, &spr_write_generic,
2527 0x00000000);
2528 /* XXX : not implemented */
2529 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2530 SPR_NOACCESS, SPR_NOACCESS,
2531 &spr_read_generic, &spr_write_generic,
2532 0x00000000);
2533 /* XXX : not implemented */
2534 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2535 SPR_NOACCESS, SPR_NOACCESS,
2536 &spr_read_generic, &spr_write_generic,
2537 0x00000000);
2538 /* XXX : not implemented */
2539 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2540 SPR_NOACCESS, SPR_NOACCESS,
2541 &spr_read_generic, &spr_write_generic,
2542 0x00000000);
2543 /* XXX : not implemented */
2544 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2545 SPR_NOACCESS, SPR_NOACCESS,
2546 &spr_read_generic, &spr_write_generic,
2547 0x00000000);
2548 /* XXX : not implemented */
2549 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2550 SPR_NOACCESS, SPR_NOACCESS,
2551 &spr_read_generic, &spr_write_generic,
2552 0x00000000);
2553 }
2554
2555 static void gen_spr_8xx (CPUPPCState *env)
2556 {
2557 /* XXX : not implemented */
2558 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2559 SPR_NOACCESS, SPR_NOACCESS,
2560 &spr_read_generic, &spr_write_generic,
2561 0x00000000);
2562 /* XXX : not implemented */
2563 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2564 SPR_NOACCESS, SPR_NOACCESS,
2565 &spr_read_generic, &spr_write_generic,
2566 0x00000000);
2567 /* XXX : not implemented */
2568 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2569 SPR_NOACCESS, SPR_NOACCESS,
2570 &spr_read_generic, &spr_write_generic,
2571 0x00000000);
2572 /* XXX : not implemented */
2573 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2574 SPR_NOACCESS, SPR_NOACCESS,
2575 &spr_read_generic, &spr_write_generic,
2576 0x00000000);
2577 /* XXX : not implemented */
2578 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2579 SPR_NOACCESS, SPR_NOACCESS,
2580 &spr_read_generic, &spr_write_generic,
2581 0x00000000);
2582 /* XXX : not implemented */
2583 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2584 SPR_NOACCESS, SPR_NOACCESS,
2585 &spr_read_generic, &spr_write_generic,
2586 0x00000000);
2587 /* XXX : not implemented */
2588 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2589 SPR_NOACCESS, SPR_NOACCESS,
2590 &spr_read_generic, &spr_write_generic,
2591 0x00000000);
2592 /* XXX : not implemented */
2593 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2594 SPR_NOACCESS, SPR_NOACCESS,
2595 &spr_read_generic, &spr_write_generic,
2596 0x00000000);
2597 /* XXX : not implemented */
2598 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2599 SPR_NOACCESS, SPR_NOACCESS,
2600 &spr_read_generic, &spr_write_generic,
2601 0x00000000);
2602 /* XXX : not implemented */
2603 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2604 SPR_NOACCESS, SPR_NOACCESS,
2605 &spr_read_generic, &spr_write_generic,
2606 0x00000000);
2607 /* XXX : not implemented */
2608 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2609 SPR_NOACCESS, SPR_NOACCESS,
2610 &spr_read_generic, &spr_write_generic,
2611 0x00000000);
2612 /* XXX : not implemented */
2613 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2614 SPR_NOACCESS, SPR_NOACCESS,
2615 &spr_read_generic, &spr_write_generic,
2616 0x00000000);
2617 /* XXX : not implemented */
2618 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2619 SPR_NOACCESS, SPR_NOACCESS,
2620 &spr_read_generic, &spr_write_generic,
2621 0x00000000);
2622 /* XXX : not implemented */
2623 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2624 SPR_NOACCESS, SPR_NOACCESS,
2625 &spr_read_generic, &spr_write_generic,
2626 0x00000000);
2627 /* XXX : not implemented */
2628 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2629 SPR_NOACCESS, SPR_NOACCESS,
2630 &spr_read_generic, &spr_write_generic,
2631 0x00000000);
2632 /* XXX : not implemented */
2633 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2634 SPR_NOACCESS, SPR_NOACCESS,
2635 &spr_read_generic, &spr_write_generic,
2636 0x00000000);
2637 /* XXX : not implemented */
2638 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2639 SPR_NOACCESS, SPR_NOACCESS,
2640 &spr_read_generic, &spr_write_generic,
2641 0x00000000);
2642 /* XXX : not implemented */
2643 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2644 SPR_NOACCESS, SPR_NOACCESS,
2645 &spr_read_generic, &spr_write_generic,
2646 0x00000000);
2647 /* XXX : not implemented */
2648 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2649 SPR_NOACCESS, SPR_NOACCESS,
2650 &spr_read_generic, &spr_write_generic,
2651 0x00000000);
2652 /* XXX : not implemented */
2653 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2654 SPR_NOACCESS, SPR_NOACCESS,
2655 &spr_read_generic, &spr_write_generic,
2656 0x00000000);
2657 /* XXX : not implemented */
2658 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2659 SPR_NOACCESS, SPR_NOACCESS,
2660 &spr_read_generic, &spr_write_generic,
2661 0x00000000);
2662 /* XXX : not implemented */
2663 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2664 SPR_NOACCESS, SPR_NOACCESS,
2665 &spr_read_generic, &spr_write_generic,
2666 0x00000000);
2667 /* XXX : not implemented */
2668 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2669 SPR_NOACCESS, SPR_NOACCESS,
2670 &spr_read_generic, &spr_write_generic,
2671 0x00000000);
2672 /* XXX : not implemented */
2673 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2674 SPR_NOACCESS, SPR_NOACCESS,
2675 &spr_read_generic, &spr_write_generic,
2676 0x00000000);
2677 /* XXX : not implemented */
2678 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2679 SPR_NOACCESS, SPR_NOACCESS,
2680 &spr_read_generic, &spr_write_generic,
2681 0x00000000);
2682 }
2683
2684 // XXX: TODO
2685 /*
2686 * AMR => SPR 29 (Power 2.04)
2687 * CTRL => SPR 136 (Power 2.04)
2688 * CTRL => SPR 152 (Power 2.04)
2689 * SCOMC => SPR 276 (64 bits ?)
2690 * SCOMD => SPR 277 (64 bits ?)
2691 * TBU40 => SPR 286 (Power 2.04 hypv)
2692 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2693 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2694 * HDSISR => SPR 306 (Power 2.04 hypv)
2695 * HDAR => SPR 307 (Power 2.04 hypv)
2696 * PURR => SPR 309 (Power 2.04 hypv)
2697 * HDEC => SPR 310 (Power 2.04 hypv)
2698 * HIOR => SPR 311 (hypv)
2699 * RMOR => SPR 312 (970)
2700 * HRMOR => SPR 313 (Power 2.04 hypv)
2701 * HSRR0 => SPR 314 (Power 2.04 hypv)
2702 * HSRR1 => SPR 315 (Power 2.04 hypv)
2703 * LPIDR => SPR 317 (970)
2704 * EPR => SPR 702 (Power 2.04 emb)
2705 * perf => 768-783 (Power 2.04)
2706 * perf => 784-799 (Power 2.04)
2707 * PPR => SPR 896 (Power 2.04)
2708 * EPLC => SPR 947 (Power 2.04 emb)
2709 * EPSC => SPR 948 (Power 2.04 emb)
2710 * DABRX => 1015 (Power 2.04 hypv)
2711 * FPECR => SPR 1022 (?)
2712 * ... and more (thermal management, performance counters, ...)
2713 */
2714
2715 /*****************************************************************************/
2716 /* Exception vectors models */
2717 static void init_excp_4xx_real (CPUPPCState *env)
2718 {
2719 #if !defined(CONFIG_USER_ONLY)
2720 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2721 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2722 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2723 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2724 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2725 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2726 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2727 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2728 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2729 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2730 env->ivor_mask = 0x0000FFF0UL;
2731 env->ivpr_mask = 0xFFFF0000UL;
2732 /* Hardware reset vector */
2733 env->hreset_vector = 0xFFFFFFFCUL;
2734 #endif
2735 }
2736
2737 static void init_excp_4xx_softmmu (CPUPPCState *env)
2738 {
2739 #if !defined(CONFIG_USER_ONLY)
2740 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2741 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2742 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2743 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2744 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2745 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2746 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2747 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2748 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2749 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2750 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2751 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2752 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2753 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2754 env->ivor_mask = 0x0000FFF0UL;
2755 env->ivpr_mask = 0xFFFF0000UL;
2756 /* Hardware reset vector */
2757 env->hreset_vector = 0xFFFFFFFCUL;
2758 #endif
2759 }
2760
2761 static void init_excp_MPC5xx (CPUPPCState *env)
2762 {
2763 #if !defined(CONFIG_USER_ONLY)
2764 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2765 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2766 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2767 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2768 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2769 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2770 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2771 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2772 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2773 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2774 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2775 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2776 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2777 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2778 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2779 env->ivor_mask = 0x0000FFF0UL;
2780 env->ivpr_mask = 0xFFFF0000UL;
2781 /* Hardware reset vector */
2782 env->hreset_vector = 0x00000100UL;
2783 #endif
2784 }
2785
2786 static void init_excp_MPC8xx (CPUPPCState *env)
2787 {
2788 #if !defined(CONFIG_USER_ONLY)
2789 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2790 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2791 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2792 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2793 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2794 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2795 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2796 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2797 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2798 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2799 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2800 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2801 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2802 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2803 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2804 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2805 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2806 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2807 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2808 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2809 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2810 env->ivor_mask = 0x0000FFF0UL;
2811 env->ivpr_mask = 0xFFFF0000UL;
2812 /* Hardware reset vector */
2813 env->hreset_vector = 0x00000100UL;
2814 #endif
2815 }
2816
2817 static void init_excp_G2 (CPUPPCState *env)
2818 {
2819 #if !defined(CONFIG_USER_ONLY)
2820 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2821 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2822 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2823 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2824 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2825 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2826 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2827 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2828 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2829 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2830 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2831 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2832 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2833 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2834 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2835 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2836 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2837 /* Hardware reset vector */
2838 env->hreset_vector = 0x00000100UL;
2839 #endif
2840 }
2841
2842 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2843 {
2844 #if !defined(CONFIG_USER_ONLY)
2845 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2846 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2847 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2848 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2849 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2850 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2851 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2852 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2853 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2854 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2855 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2856 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2857 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2858 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2859 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2860 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2861 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2862 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2863 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2864 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2865 env->ivor_mask = 0x0000FFF7UL;
2866 env->ivpr_mask = ivpr_mask;
2867 /* Hardware reset vector */
2868 env->hreset_vector = 0xFFFFFFFCUL;
2869 #endif
2870 }
2871
2872 static void init_excp_BookE (CPUPPCState *env)
2873 {
2874 #if !defined(CONFIG_USER_ONLY)
2875 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2876 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2877 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2878 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2879 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2880 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2881 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2882 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2883 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2884 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2885 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2886 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2887 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2888 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2889 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2890 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2891 env->ivor_mask = 0x0000FFF0UL;
2892 env->ivpr_mask = 0xFFFF0000UL;
2893 /* Hardware reset vector */
2894 env->hreset_vector = 0xFFFFFFFCUL;
2895 #endif
2896 }
2897
2898 static void init_excp_601 (CPUPPCState *env)
2899 {
2900 #if !defined(CONFIG_USER_ONLY)
2901 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2902 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2903 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2904 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2905 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2906 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2907 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2908 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2909 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2910 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2911 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2912 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2913 /* Hardware reset vector */
2914 env->hreset_vector = 0x00000100UL;
2915 #endif
2916 }
2917
2918 static void init_excp_602 (CPUPPCState *env)
2919 {
2920 #if !defined(CONFIG_USER_ONLY)
2921 /* XXX: exception prefix has a special behavior on 602 */
2922 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2923 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2924 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2925 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2926 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2927 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2928 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2929 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2930 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2931 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2932 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2933 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2934 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2935 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2936 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2937 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2938 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2939 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2940 /* Hardware reset vector */
2941 env->hreset_vector = 0x00000100UL;
2942 #endif
2943 }
2944
2945 static void init_excp_603 (CPUPPCState *env)
2946 {
2947 #if !defined(CONFIG_USER_ONLY)
2948 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2949 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2950 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2951 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2952 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2953 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2954 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2955 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2956 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2957 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2958 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2959 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2960 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2961 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2962 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2963 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2964 /* Hardware reset vector */
2965 env->hreset_vector = 0x00000100UL;
2966 #endif
2967 }
2968
2969 static void init_excp_604 (CPUPPCState *env)
2970 {
2971 #if !defined(CONFIG_USER_ONLY)
2972 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2973 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2974 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2975 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2976 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2977 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2978 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2979 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2980 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2981 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2982 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2983 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2984 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2985 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2986 /* Hardware reset vector */
2987 env->hreset_vector = 0x00000100UL;
2988 #endif
2989 }
2990
2991 static void init_excp_7x0 (CPUPPCState *env)
2992 {
2993 #if !defined(CONFIG_USER_ONLY)
2994 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2995 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2996 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2997 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2998 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2999 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3000 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3001 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3002 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3003 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3004 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3005 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3006 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3007 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3008 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3009 /* Hardware reset vector */
3010 env->hreset_vector = 0x00000100UL;
3011 #endif
3012 }
3013
3014 static void init_excp_750cl (CPUPPCState *env)
3015 {
3016 #if !defined(CONFIG_USER_ONLY)
3017 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3018 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3019 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3020 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3021 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3022 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3023 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3024 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3025 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3026 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3027 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3028 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3029 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3030 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3031 /* Hardware reset vector */
3032 env->hreset_vector = 0x00000100UL;
3033 #endif
3034 }
3035
3036 static void init_excp_750cx (CPUPPCState *env)
3037 {
3038 #if !defined(CONFIG_USER_ONLY)
3039 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3040 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3041 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3042 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3043 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3044 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3045 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3046 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3047 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3048 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3049 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3050 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3051 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3052 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3053 /* Hardware reset vector */
3054 env->hreset_vector = 0x00000100UL;
3055 #endif
3056 }
3057
3058 /* XXX: Check if this is correct */
3059 static void init_excp_7x5 (CPUPPCState *env)
3060 {
3061 #if !defined(CONFIG_USER_ONLY)
3062 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3063 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3064 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3065 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3066 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3067 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3068 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3069 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3070 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3071 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3072 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3073 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3074 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3075 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3076 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3077 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3078 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3079 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3080 /* Hardware reset vector */
3081 env->hreset_vector = 0x00000100UL;
3082 #endif
3083 }
3084
3085 static void init_excp_7400 (CPUPPCState *env)
3086 {
3087 #if !defined(CONFIG_USER_ONLY)
3088 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3089 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3090 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3091 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3092 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3093 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3094 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3095 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3096 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3097 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3098 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3099 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3100 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3101 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3102 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3103 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3104 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3105 /* Hardware reset vector */
3106 env->hreset_vector = 0x00000100UL;
3107 #endif
3108 }
3109
3110 static void init_excp_7450 (CPUPPCState *env)
3111 {
3112 #if !defined(CONFIG_USER_ONLY)
3113 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3114 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3115 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3116 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3117 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3118 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3119 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3120 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3121 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3122 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3123 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3124 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3125 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3126 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3127 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3128 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3129 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3130 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3131 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3132 /* Hardware reset vector */
3133 env->hreset_vector = 0x00000100UL;
3134 #endif
3135 }
3136
3137 #if defined (TARGET_PPC64)
3138 static void init_excp_970 (CPUPPCState *env)
3139 {
3140 #if !defined(CONFIG_USER_ONLY)
3141 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3142 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3143 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3144 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3145 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3146 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3147 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3148 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3149 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3150 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3151 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3152 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3153 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3154 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3155 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3156 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3157 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3158 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3159 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3160 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3161 /* Hardware reset vector */
3162 env->hreset_vector = 0x0000000000000100ULL;
3163 #endif
3164 }
3165
3166 static void init_excp_POWER7 (CPUPPCState *env)
3167 {
3168 #if !defined(CONFIG_USER_ONLY)
3169 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3170 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3171 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3172 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3173 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3174 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3175 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3176 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3177 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3178 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3179 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3180 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3181 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3182 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3183 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3184 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3185 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
3186 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
3187 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3188 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3189 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3190 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3191 /* Hardware reset vector */
3192 env->hreset_vector = 0x0000000000000100ULL;
3193 #endif
3194 }
3195 #endif
3196
3197 /*****************************************************************************/
3198 /* Power management enable checks */
3199 static int check_pow_none (CPUPPCState *env)
3200 {
3201 return 0;
3202 }
3203
3204 static int check_pow_nocheck (CPUPPCState *env)
3205 {
3206 return 1;
3207 }
3208
3209 static int check_pow_hid0 (CPUPPCState *env)
3210 {
3211 if (env->spr[SPR_HID0] & 0x00E00000)
3212 return 1;
3213
3214 return 0;
3215 }
3216
3217 static int check_pow_hid0_74xx (CPUPPCState *env)
3218 {
3219 if (env->spr[SPR_HID0] & 0x00600000)
3220 return 1;
3221
3222 return 0;
3223 }
3224
3225 static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu)
3226 {
3227 return true;
3228 }
3229
3230 #ifdef TARGET_PPC64
3231 static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
3232 {
3233 return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
3234 }
3235 #endif
3236
3237 /*****************************************************************************/
3238 /* PowerPC implementations definitions */
3239
3240 #define POWERPC_FAMILY(_name) \
3241 static void \
3242 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3243 \
3244 static const TypeInfo \
3245 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3246 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3247 .parent = TYPE_POWERPC_CPU, \
3248 .abstract = true, \
3249 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3250 }; \
3251 \
3252 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3253 { \
3254 type_register_static( \
3255 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3256 } \
3257 \
3258 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3259 \
3260 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3261
3262 static void init_proc_401 (CPUPPCState *env)
3263 {
3264 gen_spr_40x(env);
3265 gen_spr_401_403(env);
3266 gen_spr_401(env);
3267 init_excp_4xx_real(env);
3268 env->dcache_line_size = 32;
3269 env->icache_line_size = 32;
3270 /* Allocate hardware IRQ controller */
3271 ppc40x_irq_init(ppc_env_get_cpu(env));
3272
3273 SET_FIT_PERIOD(12, 16, 20, 24);
3274 SET_WDT_PERIOD(16, 20, 24, 28);
3275 }
3276
3277 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3278 {
3279 DeviceClass *dc = DEVICE_CLASS(oc);
3280 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3281
3282 dc->desc = "PowerPC 401";
3283 pcc->init_proc = init_proc_401;
3284 pcc->check_pow = check_pow_nocheck;
3285 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3286 PPC_WRTEE | PPC_DCR |
3287 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3288 PPC_CACHE_DCBZ |
3289 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3290 PPC_4xx_COMMON | PPC_40x_EXCP;
3291 pcc->msr_mask = (1ull << MSR_KEY) |
3292 (1ull << MSR_POW) |
3293 (1ull << MSR_CE) |
3294 (1ull << MSR_ILE) |
3295 (1ull << MSR_EE) |
3296 (1ull << MSR_PR) |
3297 (1ull << MSR_ME) |
3298 (1ull << MSR_DE) |
3299 (1ull << MSR_LE);
3300 pcc->mmu_model = POWERPC_MMU_REAL;
3301 pcc->excp_model = POWERPC_EXCP_40x;
3302 pcc->bus_model = PPC_FLAGS_INPUT_401;
3303 pcc->bfd_mach = bfd_mach_ppc_403;
3304 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3305 POWERPC_FLAG_BUS_CLK;
3306 }
3307
3308 static void init_proc_401x2 (CPUPPCState *env)
3309 {
3310 gen_spr_40x(env);
3311 gen_spr_401_403(env);
3312 gen_spr_401x2(env);
3313 gen_spr_compress(env);
3314 /* Memory management */
3315 #if !defined(CONFIG_USER_ONLY)
3316 env->nb_tlb = 64;
3317 env->nb_ways = 1;
3318 env->id_tlbs = 0;
3319 env->tlb_type = TLB_EMB;
3320 #endif
3321 init_excp_4xx_softmmu(env);
3322 env->dcache_line_size = 32;
3323 env->icache_line_size = 32;
3324 /* Allocate hardware IRQ controller */
3325 ppc40x_irq_init(ppc_env_get_cpu(env));
3326
3327 SET_FIT_PERIOD(12, 16, 20, 24);
3328 SET_WDT_PERIOD(16, 20, 24, 28);
3329 }
3330
3331 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3332 {
3333 DeviceClass *dc = DEVICE_CLASS(oc);
3334 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3335
3336 dc->desc = "PowerPC 401x2";
3337 pcc->init_proc = init_proc_401x2;
3338 pcc->check_pow = check_pow_nocheck;
3339 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3340 PPC_DCR | PPC_WRTEE |
3341 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3342 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3343 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3344 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3345 PPC_4xx_COMMON | PPC_40x_EXCP;
3346 pcc->msr_mask = (1ull << 20) |
3347 (1ull << MSR_KEY) |
3348 (1ull << MSR_POW) |
3349 (1ull << MSR_CE) |
3350 (1ull << MSR_ILE) |
3351 (1ull << MSR_EE) |
3352 (1ull << MSR_PR) |
3353 (1ull << MSR_ME) |
3354 (1ull << MSR_DE) |
3355 (1ull << MSR_IR) |
3356 (1ull << MSR_DR) |
3357 (1ull << MSR_LE);
3358 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3359 pcc->excp_model = POWERPC_EXCP_40x;
3360 pcc->bus_model = PPC_FLAGS_INPUT_401;
3361 pcc->bfd_mach = bfd_mach_ppc_403;
3362 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3363 POWERPC_FLAG_BUS_CLK;
3364 }
3365
3366 static void init_proc_401x3 (CPUPPCState *env)
3367 {
3368 gen_spr_40x(env);
3369 gen_spr_401_403(env);
3370 gen_spr_401(env);
3371 gen_spr_401x2(env);
3372 gen_spr_compress(env);
3373 init_excp_4xx_softmmu(env);
3374 env->dcache_line_size = 32;
3375 env->icache_line_size = 32;
3376 /* Allocate hardware IRQ controller */
3377 ppc40x_irq_init(ppc_env_get_cpu(env));
3378
3379 SET_FIT_PERIOD(12, 16, 20, 24);
3380 SET_WDT_PERIOD(16, 20, 24, 28);
3381 }
3382
3383 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3384 {
3385 DeviceClass *dc = DEVICE_CLASS(oc);
3386 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3387
3388 dc->desc = "PowerPC 401x3";
3389 pcc->init_proc = init_proc_401x3;
3390 pcc->check_pow = check_pow_nocheck;
3391 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3392 PPC_DCR | PPC_WRTEE |
3393 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3394 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3395 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3396 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3397 PPC_4xx_COMMON | PPC_40x_EXCP;
3398 pcc->msr_mask = (1ull << 20) |
3399 (1ull << MSR_KEY) |
3400 (1ull << MSR_POW) |
3401 (1ull << MSR_CE) |
3402 (1ull << MSR_ILE) |
3403 (1ull << MSR_EE) |
3404 (1ull << MSR_PR) |
3405 (1ull << MSR_ME) |
3406 (1ull << MSR_DWE) |
3407 (1ull << MSR_DE) |
3408 (1ull << MSR_IR) |
3409 (1ull << MSR_DR) |
3410 (1ull << MSR_LE);
3411 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3412 pcc->excp_model = POWERPC_EXCP_40x;
3413 pcc->bus_model = PPC_FLAGS_INPUT_401;
3414 pcc->bfd_mach = bfd_mach_ppc_403;
3415 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3416 POWERPC_FLAG_BUS_CLK;
3417 }
3418
3419 static void init_proc_IOP480 (CPUPPCState *env)
3420 {
3421 gen_spr_40x(env);
3422 gen_spr_401_403(env);
3423 gen_spr_401x2(env);
3424 gen_spr_compress(env);
3425 /* Memory management */
3426 #if !defined(CONFIG_USER_ONLY)
3427 env->nb_tlb = 64;
3428 env->nb_ways = 1;
3429 env->id_tlbs = 0;
3430 env->tlb_type = TLB_EMB;
3431 #endif
3432 init_excp_4xx_softmmu(env);
3433 env->dcache_line_size = 32;
3434 env->icache_line_size = 32;
3435 /* Allocate hardware IRQ controller */
3436 ppc40x_irq_init(ppc_env_get_cpu(env));
3437
3438 SET_FIT_PERIOD(8, 12, 16, 20);
3439 SET_WDT_PERIOD(16, 20, 24, 28);
3440 }
3441
3442 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3443 {
3444 DeviceClass *dc = DEVICE_CLASS(oc);
3445 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3446
3447 dc->desc = "IOP480";
3448 pcc->init_proc = init_proc_IOP480;
3449 pcc->check_pow = check_pow_nocheck;
3450 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3451 PPC_DCR | PPC_WRTEE |
3452 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3453 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3454 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3455 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3456 PPC_4xx_COMMON | PPC_40x_EXCP;
3457 pcc->msr_mask = (1ull << 20) |
3458 (1ull << MSR_KEY) |
3459 (1ull << MSR_POW) |
3460 (1ull << MSR_CE) |
3461 (1ull << MSR_ILE) |
3462 (1ull << MSR_EE) |
3463 (1ull << MSR_PR) |
3464 (1ull << MSR_ME) |
3465 (1ull << MSR_DE) |
3466 (1ull << MSR_IR) |
3467 (1ull << MSR_DR) |
3468 (1ull << MSR_LE);
3469 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3470 pcc->excp_model = POWERPC_EXCP_40x;
3471 pcc->bus_model = PPC_FLAGS_INPUT_401;
3472 pcc->bfd_mach = bfd_mach_ppc_403;
3473 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3474 POWERPC_FLAG_BUS_CLK;
3475 }
3476
3477 static void init_proc_403 (CPUPPCState *env)
3478 {
3479 gen_spr_40x(env);
3480 gen_spr_401_403(env);
3481 gen_spr_403(env);
3482 gen_spr_403_real(env);
3483 init_excp_4xx_real(env);
3484 env->dcache_line_size = 32;
3485 env->icache_line_size = 32;
3486 /* Allocate hardware IRQ controller */
3487 ppc40x_irq_init(ppc_env_get_cpu(env));
3488
3489 SET_FIT_PERIOD(8, 12, 16, 20);
3490 SET_WDT_PERIOD(16, 20, 24, 28);
3491 }
3492
3493 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3494 {
3495 DeviceClass *dc = DEVICE_CLASS(oc);
3496 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3497
3498 dc->desc = "PowerPC 403";
3499 pcc->init_proc = init_proc_403;
3500 pcc->check_pow = check_pow_nocheck;
3501 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3502 PPC_DCR | PPC_WRTEE |
3503 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3504 PPC_CACHE_DCBZ |
3505 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3506 PPC_4xx_COMMON | PPC_40x_EXCP;
3507 pcc->msr_mask = (1ull << MSR_POW) |
3508 (1ull << MSR_CE) |
3509 (1ull << MSR_ILE) |
3510 (1ull << MSR_EE) |
3511 (1ull << MSR_PR) |
3512 (1ull << MSR_ME) |
3513 (1ull << MSR_PE) |
3514 (1ull << MSR_PX) |
3515 (1ull << MSR_LE);
3516 pcc->mmu_model = POWERPC_MMU_REAL;
3517 pcc->excp_model = POWERPC_EXCP_40x;
3518 pcc->bus_model = PPC_FLAGS_INPUT_401;
3519 pcc->bfd_mach = bfd_mach_ppc_403;
3520 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3521 POWERPC_FLAG_BUS_CLK;
3522 }
3523
3524 static void init_proc_403GCX (CPUPPCState *env)
3525 {
3526 gen_spr_40x(env);
3527 gen_spr_401_403(env);
3528 gen_spr_403(env);
3529 gen_spr_403_real(env);
3530 gen_spr_403_mmu(env);
3531 /* Bus access control */
3532 /* not emulated, as QEMU never does speculative access */
3533 spr_register(env, SPR_40x_SGR, "SGR",
3534 SPR_NOACCESS, SPR_NOACCESS,
3535 &spr_read_generic, &spr_write_generic,
3536 0xFFFFFFFF);
3537 /* not emulated, as QEMU do not emulate caches */
3538 spr_register(env, SPR_40x_DCWR, "DCWR",
3539 SPR_NOACCESS, SPR_NOACCESS,
3540 &spr_read_generic, &spr_write_generic,
3541 0x00000000);
3542 /* Memory management */
3543 #if !defined(CONFIG_USER_ONLY)
3544 env->nb_tlb = 64;
3545 env->nb_ways = 1;
3546 env->id_tlbs = 0;
3547 env->tlb_type = TLB_EMB;
3548 #endif
3549 init_excp_4xx_softmmu(env);
3550 env->dcache_line_size = 32;
3551 env->icache_line_size = 32;
3552 /* Allocate hardware IRQ controller */
3553 ppc40x_irq_init(ppc_env_get_cpu(env));
3554
3555 SET_FIT_PERIOD(8, 12, 16, 20);
3556 SET_WDT_PERIOD(16, 20, 24, 28);
3557 }
3558
3559 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3560 {
3561 DeviceClass *dc = DEVICE_CLASS(oc);
3562 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3563
3564 dc->desc = "PowerPC 403 GCX";
3565 pcc->init_proc = init_proc_403GCX;
3566 pcc->check_pow = check_pow_nocheck;
3567 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3568 PPC_DCR | PPC_WRTEE |
3569 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3570 PPC_CACHE_DCBZ |
3571 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3572 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3573 PPC_4xx_COMMON | PPC_40x_EXCP;
3574 pcc->msr_mask = (1ull << MSR_POW) |
3575 (1ull << MSR_CE) |
3576 (1ull << MSR_ILE) |
3577 (1ull << MSR_EE) |
3578 (1ull << MSR_PR) |
3579 (1ull << MSR_ME) |
3580 (1ull << MSR_PE) |
3581 (1ull << MSR_PX) |
3582 (1ull << MSR_LE);
3583 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3584 pcc->excp_model = POWERPC_EXCP_40x;
3585 pcc->bus_model = PPC_FLAGS_INPUT_401;
3586 pcc->bfd_mach = bfd_mach_ppc_403;
3587 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3588 POWERPC_FLAG_BUS_CLK;
3589 }
3590
3591 static void init_proc_405 (CPUPPCState *env)
3592 {
3593 /* Time base */
3594 gen_tbl(env);
3595 gen_spr_40x(env);
3596 gen_spr_405(env);
3597 /* Bus access control */
3598 /* not emulated, as QEMU never does speculative access */
3599 spr_register(env, SPR_40x_SGR, "SGR",
3600 SPR_NOACCESS, SPR_NOACCESS,
3601 &spr_read_generic, &spr_write_generic,
3602 0xFFFFFFFF);
3603 /* not emulated, as QEMU do not emulate caches */
3604 spr_register(env, SPR_40x_DCWR, "DCWR",
3605 SPR_NOACCESS, SPR_NOACCESS,
3606 &spr_read_generic, &spr_write_generic,
3607 0x00000000);
3608 /* Memory management */
3609 #if !defined(CONFIG_USER_ONLY)
3610 env->nb_tlb = 64;
3611 env->nb_ways = 1;
3612 env->id_tlbs = 0;
3613 env->tlb_type = TLB_EMB;
3614 #endif
3615 init_excp_4xx_softmmu(env);
3616 env->dcache_line_size = 32;
3617 env->icache_line_size = 32;
3618 /* Allocate hardware IRQ controller */
3619 ppc40x_irq_init(ppc_env_get_cpu(env));
3620
3621 SET_FIT_PERIOD(8, 12, 16, 20);
3622 SET_WDT_PERIOD(16, 20, 24, 28);
3623 }
3624
3625 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3626 {
3627 DeviceClass *dc = DEVICE_CLASS(oc);
3628 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3629
3630 dc->desc = "PowerPC 405";
3631 pcc->init_proc = init_proc_405;
3632 pcc->check_pow = check_pow_nocheck;
3633 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3634 PPC_DCR | PPC_WRTEE |
3635 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3636 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3637 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3638 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3639 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3640 pcc->msr_mask = (1ull << MSR_POW) |
3641 (1ull << MSR_CE) |
3642 (1ull << MSR_EE) |
3643 (1ull << MSR_PR) |
3644 (1ull << MSR_FP) |
3645 (1ull << MSR_DWE) |
3646 (1ull << MSR_DE) |
3647 (1ull << MSR_IR) |
3648 (1ull << MSR_DR);
3649 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3650 pcc->excp_model = POWERPC_EXCP_40x;
3651 pcc->bus_model = PPC_FLAGS_INPUT_405;
3652 pcc->bfd_mach = bfd_mach_ppc_403;
3653 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3654 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3655 }
3656
3657 static void init_proc_440EP (CPUPPCState *env)
3658 {
3659 /* Time base */
3660 gen_tbl(env);
3661 gen_spr_BookE(env, 0x000000000000FFFFULL);
3662 gen_spr_440(env);
3663 gen_spr_usprgh(env);
3664 /* Processor identification */
3665 spr_register(env, SPR_BOOKE_PIR, "PIR",
3666 SPR_NOACCESS, SPR_NOACCESS,
3667 &spr_read_generic, &spr_write_pir,
3668 0x00000000);
3669 /* XXX : not implemented */
3670 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3671 SPR_NOACCESS, SPR_NOACCESS,
3672 &spr_read_generic, &spr_write_generic,
3673 0x00000000);
3674 /* XXX : not implemented */
3675 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3676 SPR_NOACCESS, SPR_NOACCESS,
3677 &spr_read_generic, &spr_write_generic,
3678 0x00000000);
3679 /* XXX : not implemented */
3680 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3681 SPR_NOACCESS, SPR_NOACCESS,
3682 &spr_read_generic, &spr_write_generic,
3683 0x00000000);
3684 /* XXX : not implemented */
3685 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3686 SPR_NOACCESS, SPR_NOACCESS,
3687 &spr_read_generic, &spr_write_generic,
3688 0x00000000);
3689 /* XXX : not implemented */
3690 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3691 SPR_NOACCESS, SPR_NOACCESS,
3692 &spr_read_generic, &spr_write_generic,
3693 0x00000000);
3694 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3695 SPR_NOACCESS, SPR_NOACCESS,
3696 &spr_read_generic, &spr_write_generic,
3697 0x00000000);
3698 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3699 SPR_NOACCESS, SPR_NOACCESS,
3700 &spr_read_generic, &spr_write_generic,
3701 0x00000000);
3702 /* XXX : not implemented */
3703 spr_register(env, SPR_440_CCR1, "CCR1",
3704 SPR_NOACCESS, SPR_NOACCESS,
3705 &spr_read_generic, &spr_write_generic,
3706 0x00000000);
3707 /* Memory management */
3708 #if !defined(CONFIG_USER_ONLY)
3709 env->nb_tlb = 64;
3710 env->nb_ways = 1;
3711 env->id_tlbs = 0;
3712 env->tlb_type = TLB_EMB;
3713 #endif
3714 init_excp_BookE(env);
3715 env->dcache_line_size = 32;
3716 env->icache_line_size = 32;
3717 ppc40x_irq_init(ppc_env_get_cpu(env));
3718
3719 SET_FIT_PERIOD(12, 16, 20, 24);
3720 SET_WDT_PERIOD(20, 24, 28, 32);
3721 }
3722
3723 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3724 {
3725 DeviceClass *dc = DEVICE_CLASS(oc);
3726 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3727
3728 dc->desc = "PowerPC 440 EP";
3729 pcc->init_proc = init_proc_440EP;
3730 pcc->check_pow = check_pow_nocheck;
3731 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3732 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3733 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3734 PPC_FLOAT_STFIWX |
3735 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3736 PPC_CACHE | PPC_CACHE_ICBI |
3737 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3738 PPC_MEM_TLBSYNC | PPC_MFTB |
3739 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3740 PPC_440_SPEC;
3741 pcc->msr_mask = (1ull << MSR_POW) |
3742 (1ull << MSR_CE) |
3743 (1ull << MSR_EE) |
3744 (1ull << MSR_PR) |
3745 (1ull << MSR_FP) |
3746 (1ull << MSR_ME) |
3747 (1ull << MSR_FE0) |
3748 (1ull << MSR_DWE) |
3749 (1ull << MSR_DE) |
3750 (1ull << MSR_FE1) |
3751 (1ull << MSR_IR) |
3752 (1ull << MSR_DR);
3753 pcc->mmu_model = POWERPC_MMU_BOOKE;
3754 pcc->excp_model = POWERPC_EXCP_BOOKE;
3755 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3756 pcc->bfd_mach = bfd_mach_ppc_403;
3757 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3758 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3759 }
3760
3761 static void init_proc_440GP (CPUPPCState *env)
3762 {
3763 /* Time base */
3764 gen_tbl(env);
3765 gen_spr_BookE(env, 0x000000000000FFFFULL);
3766 gen_spr_440(env);
3767 gen_spr_usprgh(env);
3768 /* Processor identification */
3769 spr_register(env, SPR_BOOKE_PIR, "PIR",
3770 SPR_NOACCESS, SPR_NOACCESS,
3771 &spr_read_generic, &spr_write_pir,
3772 0x00000000);
3773 /* XXX : not implemented */
3774 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3775 SPR_NOACCESS, SPR_NOACCESS,
3776 &spr_read_generic, &spr_write_generic,
3777 0x00000000);
3778 /* XXX : not implemented */
3779 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3780 SPR_NOACCESS, SPR_NOACCESS,
3781 &spr_read_generic, &spr_write_generic,
3782 0x00000000);
3783 /* XXX : not implemented */
3784 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3785 SPR_NOACCESS, SPR_NOACCESS,
3786 &spr_read_generic, &spr_write_generic,
3787 0x00000000);
3788 /* XXX : not implemented */
3789 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3790 SPR_NOACCESS, SPR_NOACCESS,
3791 &spr_read_generic, &spr_write_generic,
3792 0x00000000);
3793 /* Memory management */
3794 #if !defined(CONFIG_USER_ONLY)
3795 env->nb_tlb = 64;
3796 env->nb_ways = 1;
3797 env->id_tlbs = 0;
3798 env->tlb_type = TLB_EMB;
3799 #endif
3800 init_excp_BookE(env);
3801 env->dcache_line_size = 32;
3802 env->icache_line_size = 32;
3803 /* XXX: TODO: allocate internal IRQ controller */
3804
3805 SET_FIT_PERIOD(12, 16, 20, 24);
3806 SET_WDT_PERIOD(20, 24, 28, 32);
3807 }
3808
3809 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3810 {
3811 DeviceClass *dc = DEVICE_CLASS(oc);
3812 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3813
3814 dc->desc = "PowerPC 440 GP";
3815 pcc->init_proc = init_proc_440GP;
3816 pcc->check_pow = check_pow_nocheck;
3817 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3818 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3819 PPC_CACHE | PPC_CACHE_ICBI |
3820 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3821 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3822 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3823 PPC_440_SPEC;
3824 pcc->msr_mask = (1ull << MSR_POW) |
3825 (1ull << MSR_CE) |
3826 (1ull << MSR_EE) |
3827 (1ull << MSR_PR) |
3828 (1ull << MSR_FP) |
3829 (1ull << MSR_ME) |
3830 (1ull << MSR_FE0) |
3831 (1ull << MSR_DWE) |
3832 (1ull << MSR_DE) |
3833 (1ull << MSR_FE1) |
3834 (1ull << MSR_IR) |
3835 (1ull << MSR_DR);
3836 pcc->mmu_model = POWERPC_MMU_BOOKE;
3837 pcc->excp_model = POWERPC_EXCP_BOOKE;
3838 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3839 pcc->bfd_mach = bfd_mach_ppc_403;
3840 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3841 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3842 }
3843
3844 static void init_proc_440x4 (CPUPPCState *env)
3845 {
3846 /* Time base */
3847 gen_tbl(env);
3848 gen_spr_BookE(env, 0x000000000000FFFFULL);
3849 gen_spr_440(env);
3850 gen_spr_usprgh(env);
3851 /* Processor identification */
3852 spr_register(env, SPR_BOOKE_PIR, "PIR",
3853 SPR_NOACCESS, SPR_NOACCESS,
3854 &spr_read_generic, &spr_write_pir,
3855 0x00000000);
3856 /* XXX : not implemented */
3857 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3858 SPR_NOACCESS, SPR_NOACCESS,
3859 &spr_read_generic, &spr_write_generic,
3860 0x00000000);
3861 /* XXX : not implemented */
3862 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3863 SPR_NOACCESS, SPR_NOACCESS,
3864 &spr_read_generic, &spr_write_generic,
3865 0x00000000);
3866 /* XXX : not implemented */
3867 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3868 SPR_NOACCESS, SPR_NOACCESS,
3869 &spr_read_generic, &spr_write_generic,
3870 0x00000000);
3871 /* XXX : not implemented */
3872 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3873 SPR_NOACCESS, SPR_NOACCESS,
3874 &spr_read_generic, &spr_write_generic,
3875 0x00000000);
3876 /* Memory management */
3877 #if !defined(CONFIG_USER_ONLY)
3878 env->nb_tlb = 64;
3879 env->nb_ways = 1;
3880 env->id_tlbs = 0;
3881 env->tlb_type = TLB_EMB;
3882 #endif
3883 init_excp_BookE(env);
3884 env->dcache_line_size = 32;
3885 env->icache_line_size = 32;
3886 /* XXX: TODO: allocate internal IRQ controller */
3887
3888 SET_FIT_PERIOD(12, 16, 20, 24);
3889 SET_WDT_PERIOD(20, 24, 28, 32);
3890 }
3891
3892 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3893 {
3894 DeviceClass *dc = DEVICE_CLASS(oc);
3895 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3896
3897 dc->desc = "PowerPC 440x4";
3898 pcc->init_proc = init_proc_440x4;
3899 pcc->check_pow = check_pow_nocheck;
3900 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3901 PPC_DCR | PPC_WRTEE |
3902 PPC_CACHE | PPC_CACHE_ICBI |
3903 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3904 PPC_MEM_TLBSYNC | PPC_MFTB |
3905 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3906 PPC_440_SPEC;
3907 pcc->msr_mask = (1ull << MSR_POW) |
3908 (1ull << MSR_CE) |
3909 (1ull << MSR_EE) |
3910 (1ull << MSR_PR) |
3911 (1ull << MSR_FP) |
3912 (1ull << MSR_ME) |
3913 (1ull << MSR_FE0) |
3914 (1ull << MSR_DWE) |
3915 (1ull << MSR_DE) |
3916 (1ull << MSR_FE1) |
3917 (1ull << MSR_IR) |
3918 (1ull << MSR_DR);
3919 pcc->mmu_model = POWERPC_MMU_BOOKE;
3920 pcc->excp_model = POWERPC_EXCP_BOOKE;
3921 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3922 pcc->bfd_mach = bfd_mach_ppc_403;
3923 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3924 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3925 }
3926
3927 static void init_proc_440x5 (CPUPPCState *env)
3928 {
3929 /* Time base */
3930 gen_tbl(env);
3931 gen_spr_BookE(env, 0x000000000000FFFFULL);
3932 gen_spr_440(env);
3933 gen_spr_usprgh(env);
3934 /* Processor identification */
3935 spr_register(env, SPR_BOOKE_PIR, "PIR",
3936 SPR_NOACCESS, SPR_NOACCESS,
3937 &spr_read_generic, &spr_write_pir,
3938 0x00000000);
3939 /* XXX : not implemented */
3940 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3941 SPR_NOACCESS, SPR_NOACCESS,
3942 &spr_read_generic, &spr_write_generic,
3943 0x00000000);
3944 /* XXX : not implemented */
3945 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3946 SPR_NOACCESS, SPR_NOACCESS,
3947 &spr_read_generic, &spr_write_generic,
3948 0x00000000);
3949 /* XXX : not implemented */
3950 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3951 SPR_NOACCESS, SPR_NOACCESS,
3952 &spr_read_generic, &spr_write_generic,
3953 0x00000000);
3954 /* XXX : not implemented */
3955 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3956 SPR_NOACCESS, SPR_NOACCESS,
3957 &spr_read_generic, &spr_write_generic,
3958 0x00000000);
3959 /* XXX : not implemented */
3960 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3961 SPR_NOACCESS, SPR_NOACCESS,
3962 &spr_read_generic, &spr_write_generic,
3963 0x00000000);
3964 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3965 SPR_NOACCESS, SPR_NOACCESS,
3966 &spr_read_generic, &spr_write_generic,
3967 0x00000000);
3968 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3969 SPR_NOACCESS, SPR_NOACCESS,
3970 &spr_read_generic, &spr_write_generic,
3971 0x00000000);
3972 /* XXX : not implemented */
3973 spr_register(env, SPR_440_CCR1, "CCR1",
3974 SPR_NOACCESS, SPR_NOACCESS,
3975 &spr_read_generic, &spr_write_generic,
3976 0x00000000);
3977 /* Memory management */
3978 #if !defined(CONFIG_USER_ONLY)
3979 env->nb_tlb = 64;
3980 env->nb_ways = 1;
3981 env->id_tlbs = 0;
3982 env->tlb_type = TLB_EMB;
3983 #endif
3984 init_excp_BookE(env);
3985 env->dcache_line_size = 32;
3986 env->icache_line_size = 32;
3987 ppc40x_irq_init(ppc_env_get_cpu(env));
3988
3989 SET_FIT_PERIOD(12, 16, 20, 24);
3990 SET_WDT_PERIOD(20, 24, 28, 32);
3991 }
3992
3993 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3994 {
3995 DeviceClass *dc = DEVICE_CLASS(oc);
3996 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3997
3998 dc->desc = "PowerPC 440x5";
3999 pcc->init_proc = init_proc_440x5;
4000 pcc->check_pow = check_pow_nocheck;
4001 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4002 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4003 PPC_CACHE | PPC_CACHE_ICBI |
4004 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4005 PPC_MEM_TLBSYNC | PPC_MFTB |
4006 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4007 PPC_440_SPEC;
4008 pcc->msr_mask = (1ull << MSR_POW) |
4009 (1ull << MSR_CE) |
4010 (1ull << MSR_EE) |
4011 (1ull << MSR_PR) |
4012 (1ull << MSR_FP) |
4013 (1ull << MSR_ME) |
4014 (1ull << MSR_FE0) |
4015 (1ull << MSR_DWE) |
4016 (1ull << MSR_DE) |
4017 (1ull << MSR_FE1) |
4018 (1ull << MSR_IR) |
4019 (1ull << MSR_DR);
4020 pcc->mmu_model = POWERPC_MMU_BOOKE;
4021 pcc->excp_model = POWERPC_EXCP_BOOKE;
4022 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4023 pcc->bfd_mach = bfd_mach_ppc_403;
4024 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4025 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4026 }
4027
4028 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
4029 {
4030 DeviceClass *dc = DEVICE_CLASS(oc);
4031 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4032
4033 dc->desc = "PowerPC 440x5 with double precision FPU";
4034 pcc->init_proc = init_proc_440x5;
4035 pcc->check_pow = check_pow_nocheck;
4036 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4037 PPC_FLOAT | PPC_FLOAT_FSQRT |
4038 PPC_FLOAT_STFIWX |
4039 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4040 PPC_CACHE | PPC_CACHE_ICBI |
4041 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4042 PPC_MEM_TLBSYNC | PPC_MFTB |
4043 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4044 PPC_440_SPEC;
4045 pcc->insns_flags2 = PPC2_FP_CVT_S64;
4046 pcc->msr_mask = (1ull << MSR_POW) |
4047 (1ull << MSR_CE) |
4048 (1ull << MSR_EE) |
4049 (1ull << MSR_PR) |
4050 (1ull << MSR_FP) |
4051 (1ull << MSR_ME) |
4052 (1ull << MSR_FE0) |
4053 (1ull << MSR_DWE) |
4054 (1ull << MSR_DE) |
4055 (1ull << MSR_FE1) |
4056 (1ull << MSR_IR) |
4057 (1ull << MSR_DR);
4058 pcc->mmu_model = POWERPC_MMU_BOOKE;
4059 pcc->excp_model = POWERPC_EXCP_BOOKE;
4060 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4061 pcc->bfd_mach = bfd_mach_ppc_403;
4062 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4063 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4064 }
4065
4066 static void init_proc_460 (CPUPPCState *env)
4067 {
4068 /* Time base */
4069 gen_tbl(env);
4070 gen_spr_BookE(env, 0x000000000000FFFFULL);
4071 gen_spr_440(env);
4072 gen_spr_usprgh(env);
4073 /* Processor identification */
4074 spr_register(env, SPR_BOOKE_PIR, "PIR",
4075 SPR_NOACCESS, SPR_NOACCESS,
4076 &spr_read_generic, &spr_write_pir,
4077 0x00000000);
4078 /* XXX : not implemented */
4079 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4080 SPR_NOACCESS, SPR_NOACCESS,
4081 &spr_read_generic, &spr_write_generic,
4082 0x00000000);
4083 /* XXX : not implemented */
4084 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4085 SPR_NOACCESS, SPR_NOACCESS,
4086 &spr_read_generic, &spr_write_generic,
4087 0x00000000);
4088 /* XXX : not implemented */
4089 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4090 SPR_NOACCESS, SPR_NOACCESS,
4091 &spr_read_generic, &spr_write_generic,
4092 0x00000000);
4093 /* XXX : not implemented */
4094 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4095 SPR_NOACCESS, SPR_NOACCESS,
4096 &spr_read_generic, &spr_write_generic,
4097 0x00000000);
4098 /* XXX : not implemented */
4099 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4100 SPR_NOACCESS, SPR_NOACCESS,
4101 &spr_read_generic, &spr_write_generic,
4102 0x00000000);
4103 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4104 SPR_NOACCESS, SPR_NOACCESS,
4105 &spr_read_generic, &spr_write_generic,
4106 0x00000000);
4107 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4108 SPR_NOACCESS, SPR_NOACCESS,
4109 &spr_read_generic, &spr_write_generic,
4110 0x00000000);
4111 /* XXX : not implemented */
4112 spr_register(env, SPR_440_CCR1, "CCR1",
4113 SPR_NOACCESS, SPR_NOACCESS,
4114 &spr_read_generic, &spr_write_generic,
4115 0x00000000);
4116 /* XXX : not implemented */
4117 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4118 &spr_read_generic, &spr_write_generic,
4119 &spr_read_generic, &spr_write_generic,
4120 0x00000000);
4121 /* Memory management */
4122 #if !defined(CONFIG_USER_ONLY)
4123 env->nb_tlb = 64;
4124 env->nb_ways = 1;
4125 env->id_tlbs = 0;
4126 env->tlb_type = TLB_EMB;
4127 #endif
4128 init_excp_BookE(env);
4129 env->dcache_line_size = 32;
4130 env->icache_line_size = 32;
4131 /* XXX: TODO: allocate internal IRQ controller */
4132
4133 SET_FIT_PERIOD(12, 16, 20, 24);
4134 SET_WDT_PERIOD(20, 24, 28, 32);
4135 }
4136
4137 POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
4138 {
4139 DeviceClass *dc = DEVICE_CLASS(oc);
4140 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4141
4142 dc->desc = "PowerPC 460 (guessed)";
4143 pcc->init_proc = init_proc_460;
4144 pcc->check_pow = check_pow_nocheck;
4145 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4146 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4147 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
4148 PPC_CACHE | PPC_CACHE_ICBI |
4149 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4150 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4151 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4152 PPC_440_SPEC;
4153 pcc->msr_mask = (1ull << MSR_POW) |
4154 (1ull << MSR_CE) |
4155 (1ull << MSR_EE) |
4156 (1ull << MSR_PR) |
4157 (1ull << MSR_FP) |
4158 (1ull << MSR_ME) |
4159 (1ull << MSR_FE0) |
4160 (1ull << MSR_DWE) |
4161 (1ull << MSR_DE) |
4162 (1ull << MSR_FE1) |
4163 (1ull << MSR_IR) |
4164 (1ull << MSR_DR);
4165 pcc->mmu_model = POWERPC_MMU_BOOKE;
4166 pcc->excp_model = POWERPC_EXCP_BOOKE;
4167 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4168 pcc->bfd_mach = bfd_mach_ppc_403;
4169 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4170 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4171 }
4172
4173 static void init_proc_460F (CPUPPCState *env)
4174 {
4175 /* Time base */
4176 gen_tbl(env);
4177 gen_spr_BookE(env, 0x000000000000FFFFULL);
4178 gen_spr_440(env);
4179 gen_spr_usprgh(env);
4180 /* Processor identification */
4181 spr_register(env, SPR_BOOKE_PIR, "PIR",
4182 SPR_NOACCESS, SPR_NOACCESS,
4183 &spr_read_generic, &spr_write_pir,
4184 0x00000000);
4185 /* XXX : not implemented */
4186 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4187 SPR_NOACCESS, SPR_NOACCESS,
4188 &spr_read_generic, &spr_write_generic,
4189 0x00000000);
4190 /* XXX : not implemented */
4191 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4192 SPR_NOACCESS, SPR_NOACCESS,
4193 &spr_read_generic, &spr_write_generic,
4194 0x00000000);
4195 /* XXX : not implemented */
4196 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4197 SPR_NOACCESS, SPR_NOACCESS,
4198 &spr_read_generic, &spr_write_generic,
4199 0x00000000);
4200 /* XXX : not implemented */
4201 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4202 SPR_NOACCESS, SPR_NOACCESS,
4203 &spr_read_generic, &spr_write_generic,
4204 0x00000000);
4205 /* XXX : not implemented */
4206 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4207 SPR_NOACCESS, SPR_NOACCESS,
4208 &spr_read_generic, &spr_write_generic,
4209 0x00000000);
4210 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4211 SPR_NOACCESS, SPR_NOACCESS,
4212 &spr_read_generic, &spr_write_generic,
4213 0x00000000);
4214 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4215 SPR_NOACCESS, SPR_NOACCESS,
4216 &spr_read_generic, &spr_write_generic,
4217 0x00000000);
4218 /* XXX : not implemented */
4219 spr_register(env, SPR_440_CCR1, "CCR1",
4220 SPR_NOACCESS, SPR_NOACCESS,
4221 &spr_read_generic, &spr_write_generic,
4222 0x00000000);
4223 /* XXX : not implemented */
4224 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4225 &spr_read_generic, &spr_write_generic,
4226 &spr_read_generic, &spr_write_generic,
4227 0x00000000);
4228 /* Memory management */
4229 #if !defined(CONFIG_USER_ONLY)
4230 env->nb_tlb = 64;
4231 env->nb_ways = 1;
4232 env->id_tlbs = 0;
4233 env->tlb_type = TLB_EMB;
4234 #endif
4235 init_excp_BookE(env);
4236 env->dcache_line_size = 32;
4237 env->icache_line_size = 32;
4238 /* XXX: TODO: allocate internal IRQ controller */
4239
4240 SET_FIT_PERIOD(12, 16, 20, 24);
4241 SET_WDT_PERIOD(20, 24, 28, 32);
4242 }
4243
4244 POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
4245 {
4246 DeviceClass *dc = DEVICE_CLASS(oc);
4247 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4248
4249 dc->desc = "PowerPC 460F (guessed)";
4250 pcc->init_proc = init_proc_460F;
4251 pcc->check_pow = check_pow_nocheck;
4252 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4253 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
4254 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4255 PPC_FLOAT_STFIWX | PPC_MFTB |
4256 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4257 PPC_WRTEE | PPC_MFAPIDI |
4258 PPC_CACHE | PPC_CACHE_ICBI |
4259 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4260 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4261 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4262 PPC_440_SPEC;
4263 pcc->msr_mask = (1ull << MSR_POW) |
4264 (1ull << MSR_CE) |
4265 (1ull << MSR_EE) |
4266 (1ull << MSR_PR) |
4267 (1ull << MSR_FP) |
4268 (1ull << MSR_ME) |
4269 (1ull << MSR_FE0) |
4270 (1ull << MSR_DWE) |
4271 (1ull << MSR_DE) |
4272 (1ull << MSR_FE1) |
4273 (1ull << MSR_IR) |
4274 (1ull << MSR_DR);
4275 pcc->mmu_model = POWERPC_MMU_BOOKE;
4276 pcc->excp_model = POWERPC_EXCP_BOOKE;
4277 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4278 pcc->bfd_mach = bfd_mach_ppc_403;
4279 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4280 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4281 }
4282
4283 static void init_proc_MPC5xx (CPUPPCState *env)
4284 {
4285 /* Time base */
4286 gen_tbl(env);
4287 gen_spr_5xx_8xx(env);
4288 gen_spr_5xx(env);
4289 init_excp_MPC5xx(env);
4290 env->dcache_line_size = 32;
4291 env->icache_line_size = 32;
4292 /* XXX: TODO: allocate internal IRQ controller */
4293 }
4294
4295 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4296 {
4297 DeviceClass *dc = DEVICE_CLASS(oc);
4298 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4299
4300 dc->desc = "Freescale 5xx cores (aka RCPU)";
4301 pcc->init_proc = init_proc_MPC5xx;
4302 pcc->check_pow = check_pow_none;
4303 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4304 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4305 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4306 PPC_MFTB;
4307 pcc->msr_mask = (1ull << MSR_ILE) |
4308 (1ull << MSR_EE) |
4309 (1ull << MSR_PR) |
4310 (1ull << MSR_FP) |
4311 (1ull << MSR_ME) |
4312 (1ull << MSR_FE0) |
4313 (1ull << MSR_SE) |
4314 (1ull << MSR_DE) |
4315 (1ull << MSR_FE1) |
4316 (1ull << MSR_EP) |
4317 (1ull << MSR_RI) |
4318 (1ull << MSR_LE);
4319 pcc->mmu_model = POWERPC_MMU_REAL;
4320 pcc->excp_model = POWERPC_EXCP_603;
4321 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4322 pcc->bfd_mach = bfd_mach_ppc_505;
4323 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4324 POWERPC_FLAG_BUS_CLK;
4325 }
4326
4327 static void init_proc_MPC8xx (CPUPPCState *env)
4328 {
4329 /* Time base */
4330 gen_tbl(env);
4331 gen_spr_5xx_8xx(env);
4332 gen_spr_8xx(env);
4333 init_excp_MPC8xx(env);
4334 env->dcache_line_size = 32;
4335 env->icache_line_size = 32;
4336 /* XXX: TODO: allocate internal IRQ controller */
4337 }
4338
4339 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4340 {
4341 DeviceClass *dc = DEVICE_CLASS(oc);
4342 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4343
4344 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4345 pcc->init_proc = init_proc_MPC8xx;
4346 pcc->check_pow = check_pow_none;
4347 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4348 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4349 PPC_CACHE_ICBI | PPC_MFTB;
4350 pcc->msr_mask = (1ull << MSR_ILE) |
4351 (1ull << MSR_EE) |
4352 (1ull << MSR_PR) |
4353 (1ull << MSR_FP) |
4354 (1ull << MSR_ME) |
4355 (1ull << MSR_SE) |
4356 (1ull << MSR_DE) |
4357 (1ull << MSR_EP) |
4358 (1ull << MSR_IR) |
4359 (1ull << MSR_DR) |
4360 (1ull << MSR_RI) |
4361 (1ull << MSR_LE);
4362 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4363 pcc->excp_model = POWERPC_EXCP_603;
4364 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4365 pcc->bfd_mach = bfd_mach_ppc_860;
4366 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4367 POWERPC_FLAG_BUS_CLK;
4368 }
4369
4370 /* Freescale 82xx cores (aka PowerQUICC-II) */
4371
4372 static void init_proc_G2 (CPUPPCState *env)
4373 {
4374 gen_spr_ne_601(env);
4375 gen_spr_G2_755(env);
4376 gen_spr_G2(env);
4377 /* Time base */
4378 gen_tbl(env);
4379 /* External access control */
4380 /* XXX : not implemented */
4381 spr_register(env, SPR_EAR, "EAR",
4382 SPR_NOACCESS, SPR_NOACCESS,
4383 &spr_read_generic, &spr_write_generic,
4384 0x00000000);
4385 /* Hardware implementation register */
4386 /* XXX : not implemented */
4387 spr_register(env, SPR_HID0, "HID0",
4388 SPR_NOACCESS, SPR_NOACCESS,
4389 &spr_read_generic, &spr_write_generic,
4390 0x00000000);
4391 /* XXX : not implemented */
4392 spr_register(env, SPR_HID1, "HID1",
4393 SPR_NOACCESS, SPR_NOACCESS,
4394 &spr_read_generic, &spr_write_generic,
4395 0x00000000);
4396 /* XXX : not implemented */
4397 spr_register(env, SPR_HID2, "HID2",
4398 SPR_NOACCESS, SPR_NOACCESS,
4399 &spr_read_generic, &spr_write_generic,
4400 0x00000000);
4401 /* Memory management */
4402 gen_low_BATs(env);
4403 gen_high_BATs(env);
4404 gen_6xx_7xx_soft_tlb(env, 64, 2);
4405 init_excp_G2(env);
4406 env->dcache_line_size = 32;
4407 env->icache_line_size = 32;
4408 /* Allocate hardware IRQ controller */
4409 ppc6xx_irq_init(ppc_env_get_cpu(env));
4410 }
4411
4412 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4413 {
4414 DeviceClass *dc = DEVICE_CLASS(oc);
4415 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4416
4417 dc->desc = "PowerPC G2";
4418 pcc->init_proc = init_proc_G2;
4419 pcc->check_pow = check_pow_hid0;
4420 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4421 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4422 PPC_FLOAT_STFIWX |
4423 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4424 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4425 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4426 PPC_SEGMENT | PPC_EXTERN;
4427 pcc->msr_mask = (1ull << MSR_POW) |
4428 (1ull << MSR_TGPR) |
4429 (1ull << MSR_EE) |
4430 (1ull << MSR_PR) |
4431 (1ull << MSR_FP) |
4432 (1ull << MSR_ME) |
4433 (1ull << MSR_FE0) |
4434 (1ull << MSR_SE) |
4435 (1ull << MSR_DE) |
4436 (1ull << MSR_FE1) |
4437 (1ull << MSR_AL) |
4438 (1ull << MSR_EP) |
4439 (1ull << MSR_IR) |
4440 (1ull << MSR_DR) |
4441 (1ull << MSR_RI);
4442 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4443 pcc->excp_model = POWERPC_EXCP_G2;
4444 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4445 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4446 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4447 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4448 }
4449
4450 static void init_proc_G2LE (CPUPPCState *env)
4451 {
4452 gen_spr_ne_601(env);
4453 gen_spr_G2_755(env);
4454 gen_spr_G2(env);
4455 /* Time base */
4456 gen_tbl(env);
4457 /* External access control */
4458 /* XXX : not implemented */
4459 spr_register(env, SPR_EAR, "EAR",
4460 SPR_NOACCESS, SPR_NOACCESS,
4461 &spr_read_generic, &spr_write_generic,
4462 0x00000000);
4463 /* Hardware implementation register */
4464 /* XXX : not implemented */
4465 spr_register(env, SPR_HID0, "HID0",
4466 SPR_NOACCESS, SPR_NOACCESS,
4467 &spr_read_generic, &spr_write_generic,
4468 0x00000000);
4469 /* XXX : not implemented */
4470 spr_register(env, SPR_HID1, "HID1",
4471 SPR_NOACCESS, SPR_NOACCESS,
4472 &spr_read_generic, &spr_write_generic,
4473 0x00000000);
4474 /* XXX : not implemented */
4475 spr_register(env, SPR_HID2, "HID2",
4476 SPR_NOACCESS, SPR_NOACCESS,
4477 &spr_read_generic, &spr_write_generic,
4478 0x00000000);
4479
4480 /* Memory management */
4481 gen_low_BATs(env);
4482 gen_high_BATs(env);
4483 gen_6xx_7xx_soft_tlb(env, 64, 2);
4484 init_excp_G2(env);
4485 env->dcache_line_size = 32;
4486 env->icache_line_size = 32;
4487 /* Allocate hardware IRQ controller */
4488 ppc6xx_irq_init(ppc_env_get_cpu(env));
4489 }
4490
4491 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4492 {
4493 DeviceClass *dc = DEVICE_CLASS(oc);
4494 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4495
4496 dc->desc = "PowerPC G2LE";
4497 pcc->init_proc = init_proc_G2LE;
4498 pcc->check_pow = check_pow_hid0;
4499 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4500 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4501 PPC_FLOAT_STFIWX |
4502 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4503 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4504 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4505 PPC_SEGMENT | PPC_EXTERN;
4506 pcc->msr_mask = (1ull << MSR_POW) |
4507 (1ull << MSR_TGPR) |
4508 (1ull << MSR_ILE) |
4509 (1ull << MSR_EE) |
4510 (1ull << MSR_PR) |
4511 (1ull << MSR_FP) |
4512 (1ull << MSR_ME) |
4513 (1ull << MSR_FE0) |
4514 (1ull << MSR_SE) |
4515 (1ull << MSR_DE) |
4516 (1ull << MSR_FE1) |
4517 (1ull << MSR_AL) |
4518 (1ull << MSR_EP) |
4519 (1ull << MSR_IR) |
4520 (1ull << MSR_DR) |
4521 (1ull << MSR_RI) |
4522 (1ull << MSR_LE);
4523 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4524 pcc->excp_model = POWERPC_EXCP_G2;
4525 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4526 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4527 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4528 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4529 }
4530
4531 static void init_proc_e200 (CPUPPCState *env)
4532 {
4533 /* Time base */
4534 gen_tbl(env);
4535 gen_spr_BookE(env, 0x000000070000FFFFULL);
4536 /* XXX : not implemented */
4537 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4538 &spr_read_spefscr, &spr_write_spefscr,
4539 &spr_read_spefscr, &spr_write_spefscr,
4540 0x00000000);
4541 /* Memory management */
4542 gen_spr_BookE206(env, 0x0000005D, NULL);
4543 /* XXX : not implemented */
4544 spr_register(env, SPR_HID0, "HID0",
4545 SPR_NOACCESS, SPR_NOACCESS,
4546 &spr_read_generic, &spr_write_generic,
4547 0x00000000);
4548 /* XXX : not implemented */
4549 spr_register(env, SPR_HID1, "HID1",
4550 SPR_NOACCESS, SPR_NOACCESS,
4551 &spr_read_generic, &spr_write_generic,
4552 0x00000000);
4553 /* XXX : not implemented */
4554 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4555 SPR_NOACCESS, SPR_NOACCESS,
4556 &spr_read_generic, &spr_write_generic,
4557 0x00000000);
4558 /* XXX : not implemented */
4559 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4560 SPR_NOACCESS, SPR_NOACCESS,
4561 &spr_read_generic, &spr_write_generic,
4562 0x00000000);
4563 /* XXX : not implemented */
4564 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4565 SPR_NOACCESS, SPR_NOACCESS,
4566 &spr_read_generic, &spr_write_generic,
4567 0x00000000);
4568 /* XXX : not implemented */
4569 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4570 SPR_NOACCESS, SPR_NOACCESS,
4571 &spr_read_generic, &spr_write_generic,
4572 0x00000000);
4573 /* XXX : not implemented */
4574 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4575 SPR_NOACCESS, SPR_NOACCESS,
4576 &spr_read_generic, &spr_write_generic,
4577 0x00000000);
4578 /* XXX : not implemented */
4579 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4580 &spr_read_generic, SPR_NOACCESS,
4581 &spr_read_generic, SPR_NOACCESS,
4582 0x00000000);
4583 /* XXX : not implemented */
4584 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4585 SPR_NOACCESS, SPR_NOACCESS,
4586 &spr_read_generic, &spr_write_generic,
4587 0x00000000);
4588 /* XXX : not implemented */
4589 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4590 SPR_NOACCESS, SPR_NOACCESS,
4591 &spr_read_generic, &spr_write_generic,
4592 0x00000000);
4593 /* XXX : not implemented */
4594 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4595 SPR_NOACCESS, SPR_NOACCESS,
4596 &spr_read_generic, &spr_write_generic,
4597 0x00000000);
4598 /* XXX : not implemented */
4599 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4600 SPR_NOACCESS, SPR_NOACCESS,
4601 &spr_read_generic, &spr_write_generic,
4602 0x00000000);
4603 /* XXX : not implemented */
4604 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4605 SPR_NOACCESS, SPR_NOACCESS,
4606 &spr_read_generic, &spr_write_generic,
4607 0x00000000);
4608 /* XXX : not implemented */
4609 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4610 SPR_NOACCESS, SPR_NOACCESS,
4611 &spr_read_generic, &spr_write_generic,
4612 0x00000000);
4613 /* XXX : not implemented */
4614 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4615 SPR_NOACCESS, SPR_NOACCESS,
4616 &spr_read_generic, &spr_write_generic,
4617 0x00000000); /* TOFIX */
4618 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4619 SPR_NOACCESS, SPR_NOACCESS,
4620 &spr_read_generic, &spr_write_generic,
4621 0x00000000);
4622 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4623 SPR_NOACCESS, SPR_NOACCESS,
4624 &spr_read_generic, &spr_write_generic,
4625 0x00000000);
4626 #if !defined(CONFIG_USER_ONLY)
4627 env->nb_tlb = 64;
4628 env->nb_ways = 1;
4629 env->id_tlbs = 0;
4630 env->tlb_type = TLB_EMB;
4631 #endif
4632 init_excp_e200(env, 0xFFFF0000UL);
4633 env->dcache_line_size = 32;
4634 env->icache_line_size = 32;
4635 /* XXX: TODO: allocate internal IRQ controller */
4636 }
4637
4638 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4639 {
4640 DeviceClass *dc = DEVICE_CLASS(oc);
4641 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4642
4643 dc->desc = "e200 core";
4644 pcc->init_proc = init_proc_e200;
4645 pcc->check_pow = check_pow_hid0;
4646 /* XXX: unimplemented instructions:
4647 * dcblc
4648 * dcbtlst
4649 * dcbtstls
4650 * icblc
4651 * icbtls
4652 * tlbivax
4653 * all SPE multiply-accumulate instructions
4654 */
4655 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4656 PPC_SPE | PPC_SPE_SINGLE |
4657 PPC_WRTEE | PPC_RFDI |
4658 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4659 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4660 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4661 PPC_BOOKE;
4662 pcc->msr_mask = (1ull << MSR_UCLE) |
4663 (1ull << MSR_SPE) |
4664 (1ull << MSR_POW) |
4665 (1ull << MSR_CE) |
4666 (1ull << MSR_EE) |
4667 (1ull << MSR_PR) |
4668 (1ull << MSR_FP) |
4669 (1ull << MSR_ME) |
4670 (1ull << MSR_FE0) |
4671 (1ull << MSR_DWE) |
4672 (1ull << MSR_DE) |
4673 (1ull << MSR_FE1) |
4674 (1ull << MSR_IR) |
4675 (1ull << MSR_DR);
4676 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4677 pcc->excp_model = POWERPC_EXCP_BOOKE;
4678 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4679 pcc->bfd_mach = bfd_mach_ppc_860;
4680 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4681 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4682 POWERPC_FLAG_BUS_CLK;
4683 }
4684
4685 static void init_proc_e300 (CPUPPCState *env)
4686 {
4687 gen_spr_ne_601(env);
4688 gen_spr_603(env);
4689 /* Time base */
4690 gen_tbl(env);
4691 /* hardware implementation registers */
4692 /* XXX : not implemented */
4693 spr_register(env, SPR_HID0, "HID0",
4694 SPR_NOACCESS, SPR_NOACCESS,
4695 &spr_read_generic, &spr_write_generic,
4696 0x00000000);
4697 /* XXX : not implemented */
4698 spr_register(env, SPR_HID1, "HID1",
4699 SPR_NOACCESS, SPR_NOACCESS,
4700 &spr_read_generic, &spr_write_generic,
4701 0x00000000);
4702 /* XXX : not implemented */
4703 spr_register(env, SPR_HID2, "HID2",
4704 SPR_NOACCESS, SPR_NOACCESS,
4705 &spr_read_generic, &spr_write_generic,
4706 0x00000000);
4707 /* Breakpoints */
4708 /* XXX : not implemented */
4709 spr_register(env, SPR_DABR, "DABR",
4710 SPR_NOACCESS, SPR_NOACCESS,
4711 &spr_read_generic, &spr_write_generic,
4712 0x00000000);
4713 /* XXX : not implemented */
4714 spr_register(env, SPR_DABR2, "DABR2",
4715 SPR_NOACCESS, SPR_NOACCESS,
4716 &spr_read_generic, &spr_write_generic,
4717 0x00000000);
4718 /* XXX : not implemented */
4719 spr_register(env, SPR_IABR2, "IABR2",
4720 SPR_NOACCESS, SPR_NOACCESS,
4721 &spr_read_generic, &spr_write_generic,
4722 0x00000000);
4723 /* XXX : not implemented */
4724 spr_register(env, SPR_IBCR, "IBCR",
4725 SPR_NOACCESS, SPR_NOACCESS,
4726 &spr_read_generic, &spr_write_generic,
4727 0x00000000);
4728 /* XXX : not implemented */
4729 spr_register(env, SPR_DBCR, "DBCR",
4730 SPR_NOACCESS, SPR_NOACCESS,
4731 &spr_read_generic, &spr_write_generic,
4732 0x00000000);
4733 /* Memory management */
4734 gen_low_BATs(env);
4735 gen_high_BATs(env);
4736 gen_6xx_7xx_soft_tlb(env, 64, 2);
4737 init_excp_603(env);
4738 env->dcache_line_size = 32;
4739 env->icache_line_size = 32;
4740 /* Allocate hardware IRQ controller */
4741 ppc6xx_irq_init(ppc_env_get_cpu(env));
4742 }
4743
4744 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4745 {
4746 DeviceClass *dc = DEVICE_CLASS(oc);
4747 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4748
4749 dc->desc = "e300 core";
4750 pcc->init_proc = init_proc_e300;
4751 pcc->check_pow = check_pow_hid0;
4752 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4753 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4754 PPC_FLOAT_STFIWX |
4755 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4756 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4757 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4758 PPC_SEGMENT | PPC_EXTERN;
4759 pcc->msr_mask = (1ull << MSR_POW) |
4760 (1ull << MSR_TGPR) |
4761 (1ull << MSR_ILE) |
4762 (1ull << MSR_EE) |
4763 (1ull << MSR_PR) |
4764 (1ull << MSR_FP) |
4765 (1ull << MSR_ME) |
4766 (1ull << MSR_FE0) |
4767 (1ull << MSR_SE) |
4768 (1ull << MSR_DE) |
4769 (1ull << MSR_FE1) |
4770 (1ull << MSR_AL) |
4771 (1ull << MSR_EP) |
4772 (1ull << MSR_IR) |
4773 (1ull << MSR_DR) |
4774 (1ull << MSR_RI) |
4775 (1ull << MSR_LE);
4776 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4777 pcc->excp_model = POWERPC_EXCP_603;
4778 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4779 pcc->bfd_mach = bfd_mach_ppc_603;
4780 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4781 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4782 }
4783
4784 #if !defined(CONFIG_USER_ONLY)
4785 static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
4786 {
4787 TCGv val = tcg_temp_new();
4788 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4789 gen_store_spr(SPR_BOOKE_MAS3, val);
4790 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4791 gen_store_spr(SPR_BOOKE_MAS7, val);
4792 tcg_temp_free(val);
4793 }
4794
4795 static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
4796 {
4797 TCGv mas7 = tcg_temp_new();
4798 TCGv mas3 = tcg_temp_new();
4799 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4800 tcg_gen_shli_tl(mas7, mas7, 32);
4801 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4802 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4803 tcg_temp_free(mas3);
4804 tcg_temp_free(mas7);
4805 }
4806
4807 #endif
4808
4809 enum fsl_e500_version {
4810 fsl_e500v1,
4811 fsl_e500v2,
4812 fsl_e500mc,
4813 fsl_e5500,
4814 };
4815
4816 static void init_proc_e500 (CPUPPCState *env, int version)
4817 {
4818 PowerPCCPU *cpu = ppc_env_get_cpu(env);
4819 uint32_t tlbncfg[2];
4820 uint64_t ivor_mask;
4821 uint64_t ivpr_mask = 0xFFFF0000ULL;
4822 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4823 | 0x0020; /* 32 kb */
4824 uint32_t l1cfg1 = 0x3800 /* 8 ways */
4825 | 0x0020; /* 32 kb */
4826 #if !defined(CONFIG_USER_ONLY)
4827 int i;
4828 #endif
4829
4830 /* Time base */
4831 gen_tbl(env);
4832 /*
4833 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4834 * complain when accessing them.
4835 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4836 */
4837 switch (version) {
4838 case fsl_e500v1:
4839 case fsl_e500v2:
4840 default:
4841 ivor_mask = 0x0000000F0000FFFFULL;
4842 break;
4843 case fsl_e500mc:
4844 case fsl_e5500:
4845 ivor_mask = 0x000003FE0000FFFFULL;
4846 break;
4847 }
4848 gen_spr_BookE(env, ivor_mask);
4849 /* Processor identification */
4850 spr_register(env, SPR_BOOKE_PIR, "PIR",
4851 SPR_NOACCESS, SPR_NOACCESS,
4852 &spr_read_generic, &spr_write_pir,
4853 0x00000000);
4854 /* XXX : not implemented */
4855 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4856 &spr_read_spefscr, &spr_write_spefscr,
4857 &spr_read_spefscr, &spr_write_spefscr,
4858 0x00000000);
4859 #if !defined(CONFIG_USER_ONLY)
4860 /* Memory management */
4861 env->nb_pids = 3;
4862 env->nb_ways = 2;
4863 env->id_tlbs = 0;
4864 switch (version) {
4865 case fsl_e500v1:
4866 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4867 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4868 break;
4869 case fsl_e500v2:
4870 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4871 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4872 break;
4873 case fsl_e500mc:
4874 case fsl_e5500:
4875 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4876 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4877 break;
4878 default:
4879 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4880 }
4881 #endif
4882 /* Cache sizes */
4883 switch (version) {
4884 case fsl_e500v1:
4885 case fsl_e500v2:
4886 env->dcache_line_size = 32;
4887 env->icache_line_size = 32;
4888 break;
4889 case fsl_e500mc:
4890 case fsl_e5500:
4891 env->dcache_line_size = 64;
4892 env->icache_line_size = 64;
4893 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4894 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
4895 break;
4896 default:
4897 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4898 }
4899 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4900 /* XXX : not implemented */
4901 spr_register(env, SPR_HID0, "HID0",
4902 SPR_NOACCESS, SPR_NOACCESS,
4903 &spr_read_generic, &spr_write_generic,
4904 0x00000000);
4905 /* XXX : not implemented */
4906 spr_register(env, SPR_HID1, "HID1",
4907 SPR_NOACCESS, SPR_NOACCESS,
4908 &spr_read_generic, &spr_write_generic,
4909 0x00000000);
4910 /* XXX : not implemented */
4911 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4912 SPR_NOACCESS, SPR_NOACCESS,
4913 &spr_read_generic, &spr_write_generic,
4914 0x00000000);
4915 /* XXX : not implemented */
4916 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4917 SPR_NOACCESS, SPR_NOACCESS,
4918 &spr_read_generic, &spr_write_generic,
4919 0x00000000);
4920 /* XXX : not implemented */
4921 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4922 SPR_NOACCESS, SPR_NOACCESS,
4923 &spr_read_generic, &spr_write_generic,
4924 0x00000000);
4925 /* XXX : not implemented */
4926 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4927 SPR_NOACCESS, SPR_NOACCESS,
4928 &spr_read_generic, &spr_write_generic,
4929 0x00000000);
4930 /* XXX : not implemented */
4931 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4932 SPR_NOACCESS, SPR_NOACCESS,
4933 &spr_read_generic, &spr_write_generic,
4934 0x00000000);
4935 /* XXX : not implemented */
4936 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4937 SPR_NOACCESS, SPR_NOACCESS,
4938 &spr_read_generic, &spr_write_generic,
4939 0x00000000);
4940 /* XXX : not implemented */
4941 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4942 &spr_read_generic, SPR_NOACCESS,
4943 &spr_read_generic, SPR_NOACCESS,
4944 l1cfg0);
4945 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
4946 &spr_read_generic, SPR_NOACCESS,
4947 &spr_read_generic, SPR_NOACCESS,
4948 l1cfg1);
4949 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4950 SPR_NOACCESS, SPR_NOACCESS,
4951 &spr_read_generic, &spr_write_e500_l1csr0,
4952 0x00000000);
4953 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4954 SPR_NOACCESS, SPR_NOACCESS,
4955 &spr_read_generic, &spr_write_e500_l1csr1,
4956 0x00000000);
4957 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4958 SPR_NOACCESS, SPR_NOACCESS,
4959 &spr_read_generic, &spr_write_generic,
4960 0x00000000);
4961 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4962 SPR_NOACCESS, SPR_NOACCESS,
4963 &spr_read_generic, &spr_write_generic,
4964 0x00000000);
4965 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4966 SPR_NOACCESS, SPR_NOACCESS,
4967 &spr_read_generic, &spr_write_booke206_mmucsr0,
4968 0x00000000);
4969 spr_register(env, SPR_BOOKE_EPR, "EPR",
4970 SPR_NOACCESS, SPR_NOACCESS,
4971 &spr_read_generic, SPR_NOACCESS,
4972 0x00000000);
4973 /* XXX better abstract into Emb.xxx features */
4974 if (version == fsl_e5500) {
4975 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4976 SPR_NOACCESS, SPR_NOACCESS,
4977 &spr_read_generic, &spr_write_generic,
4978 0x00000000);
4979 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4980 SPR_NOACCESS, SPR_NOACCESS,
4981 &spr_read_mas73, &spr_write_mas73,
4982 0x00000000);
4983 ivpr_mask = (target_ulong)~0xFFFFULL;
4984 }
4985
4986 #if !defined(CONFIG_USER_ONLY)
4987 env->nb_tlb = 0;
4988 env->tlb_type = TLB_MAS;
4989 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4990 env->nb_tlb += booke206_tlb_size(env, i);
4991 }
4992 #endif
4993
4994 init_excp_e200(env, ivpr_mask);
4995 /* Allocate hardware IRQ controller */
4996 ppce500_irq_init(ppc_env_get_cpu(env));
4997 }
4998
4999 static void init_proc_e500v1(CPUPPCState *env)
5000 {
5001 init_proc_e500(env, fsl_e500v1);
5002 }
5003
5004 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
5005 {
5006 DeviceClass *dc = DEVICE_CLASS(oc);
5007 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5008
5009 dc->desc = "e500v1 core";
5010 pcc->init_proc = init_proc_e500v1;
5011 pcc->check_pow = check_pow_hid0;
5012 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5013 PPC_SPE | PPC_SPE_SINGLE |
5014 PPC_WRTEE | PPC_RFDI |
5015 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5016 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5017 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5018 pcc->insns_flags2 = PPC2_BOOKE206;
5019 pcc->msr_mask = (1ull << MSR_UCLE) |
5020 (1ull << MSR_SPE) |
5021 (1ull << MSR_POW) |
5022 (1ull << MSR_CE) |
5023 (1ull << MSR_EE) |
5024 (1ull << MSR_PR) |
5025 (1ull << MSR_FP) |
5026 (1ull << MSR_ME) |
5027 (1ull << MSR_FE0) |
5028 (1ull << MSR_DWE) |
5029 (1ull << MSR_DE) |
5030 (1ull << MSR_FE1) |
5031 (1ull << MSR_IR) |
5032 (1ull << MSR_DR);
5033 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5034 pcc->excp_model = POWERPC_EXCP_BOOKE;
5035 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5036 pcc->bfd_mach = bfd_mach_ppc_860;
5037 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
5038 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
5039 POWERPC_FLAG_BUS_CLK;
5040 }
5041
5042 static void init_proc_e500v2(CPUPPCState *env)
5043 {
5044 init_proc_e500(env, fsl_e500v2);
5045 }
5046
5047 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
5048 {
5049 DeviceClass *dc = DEVICE_CLASS(oc);
5050 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5051
5052 dc->desc = "e500v2 core";
5053 pcc->init_proc = init_proc_e500v2;
5054 pcc->check_pow = check_pow_hid0;
5055 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5056 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
5057 PPC_WRTEE | PPC_RFDI |
5058 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5059 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5060 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5061 pcc->insns_flags2 = PPC2_BOOKE206;
5062 pcc->msr_mask = (1ull << MSR_UCLE) |
5063 (1ull << MSR_SPE) |
5064 (1ull << MSR_POW) |
5065 (1ull << MSR_CE) |
5066 (1ull << MSR_EE) |
5067 (1ull << MSR_PR) |
5068 (1ull << MSR_FP) |
5069 (1ull << MSR_ME) |
5070 (1ull << MSR_FE0) |
5071 (1ull << MSR_DWE) |
5072 (1ull << MSR_DE) |
5073 (1ull << MSR_FE1) |
5074 (1ull << MSR_IR) |
5075 (1ull << MSR_DR);
5076 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5077 pcc->excp_model = POWERPC_EXCP_BOOKE;
5078 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5079 pcc->bfd_mach = bfd_mach_ppc_860;
5080 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
5081 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
5082 POWERPC_FLAG_BUS_CLK;
5083 }
5084
5085 static void init_proc_e500mc(CPUPPCState *env)
5086 {
5087 init_proc_e500(env, fsl_e500mc);
5088 }
5089
5090 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
5091 {
5092 DeviceClass *dc = DEVICE_CLASS(oc);
5093 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5094
5095 dc->desc = "e500mc core";
5096 pcc->init_proc = init_proc_e500mc;
5097 pcc->check_pow = check_pow_none;
5098 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5099 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5100 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5101 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5102 PPC_FLOAT | PPC_FLOAT_FRES |
5103 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5104 PPC_FLOAT_STFIWX | PPC_WAIT |
5105 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5106 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
5107 pcc->msr_mask = (1ull << MSR_GS) |
5108 (1ull << MSR_UCLE) |
5109 (1ull << MSR_CE) |
5110 (1ull << MSR_EE) |
5111 (1ull << MSR_PR) |
5112 (1ull << MSR_FP) |
5113 (1ull << MSR_ME) |
5114 (1ull << MSR_FE0) |
5115 (1ull << MSR_DE) |
5116 (1ull << MSR_FE1) |
5117 (1ull << MSR_IR) |
5118 (1ull << MSR_DR) |
5119 (1ull << MSR_PX) |
5120 (1ull << MSR_RI);
5121 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5122 pcc->excp_model = POWERPC_EXCP_BOOKE;
5123 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5124 /* FIXME: figure out the correct flag for e500mc */
5125 pcc->bfd_mach = bfd_mach_ppc_e500;
5126 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5127 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5128 }
5129
5130 #ifdef TARGET_PPC64
5131 static void init_proc_e5500(CPUPPCState *env)
5132 {
5133 init_proc_e500(env, fsl_e5500);
5134 }
5135
5136 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
5137 {
5138 DeviceClass *dc = DEVICE_CLASS(oc);
5139 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5140
5141 dc->desc = "e5500 core";
5142 pcc->init_proc = init_proc_e5500;
5143 pcc->check_pow = check_pow_none;
5144 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5145 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5146 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5147 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5148 PPC_FLOAT | PPC_FLOAT_FRES |
5149 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5150 PPC_FLOAT_STFIWX | PPC_WAIT |
5151 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
5152 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
5153 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | \
5154 PPC2_FP_CVT_S64;
5155 pcc->msr_mask = (1ull << MSR_CM) |
5156 (1ull << MSR_GS) |
5157 (1ull << MSR_UCLE) |
5158 (1ull << MSR_CE) |
5159 (1ull << MSR_EE) |
5160 (1ull << MSR_PR) |
5161 (1ull << MSR_FP) |
5162 (1ull << MSR_ME) |
5163 (1ull << MSR_FE0) |
5164 (1ull << MSR_DE) |
5165 (1ull << MSR_FE1) |
5166 (1ull << MSR_IR) |
5167 (1ull << MSR_DR) |
5168 (1ull << MSR_PX) |
5169 (1ull << MSR_RI);
5170 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5171 pcc->excp_model = POWERPC_EXCP_BOOKE;
5172 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5173 /* FIXME: figure out the correct flag for e5500 */
5174 pcc->bfd_mach = bfd_mach_ppc_e500;
5175 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5176 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5177 }
5178 #endif
5179
5180 /* Non-embedded PowerPC */
5181
5182 /* POWER : same as 601, without mfmsr, mfsr */
5183 POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
5184 {
5185 DeviceClass *dc = DEVICE_CLASS(oc);
5186 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5187
5188 dc->desc = "POWER";
5189 /* pcc->insns_flags = XXX_TODO; */
5190 /* POWER RSC (from RAD6000) */
5191 pcc->msr_mask = (1ull << MSR_EE) |
5192 (1ull << MSR_PR) |
5193 (1ull << MSR_FP) |
5194 (1ull << MSR_ME) |
5195 (1ull << MSR_FE0) |
5196 (1ull << MSR_SE) |
5197 (1ull << MSR_DE) |
5198 (1ull << MSR_AL) |
5199 (1ull << MSR_EP) |
5200 (1ull << MSR_IR) |
5201 (1ull << MSR_DR);
5202 }
5203
5204 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
5205
5206 static void init_proc_601 (CPUPPCState *env)
5207 {
5208 gen_spr_ne_601(env);
5209 gen_spr_601(env);
5210 /* Hardware implementation registers */
5211 /* XXX : not implemented */
5212 spr_register(env, SPR_HID0, "HID0",
5213 SPR_NOACCESS, SPR_NOACCESS,
5214 &spr_read_generic, &spr_write_hid0_601,
5215 0x80010080);
5216 /* XXX : not implemented */
5217 spr_register(env, SPR_HID1, "HID1",
5218 SPR_NOACCESS, SPR_NOACCESS,
5219 &spr_read_generic, &spr_write_generic,
5220 0x00000000);
5221 /* XXX : not implemented */
5222 spr_register(env, SPR_601_HID2, "HID2",
5223 SPR_NOACCESS, SPR_NOACCESS,
5224 &spr_read_generic, &spr_write_generic,
5225 0x00000000);
5226 /* XXX : not implemented */
5227 spr_register(env, SPR_601_HID5, "HID5",
5228 SPR_NOACCESS, SPR_NOACCESS,
5229 &spr_read_generic, &spr_write_generic,
5230 0x00000000);
5231 /* Memory management */
5232 init_excp_601(env);
5233 /* XXX: beware that dcache line size is 64
5234 * but dcbz uses 32 bytes "sectors"
5235 * XXX: this breaks clcs instruction !
5236 */
5237 env->dcache_line_size = 32;
5238 env->icache_line_size = 64;
5239 /* Allocate hardware IRQ controller */
5240 ppc6xx_irq_init(ppc_env_get_cpu(env));
5241 }
5242
5243 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
5244 {
5245 DeviceClass *dc = DEVICE_CLASS(oc);
5246 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5247
5248 dc->desc = "PowerPC 601";
5249 pcc->init_proc = init_proc_601;
5250 pcc->check_pow = check_pow_none;
5251 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5252 PPC_FLOAT |
5253 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5254 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5255 PPC_SEGMENT | PPC_EXTERN;
5256 pcc->msr_mask = (1ull << MSR_EE) |
5257 (1ull << MSR_PR) |
5258 (1ull << MSR_FP) |
5259 (1ull << MSR_ME) |
5260 (1ull << MSR_FE0) |
5261 (1ull << MSR_SE) |
5262 (1ull << MSR_FE1) |
5263 (1ull << MSR_EP) |
5264 (1ull << MSR_IR) |
5265 (1ull << MSR_DR);
5266 pcc->mmu_model = POWERPC_MMU_601;
5267 #if defined(CONFIG_SOFTMMU)
5268 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5269 #endif
5270 pcc->excp_model = POWERPC_EXCP_601;
5271 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5272 pcc->bfd_mach = bfd_mach_ppc_601;
5273 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5274 }
5275
5276 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
5277
5278 static void init_proc_601v (CPUPPCState *env)
5279 {
5280 init_proc_601(env);
5281 /* XXX : not implemented */
5282 spr_register(env, SPR_601_HID15, "HID15",
5283 SPR_NOACCESS, SPR_NOACCESS,
5284 &spr_read_generic, &spr_write_generic,
5285 0x00000000);
5286 }
5287
5288 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
5289 {
5290 DeviceClass *dc = DEVICE_CLASS(oc);
5291 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5292
5293 dc->desc = "PowerPC 601v";
5294 pcc->init_proc = init_proc_601v;
5295 pcc->check_pow = check_pow_none;
5296 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5297 PPC_FLOAT |
5298 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5299 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5300 PPC_SEGMENT | PPC_EXTERN;
5301 pcc->msr_mask = (1ull << MSR_EE) |
5302 (1ull << MSR_PR) |
5303 (1ull << MSR_FP) |
5304 (1ull << MSR_ME) |
5305 (1ull << MSR_FE0) |
5306 (1ull << MSR_SE) |
5307 (1ull << MSR_FE1) |
5308 (1ull << MSR_EP) |
5309 (1ull << MSR_IR) |
5310 (1ull << MSR_DR);
5311 pcc->mmu_model = POWERPC_MMU_601;
5312 #if defined(CONFIG_SOFTMMU)
5313 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5314 #endif
5315 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5316 pcc->bfd_mach = bfd_mach_ppc_601;
5317 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5318 }
5319
5320 static void init_proc_602 (CPUPPCState *env)
5321 {
5322 gen_spr_ne_601(env);
5323 gen_spr_602(env);
5324 /* Time base */
5325 gen_tbl(env);
5326 /* hardware implementation registers */
5327 /* XXX : not implemented */
5328 spr_register(env, SPR_HID0, "HID0",
5329 SPR_NOACCESS, SPR_NOACCESS,
5330 &spr_read_generic, &spr_write_generic,
5331 0x00000000);
5332 /* XXX : not implemented */
5333 spr_register(env, SPR_HID1, "HID1",
5334 SPR_NOACCESS, SPR_NOACCESS,
5335 &spr_read_generic, &spr_write_generic,
5336 0x00000000);
5337 /* Memory management */
5338 gen_low_BATs(env);
5339 gen_6xx_7xx_soft_tlb(env, 64, 2);
5340 init_excp_602(env);
5341 env->dcache_line_size = 32;
5342 env->icache_line_size = 32;
5343 /* Allocate hardware IRQ controller */
5344 ppc6xx_irq_init(ppc_env_get_cpu(env));
5345 }
5346
5347 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
5348 {
5349 DeviceClass *dc = DEVICE_CLASS(oc);
5350 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5351
5352 dc->desc = "PowerPC 602";
5353 pcc->init_proc = init_proc_602;
5354 pcc->check_pow = check_pow_hid0;
5355 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5356 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5357 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5358 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5359 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5360 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
5361 PPC_SEGMENT | PPC_602_SPEC;
5362 pcc->msr_mask = (1ull << MSR_VSX) |
5363 (1ull << MSR_SA) |
5364 (1ull << MSR_POW) |
5365 (1ull << MSR_TGPR) |
5366 (1ull << MSR_ILE) |
5367 (1ull << MSR_EE) |
5368 (1ull << MSR_PR) |
5369 (1ull << MSR_FP) |
5370 (1ull << MSR_ME) |
5371 (1ull << MSR_FE0) |
5372 (1ull << MSR_SE) |
5373 (1ull << MSR_DE) |
5374 (1ull << MSR_FE1) |
5375 (1ull << MSR_EP) |
5376 (1ull << MSR_IR) |
5377 (1ull << MSR_DR) |
5378 (1ull << MSR_RI) |
5379 (1ull << MSR_LE);
5380 /* XXX: 602 MMU is quite specific. Should add a special case */
5381 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5382 pcc->excp_model = POWERPC_EXCP_602;
5383 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5384 pcc->bfd_mach = bfd_mach_ppc_602;
5385 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5386 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5387 }
5388
5389 static void init_proc_603 (CPUPPCState *env)
5390 {
5391 gen_spr_ne_601(env);
5392 gen_spr_603(env);
5393 /* Time base */
5394 gen_tbl(env);
5395 /* hardware implementation registers */
5396 /* XXX : not implemented */
5397 spr_register(env, SPR_HID0, "HID0",
5398 SPR_NOACCESS, SPR_NOACCESS,
5399 &spr_read_generic, &spr_write_generic,
5400 0x00000000);
5401 /* XXX : not implemented */
5402 spr_register(env, SPR_HID1, "HID1",
5403 SPR_NOACCESS, SPR_NOACCESS,
5404 &spr_read_generic, &spr_write_generic,
5405 0x00000000);
5406 /* Memory management */
5407 gen_low_BATs(env);
5408 gen_6xx_7xx_soft_tlb(env, 64, 2);
5409 init_excp_603(env);
5410 env->dcache_line_size = 32;
5411 env->icache_line_size = 32;
5412 /* Allocate hardware IRQ controller */
5413 ppc6xx_irq_init(ppc_env_get_cpu(env));
5414 }
5415
5416 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
5417 {
5418 DeviceClass *dc = DEVICE_CLASS(oc);
5419 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5420
5421 dc->desc = "PowerPC 603";
5422 pcc->init_proc = init_proc_603;
5423 pcc->check_pow = check_pow_hid0;
5424 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5425 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5426 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5427 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5428 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5429 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5430 PPC_SEGMENT | PPC_EXTERN;
5431 pcc->msr_mask = (1ull << MSR_POW) |
5432 (1ull << MSR_TGPR) |
5433 (1ull << MSR_ILE) |
5434 (1ull << MSR_EE) |
5435 (1ull << MSR_PR) |
5436 (1ull << MSR_FP) |
5437 (1ull << MSR_ME) |
5438 (1ull << MSR_FE0) |
5439 (1ull << MSR_SE) |
5440 (1ull << MSR_DE) |
5441 (1ull << MSR_FE1) |
5442 (1ull << MSR_EP) |
5443 (1ull << MSR_IR) |
5444 (1ull << MSR_DR) |
5445 (1ull << MSR_RI) |
5446 (1ull << MSR_LE);
5447 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5448 pcc->excp_model = POWERPC_EXCP_603;
5449 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5450 pcc->bfd_mach = bfd_mach_ppc_603;
5451 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5452 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5453 }
5454
5455 static void init_proc_603E (CPUPPCState *env)
5456 {
5457 gen_spr_ne_601(env);
5458 gen_spr_603(env);
5459 /* Time base */
5460 gen_tbl(env);
5461 /* hardware implementation registers */
5462 /* XXX : not implemented */
5463 spr_register(env, SPR_HID0, "HID0",
5464 SPR_NOACCESS, SPR_NOACCESS,
5465 &spr_read_generic, &spr_write_generic,
5466 0x00000000);
5467 /* XXX : not implemented */
5468 spr_register(env, SPR_HID1, "HID1",
5469 SPR_NOACCESS, SPR_NOACCESS,
5470 &spr_read_generic, &spr_write_generic,
5471 0x00000000);
5472 /* Memory management */
5473 gen_low_BATs(env);
5474 gen_6xx_7xx_soft_tlb(env, 64, 2);
5475 init_excp_603(env);
5476 env->dcache_line_size = 32;
5477 env->icache_line_size = 32;
5478 /* Allocate hardware IRQ controller */
5479 ppc6xx_irq_init(ppc_env_get_cpu(env));
5480 }
5481
5482 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
5483 {
5484 DeviceClass *dc = DEVICE_CLASS(oc);
5485 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5486
5487 dc->desc = "PowerPC 603e";
5488 pcc->init_proc = init_proc_603E;
5489 pcc->check_pow = check_pow_hid0;
5490 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5491 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5492 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5493 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5494 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5495 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5496 PPC_SEGMENT | PPC_EXTERN;
5497 pcc->msr_mask = (1ull << MSR_POW) |
5498 (1ull << MSR_TGPR) |
5499 (1ull << MSR_ILE) |
5500 (1ull << MSR_EE) |
5501 (1ull << MSR_PR) |
5502 (1ull << MSR_FP) |
5503 (1ull << MSR_ME) |
5504 (1ull << MSR_FE0) |
5505 (1ull << MSR_SE) |
5506 (1ull << MSR_DE) |
5507 (1ull << MSR_FE1) |
5508 (1ull << MSR_EP) |
5509 (1ull << MSR_IR) |
5510 (1ull << MSR_DR) |
5511 (1ull << MSR_RI) |
5512 (1ull << MSR_LE);
5513 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5514 pcc->excp_model = POWERPC_EXCP_603E;
5515 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5516 pcc->bfd_mach = bfd_mach_ppc_ec603e;
5517 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5518 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5519 }
5520
5521 static void init_proc_604 (CPUPPCState *env)
5522 {
5523 gen_spr_ne_601(env);
5524 gen_spr_604(env);
5525 /* Time base */
5526 gen_tbl(env);
5527 /* Hardware implementation registers */
5528 /* XXX : not implemented */
5529 spr_register(env, SPR_HID0, "HID0",
5530 SPR_NOACCESS, SPR_NOACCESS,
5531 &spr_read_generic, &spr_write_generic,
5532 0x00000000);
5533 /* Memory management */
5534 gen_low_BATs(env);
5535 init_excp_604(env);
5536 env->dcache_line_size = 32;
5537 env->icache_line_size = 32;
5538 /* Allocate hardware IRQ controller */
5539 ppc6xx_irq_init(ppc_env_get_cpu(env));
5540 }
5541
5542 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5543 {
5544 DeviceClass *dc = DEVICE_CLASS(oc);
5545 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5546
5547 dc->desc = "PowerPC 604";
5548 pcc->init_proc = init_proc_604;
5549 pcc->check_pow = check_pow_nocheck;
5550 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5551 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5552 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5553 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5554 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5555 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5556 PPC_SEGMENT | PPC_EXTERN;
5557 pcc->msr_mask = (1ull << MSR_POW) |
5558 (1ull << MSR_ILE) |
5559 (1ull << MSR_EE) |
5560 (1ull << MSR_PR) |
5561 (1ull << MSR_FP) |
5562 (1ull << MSR_ME) |
5563 (1ull << MSR_FE0) |
5564 (1ull << MSR_SE) |
5565 (1ull << MSR_DE) |
5566 (1ull << MSR_FE1) |
5567 (1ull << MSR_EP) |
5568 (1ull << MSR_IR) |
5569 (1ull << MSR_DR) |
5570 (1ull << MSR_PMM) |
5571 (1ull << MSR_RI) |
5572 (1ull << MSR_LE);
5573 pcc->mmu_model = POWERPC_MMU_32B;
5574 #if defined(CONFIG_SOFTMMU)
5575 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5576 #endif
5577 pcc->excp_model = POWERPC_EXCP_604;
5578 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5579 pcc->bfd_mach = bfd_mach_ppc_604;
5580 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5581 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5582 }
5583
5584 static void init_proc_604E (CPUPPCState *env)
5585 {
5586 gen_spr_ne_601(env);
5587 gen_spr_604(env);
5588 /* XXX : not implemented */
5589 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
5590 SPR_NOACCESS, SPR_NOACCESS,
5591 &spr_read_generic, &spr_write_generic,
5592 0x00000000);
5593 /* XXX : not implemented */
5594 spr_register(env, SPR_7XX_PMC3, "PMC3",
5595 SPR_NOACCESS, SPR_NOACCESS,
5596 &spr_read_generic, &spr_write_generic,
5597 0x00000000);
5598 /* XXX : not implemented */
5599 spr_register(env, SPR_7XX_PMC4, "PMC4",
5600 SPR_NOACCESS, SPR_NOACCESS,
5601 &spr_read_generic, &spr_write_generic,
5602 0x00000000);
5603 /* Time base */
5604 gen_tbl(env);
5605 /* Hardware implementation registers */
5606 /* XXX : not implemented */
5607 spr_register(env, SPR_HID0, "HID0",
5608 SPR_NOACCESS, SPR_NOACCESS,
5609 &spr_read_generic, &spr_write_generic,
5610 0x00000000);
5611 /* XXX : not implemented */
5612 spr_register(env, SPR_HID1, "HID1",
5613 SPR_NOACCESS, SPR_NOACCESS,
5614 &spr_read_generic, &spr_write_generic,
5615 0x00000000);
5616 /* Memory management */
5617 gen_low_BATs(env);
5618 init_excp_604(env);
5619 env->dcache_line_size = 32;
5620 env->icache_line_size = 32;
5621 /* Allocate hardware IRQ controller */
5622 ppc6xx_irq_init(ppc_env_get_cpu(env));
5623 }
5624
5625 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5626 {
5627 DeviceClass *dc = DEVICE_CLASS(oc);
5628 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5629
5630 dc->desc = "PowerPC 604E";
5631 pcc->init_proc = init_proc_604E;
5632 pcc->check_pow = check_pow_nocheck;
5633 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5634 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5635 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5636 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5637 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5638 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5639 PPC_SEGMENT | PPC_EXTERN;
5640 pcc->msr_mask = (1ull << MSR_POW) |
5641 (1ull << MSR_ILE) |
5642 (1ull << MSR_EE) |
5643 (1ull << MSR_PR) |
5644 (1ull << MSR_FP) |
5645 (1ull << MSR_ME) |
5646 (1ull << MSR_FE0) |
5647 (1ull << MSR_SE) |
5648 (1ull << MSR_DE) |
5649 (1ull << MSR_FE1) |
5650 (1ull << MSR_EP) |
5651 (1ull << MSR_IR) |
5652 (1ull << MSR_DR) |
5653 (1ull << MSR_PMM) |
5654 (1ull << MSR_RI) |
5655 (1ull << MSR_LE);
5656 pcc->mmu_model = POWERPC_MMU_32B;
5657 #if defined(CONFIG_SOFTMMU)
5658 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5659 #endif
5660 pcc->excp_model = POWERPC_EXCP_604;
5661 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5662 pcc->bfd_mach = bfd_mach_ppc_604;
5663 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5664 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5665 }
5666
5667 static void init_proc_740 (CPUPPCState *env)
5668 {
5669 gen_spr_ne_601(env);
5670 gen_spr_7xx(env);
5671 /* Time base */
5672 gen_tbl(env);
5673 /* Thermal management */
5674 gen_spr_thrm(env);
5675 /* Hardware implementation registers */
5676 /* XXX : not implemented */
5677 spr_register(env, SPR_HID0, "HID0",
5678 SPR_NOACCESS, SPR_NOACCESS,
5679 &spr_read_generic, &spr_write_generic,
5680 0x00000000);
5681 /* XXX : not implemented */
5682 spr_register(env, SPR_HID1, "HID1",
5683 SPR_NOACCESS, SPR_NOACCESS,
5684 &spr_read_generic, &spr_write_generic,
5685 0x00000000);
5686 /* Memory management */
5687 gen_low_BATs(env);
5688 init_excp_7x0(env);
5689 env->dcache_line_size = 32;
5690 env->icache_line_size = 32;
5691 /* Allocate hardware IRQ controller */
5692 ppc6xx_irq_init(ppc_env_get_cpu(env));
5693 }
5694
5695 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5696 {
5697 DeviceClass *dc = DEVICE_CLASS(oc);
5698 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5699
5700 dc->desc = "PowerPC 740";
5701 pcc->init_proc = init_proc_740;
5702 pcc->check_pow = check_pow_hid0;
5703 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5704 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5705 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5706 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5707 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5708 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5709 PPC_SEGMENT | PPC_EXTERN;
5710 pcc->msr_mask = (1ull << MSR_POW) |
5711 (1ull << MSR_ILE) |
5712 (1ull << MSR_EE) |
5713 (1ull << MSR_PR) |
5714 (1ull << MSR_FP) |
5715 (1ull << MSR_ME) |
5716 (1ull << MSR_FE0) |
5717 (1ull << MSR_SE) |
5718 (1ull << MSR_DE) |
5719 (1ull << MSR_FE1) |
5720 (1ull << MSR_EP) |
5721 (1ull << MSR_IR) |
5722 (1ull << MSR_DR) |
5723 (1ull << MSR_PMM) |
5724 (1ull << MSR_RI) |
5725 (1ull << MSR_LE);
5726 pcc->mmu_model = POWERPC_MMU_32B;
5727 #if defined(CONFIG_SOFTMMU)
5728 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5729 #endif
5730 pcc->excp_model = POWERPC_EXCP_7x0;
5731 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5732 pcc->bfd_mach = bfd_mach_ppc_750;
5733 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5734 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5735 }
5736
5737 static void init_proc_750 (CPUPPCState *env)
5738 {
5739 gen_spr_ne_601(env);
5740 gen_spr_7xx(env);
5741 /* XXX : not implemented */
5742 spr_register(env, SPR_L2CR, "L2CR",
5743 SPR_NOACCESS, SPR_NOACCESS,
5744 &spr_read_generic, spr_access_nop,
5745 0x00000000);
5746 /* Time base */
5747 gen_tbl(env);
5748 /* Thermal management */
5749 gen_spr_thrm(env);
5750 /* Hardware implementation registers */
5751 /* XXX : not implemented */
5752 spr_register(env, SPR_HID0, "HID0",
5753 SPR_NOACCESS, SPR_NOACCESS,
5754 &spr_read_generic, &spr_write_generic,
5755 0x00000000);
5756 /* XXX : not implemented */
5757 spr_register(env, SPR_HID1, "HID1",
5758 SPR_NOACCESS, SPR_NOACCESS,
5759 &spr_read_generic, &spr_write_generic,
5760 0x00000000);
5761 /* Memory management */
5762 gen_low_BATs(env);
5763 /* XXX: high BATs are also present but are known to be bugged on
5764 * die version 1.x
5765 */
5766 init_excp_7x0(env);
5767 env->dcache_line_size = 32;
5768 env->icache_line_size = 32;
5769 /* Allocate hardware IRQ controller */
5770 ppc6xx_irq_init(ppc_env_get_cpu(env));
5771 }
5772
5773 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5774 {
5775 DeviceClass *dc = DEVICE_CLASS(oc);
5776 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5777
5778 dc->desc = "PowerPC 750";
5779 pcc->init_proc = init_proc_750;
5780 pcc->check_pow = check_pow_hid0;
5781 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5782 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5783 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5784 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5785 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5786 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5787 PPC_SEGMENT | PPC_EXTERN;
5788 pcc->msr_mask = (1ull << MSR_POW) |
5789 (1ull << MSR_ILE) |
5790 (1ull << MSR_EE) |
5791 (1ull << MSR_PR) |
5792 (1ull << MSR_FP) |
5793 (1ull << MSR_ME) |
5794 (1ull << MSR_FE0) |
5795 (1ull << MSR_SE) |
5796 (1ull << MSR_DE) |
5797 (1ull << MSR_FE1) |
5798 (1ull << MSR_EP) |
5799 (1ull << MSR_IR) |
5800 (1ull << MSR_DR) |
5801 (1ull << MSR_PMM) |
5802 (1ull << MSR_RI) |
5803 (1ull << MSR_LE);
5804 pcc->mmu_model = POWERPC_MMU_32B;
5805 #if defined(CONFIG_SOFTMMU)
5806 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5807 #endif
5808 pcc->excp_model = POWERPC_EXCP_7x0;
5809 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5810 pcc->bfd_mach = bfd_mach_ppc_750;
5811 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5812 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5813 }
5814
5815 static void init_proc_750cl (CPUPPCState *env)
5816 {
5817 gen_spr_ne_601(env);
5818 gen_spr_7xx(env);
5819 /* XXX : not implemented */
5820 spr_register(env, SPR_L2CR, "L2CR",
5821 SPR_NOACCESS, SPR_NOACCESS,
5822 &spr_read_generic, spr_access_nop,
5823 0x00000000);
5824 /* Time base */
5825 gen_tbl(env);
5826 /* Thermal management */
5827 /* Those registers are fake on 750CL */
5828 spr_register(env, SPR_THRM1, "THRM1",
5829 SPR_NOACCESS, SPR_NOACCESS,
5830 &spr_read_generic, &spr_write_generic,
5831 0x00000000);
5832 spr_register(env, SPR_THRM2, "THRM2",
5833 SPR_NOACCESS, SPR_NOACCESS,
5834 &spr_read_generic, &spr_write_generic,
5835 0x00000000);
5836 spr_register(env, SPR_THRM3, "THRM3",
5837 SPR_NOACCESS, SPR_NOACCESS,
5838 &spr_read_generic, &spr_write_generic,
5839 0x00000000);
5840 /* XXX: not implemented */
5841 spr_register(env, SPR_750_TDCL, "TDCL",
5842 SPR_NOACCESS, SPR_NOACCESS,
5843 &spr_read_generic, &spr_write_generic,
5844 0x00000000);
5845 spr_register(env, SPR_750_TDCH, "TDCH",
5846 SPR_NOACCESS, SPR_NOACCESS,
5847 &spr_read_generic, &spr_write_generic,
5848 0x00000000);
5849 /* DMA */
5850 /* XXX : not implemented */
5851 spr_register(env, SPR_750_WPAR, "WPAR",
5852 SPR_NOACCESS, SPR_NOACCESS,
5853 &spr_read_generic, &spr_write_generic,
5854 0x00000000);
5855 spr_register(env, SPR_750_DMAL, "DMAL",
5856 SPR_NOACCESS, SPR_NOACCESS,
5857 &spr_read_generic, &spr_write_generic,
5858 0x00000000);
5859 spr_register(env, SPR_750_DMAU, "DMAU",
5860 SPR_NOACCESS, SPR_NOACCESS,
5861 &spr_read_generic, &spr_write_generic,
5862 0x00000000);
5863 /* Hardware implementation registers */
5864 /* XXX : not implemented */
5865 spr_register(env, SPR_HID0, "HID0",
5866 SPR_NOACCESS, SPR_NOACCESS,
5867 &spr_read_generic, &spr_write_generic,
5868 0x00000000);
5869 /* XXX : not implemented */
5870 spr_register(env, SPR_HID1, "HID1",
5871 SPR_NOACCESS, SPR_NOACCESS,
5872 &spr_read_generic, &spr_write_generic,
5873 0x00000000);
5874 /* XXX : not implemented */
5875 spr_register(env, SPR_750CL_HID2, "HID2",
5876 SPR_NOACCESS, SPR_NOACCESS,
5877 &spr_read_generic, &spr_write_generic,
5878 0x00000000);
5879 /* XXX : not implemented */
5880 spr_register(env, SPR_750CL_HID4, "HID4",
5881 SPR_NOACCESS, SPR_NOACCESS,
5882 &spr_read_generic, &spr_write_generic,
5883 0x00000000);
5884 /* Quantization registers */
5885 /* XXX : not implemented */
5886 spr_register(env, SPR_750_GQR0, "GQR0",
5887 SPR_NOACCESS, SPR_NOACCESS,
5888 &spr_read_generic, &spr_write_generic,
5889 0x00000000);
5890 /* XXX : not implemented */
5891 spr_register(env, SPR_750_GQR1, "GQR1",
5892 SPR_NOACCESS, SPR_NOACCESS,
5893 &spr_read_generic, &spr_write_generic,
5894 0x00000000);
5895 /* XXX : not implemented */
5896 spr_register(env, SPR_750_GQR2, "GQR2",
5897 SPR_NOACCESS, SPR_NOACCESS,
5898 &spr_read_generic, &spr_write_generic,
5899 0x00000000);
5900 /* XXX : not implemented */
5901 spr_register(env, SPR_750_GQR3, "GQR3",
5902 SPR_NOACCESS, SPR_NOACCESS,
5903 &spr_read_generic, &spr_write_generic,
5904 0x00000000);
5905 /* XXX : not implemented */
5906 spr_register(env, SPR_750_GQR4, "GQR4",
5907 SPR_NOACCESS, SPR_NOACCESS,
5908 &spr_read_generic, &spr_write_generic,
5909 0x00000000);
5910 /* XXX : not implemented */
5911 spr_register(env, SPR_750_GQR5, "GQR5",
5912 SPR_NOACCESS, SPR_NOACCESS,
5913 &spr_read_generic, &spr_write_generic,
5914 0x00000000);
5915 /* XXX : not implemented */
5916 spr_register(env, SPR_750_GQR6, "GQR6",
5917 SPR_NOACCESS, SPR_NOACCESS,
5918 &spr_read_generic, &spr_write_generic,
5919 0x00000000);
5920 /* XXX : not implemented */
5921 spr_register(env, SPR_750_GQR7, "GQR7",
5922 SPR_NOACCESS, SPR_NOACCESS,
5923 &spr_read_generic, &spr_write_generic,
5924 0x00000000);
5925 /* Memory management */
5926 gen_low_BATs(env);
5927 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5928 gen_high_BATs(env);
5929 init_excp_750cl(env);
5930 env->dcache_line_size = 32;
5931 env->icache_line_size = 32;
5932 /* Allocate hardware IRQ controller */
5933 ppc6xx_irq_init(ppc_env_get_cpu(env));
5934 }
5935
5936 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5937 {
5938 DeviceClass *dc = DEVICE_CLASS(oc);
5939 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5940
5941 dc->desc = "PowerPC 750 CL";
5942 pcc->init_proc = init_proc_750cl;
5943 pcc->check_pow = check_pow_hid0;
5944 /* XXX: not implemented:
5945 * cache lock instructions:
5946 * dcbz_l
5947 * floating point paired instructions
5948 * psq_lux
5949 * psq_lx
5950 * psq_stux
5951 * psq_stx
5952 * ps_abs
5953 * ps_add
5954 * ps_cmpo0
5955 * ps_cmpo1
5956 * ps_cmpu0
5957 * ps_cmpu1
5958 * ps_div
5959 * ps_madd
5960 * ps_madds0
5961 * ps_madds1
5962 * ps_merge00
5963 * ps_merge01
5964 * ps_merge10
5965 * ps_merge11
5966 * ps_mr
5967 * ps_msub
5968 * ps_mul
5969 * ps_muls0
5970 * ps_muls1
5971 * ps_nabs
5972 * ps_neg
5973 * ps_nmadd
5974 * ps_nmsub
5975 * ps_res
5976 * ps_rsqrte
5977 * ps_sel
5978 * ps_sub
5979 * ps_sum0
5980 * ps_sum1
5981 */
5982 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5983 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5984 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5985 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5986 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5987 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5988 PPC_SEGMENT | PPC_EXTERN;
5989 pcc->msr_mask = (1ull << MSR_POW) |
5990 (1ull << MSR_ILE) |
5991 (1ull << MSR_EE) |
5992 (1ull << MSR_PR) |
5993 (1ull << MSR_FP) |
5994 (1ull << MSR_ME) |
5995 (1ull << MSR_FE0) |
5996 (1ull << MSR_SE) |
5997 (1ull << MSR_DE) |
5998 (1ull << MSR_FE1) |
5999 (1ull << MSR_EP) |
6000 (1ull << MSR_IR) |
6001 (1ull << MSR_DR) |
6002 (1ull << MSR_PMM) |
6003 (1ull << MSR_RI) |
6004 (1ull << MSR_LE);
6005 pcc->mmu_model = POWERPC_MMU_32B;
6006 #if defined(CONFIG_SOFTMMU)
6007 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6008 #endif
6009 pcc->excp_model = POWERPC_EXCP_7x0;
6010 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6011 pcc->bfd_mach = bfd_mach_ppc_750;
6012 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6013 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6014 }
6015
6016 static void init_proc_750cx (CPUPPCState *env)
6017 {
6018 gen_spr_ne_601(env);
6019 gen_spr_7xx(env);
6020 /* XXX : not implemented */
6021 spr_register(env, SPR_L2CR, "L2CR",
6022 SPR_NOACCESS, SPR_NOACCESS,
6023 &spr_read_generic, spr_access_nop,
6024 0x00000000);
6025 /* Time base */
6026 gen_tbl(env);
6027 /* Thermal management */
6028 gen_spr_thrm(env);
6029 /* This register is not implemented but is present for compatibility */
6030 spr_register(env, SPR_SDA, "SDA",
6031 SPR_NOACCESS, SPR_NOACCESS,
6032 &spr_read_generic, &spr_write_generic,
6033 0x00000000);
6034 /* Hardware implementation registers */
6035 /* XXX : not implemented */
6036 spr_register(env, SPR_HID0, "HID0",
6037 SPR_NOACCESS, SPR_NOACCESS,
6038 &spr_read_generic, &spr_write_generic,
6039 0x00000000);
6040 /* XXX : not implemented */
6041 spr_register(env, SPR_HID1, "HID1",
6042 SPR_NOACCESS, SPR_NOACCESS,
6043 &spr_read_generic, &spr_write_generic,
6044 0x00000000);
6045 /* Memory management */
6046 gen_low_BATs(env);
6047 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
6048 gen_high_BATs(env);
6049 init_excp_750cx(env);
6050 env->dcache_line_size = 32;
6051 env->icache_line_size = 32;
6052 /* Allocate hardware IRQ controller */
6053 ppc6xx_irq_init(ppc_env_get_cpu(env));
6054 }
6055
6056 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
6057 {
6058 DeviceClass *dc = DEVICE_CLASS(oc);
6059 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6060
6061 dc->desc = "PowerPC 750CX";
6062 pcc->init_proc = init_proc_750cx;
6063 pcc->check_pow = check_pow_hid0;
6064 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6065 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6066 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6067 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6068 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6069 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6070 PPC_SEGMENT | PPC_EXTERN;
6071 pcc->msr_mask = (1ull << MSR_POW) |
6072 (1ull << MSR_ILE) |
6073 (1ull << MSR_EE) |
6074 (1ull << MSR_PR) |
6075 (1ull << MSR_FP) |
6076 (1ull << MSR_ME) |
6077 (1ull << MSR_FE0) |
6078 (1ull << MSR_SE) |
6079 (1ull << MSR_DE) |
6080 (1ull << MSR_FE1) |
6081 (1ull << MSR_EP) |
6082 (1ull << MSR_IR) |
6083 (1ull << MSR_DR) |
6084 (1ull << MSR_PMM) |
6085 (1ull << MSR_RI) |
6086 (1ull << MSR_LE);
6087 pcc->mmu_model = POWERPC_MMU_32B;
6088 #if defined(CONFIG_SOFTMMU)
6089 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6090 #endif
6091 pcc->excp_model = POWERPC_EXCP_7x0;
6092 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6093 pcc->bfd_mach = bfd_mach_ppc_750;
6094 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6095 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6096 }
6097
6098 static void init_proc_750fx (CPUPPCState *env)
6099 {
6100 gen_spr_ne_601(env);
6101 gen_spr_7xx(env);
6102 /* XXX : not implemented */
6103 spr_register(env, SPR_L2CR, "L2CR",
6104 SPR_NOACCESS, SPR_NOACCESS,
6105 &spr_read_generic, spr_access_nop,
6106 0x00000000);
6107 /* Time base */
6108 gen_tbl(env);
6109 /* Thermal management */
6110 gen_spr_thrm(env);
6111 /* XXX : not implemented */
6112 spr_register(env, SPR_750_THRM4, "THRM4",
6113 SPR_NOACCESS, SPR_NOACCESS,
6114 &spr_read_generic, &spr_write_generic,
6115 0x00000000);
6116 /* Hardware implementation registers */
6117 /* XXX : not implemented */
6118 spr_register(env, SPR_HID0, "HID0",
6119 SPR_NOACCESS, SPR_NOACCESS,
6120 &spr_read_generic, &spr_write_generic,
6121 0x00000000);
6122 /* XXX : not implemented */
6123 spr_register(env, SPR_HID1, "HID1",
6124 SPR_NOACCESS, SPR_NOACCESS,
6125 &spr_read_generic, &spr_write_generic,
6126 0x00000000);
6127 /* XXX : not implemented */
6128 spr_register(env, SPR_750FX_HID2, "HID2",
6129 SPR_NOACCESS, SPR_NOACCESS,
6130 &spr_read_generic, &spr_write_generic,
6131 0x00000000);
6132 /* Memory management */
6133 gen_low_BATs(env);
6134 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6135 gen_high_BATs(env);
6136 init_excp_7x0(env);
6137 env->dcache_line_size = 32;
6138 env->icache_line_size = 32;
6139 /* Allocate hardware IRQ controller */
6140 ppc6xx_irq_init(ppc_env_get_cpu(env));
6141 }
6142
6143 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
6144 {
6145 DeviceClass *dc = DEVICE_CLASS(oc);
6146 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6147
6148 dc->desc = "PowerPC 750FX";
6149 pcc->init_proc = init_proc_750fx;
6150 pcc->check_pow = check_pow_hid0;
6151 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6152 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6153 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6154 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6155 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6156 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6157 PPC_SEGMENT | PPC_EXTERN;
6158 pcc->msr_mask = (1ull << MSR_POW) |
6159 (1ull << MSR_ILE) |
6160 (1ull << MSR_EE) |
6161 (1ull << MSR_PR) |
6162 (1ull << MSR_FP) |
6163 (1ull << MSR_ME) |
6164 (1ull << MSR_FE0) |
6165 (1ull << MSR_SE) |
6166 (1ull << MSR_DE) |
6167 (1ull << MSR_FE1) |
6168 (1ull << MSR_EP) |
6169 (1ull << MSR_IR) |
6170 (1ull << MSR_DR) |
6171 (1ull << MSR_PMM) |
6172 (1ull << MSR_RI) |
6173 (1ull << MSR_LE);
6174 pcc->mmu_model = POWERPC_MMU_32B;
6175 #if defined(CONFIG_SOFTMMU)
6176 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6177 #endif
6178 pcc->excp_model = POWERPC_EXCP_7x0;
6179 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6180 pcc->bfd_mach = bfd_mach_ppc_750;
6181 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6182 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6183 }
6184
6185 static void init_proc_750gx (CPUPPCState *env)
6186 {
6187 gen_spr_ne_601(env);
6188 gen_spr_7xx(env);
6189 /* XXX : not implemented (XXX: different from 750fx) */
6190 spr_register(env, SPR_L2CR, "L2CR",
6191 SPR_NOACCESS, SPR_NOACCESS,
6192 &spr_read_generic, spr_access_nop,
6193 0x00000000);
6194 /* Time base */
6195 gen_tbl(env);
6196 /* Thermal management */
6197 gen_spr_thrm(env);
6198 /* XXX : not implemented */
6199 spr_register(env, SPR_750_THRM4, "THRM4",
6200 SPR_NOACCESS, SPR_NOACCESS,
6201 &spr_read_generic, &spr_write_generic,
6202 0x00000000);
6203 /* Hardware implementation registers */
6204 /* XXX : not implemented (XXX: different from 750fx) */
6205 spr_register(env, SPR_HID0, "HID0",
6206 SPR_NOACCESS, SPR_NOACCESS,
6207 &spr_read_generic, &spr_write_generic,
6208 0x00000000);
6209 /* XXX : not implemented */
6210 spr_register(env, SPR_HID1, "HID1",
6211 SPR_NOACCESS, SPR_NOACCESS,
6212 &spr_read_generic, &spr_write_generic,
6213 0x00000000);
6214 /* XXX : not implemented (XXX: different from 750fx) */
6215 spr_register(env, SPR_750FX_HID2, "HID2",
6216 SPR_NOACCESS, SPR_NOACCESS,
6217 &spr_read_generic, &spr_write_generic,
6218 0x00000000);
6219 /* Memory management */
6220 gen_low_BATs(env);
6221 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6222 gen_high_BATs(env);
6223 init_excp_7x0(env);
6224 env->dcache_line_size = 32;
6225 env->icache_line_size = 32;
6226 /* Allocate hardware IRQ controller */
6227 ppc6xx_irq_init(ppc_env_get_cpu(env));
6228 }
6229
6230 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
6231 {
6232 DeviceClass *dc = DEVICE_CLASS(oc);
6233 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6234
6235 dc->desc = "PowerPC 750GX";
6236 pcc->init_proc = init_proc_750gx;
6237 pcc->check_pow = check_pow_hid0;
6238 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6239 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6240 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6241 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6242 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6243 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6244 PPC_SEGMENT | PPC_EXTERN;
6245 pcc->msr_mask = (1ull << MSR_POW) |
6246 (1ull << MSR_ILE) |
6247 (1ull << MSR_EE) |
6248 (1ull << MSR_PR) |
6249 (1ull << MSR_FP) |
6250 (1ull << MSR_ME) |
6251 (1ull << MSR_FE0) |
6252 (1ull << MSR_SE) |
6253 (1ull << MSR_DE) |
6254 (1ull << MSR_FE1) |
6255 (1ull << MSR_EP) |
6256 (1ull << MSR_IR) |
6257 (1ull << MSR_DR) |
6258 (1ull << MSR_PMM) |
6259 (1ull << MSR_RI) |
6260 (1ull << MSR_LE);
6261 pcc->mmu_model = POWERPC_MMU_32B;
6262 #if defined(CONFIG_SOFTMMU)
6263 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6264 #endif
6265 pcc->excp_model = POWERPC_EXCP_7x0;
6266 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6267 pcc->bfd_mach = bfd_mach_ppc_750;
6268 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6269 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6270 }
6271
6272 static void init_proc_745 (CPUPPCState *env)
6273 {
6274 gen_spr_ne_601(env);
6275 gen_spr_7xx(env);
6276 gen_spr_G2_755(env);
6277 /* Time base */
6278 gen_tbl(env);
6279 /* Thermal management */
6280 gen_spr_thrm(env);
6281 /* Hardware implementation registers */
6282 /* XXX : not implemented */
6283 spr_register(env, SPR_HID0, "HID0",
6284 SPR_NOACCESS, SPR_NOACCESS,
6285 &spr_read_generic, &spr_write_generic,
6286 0x00000000);
6287 /* XXX : not implemented */
6288 spr_register(env, SPR_HID1, "HID1",
6289 SPR_NOACCESS, SPR_NOACCESS,
6290 &spr_read_generic, &spr_write_generic,
6291 0x00000000);
6292 /* XXX : not implemented */
6293 spr_register(env, SPR_HID2, "HID2",
6294 SPR_NOACCESS, SPR_NOACCESS,
6295 &spr_read_generic, &spr_write_generic,
6296 0x00000000);
6297 /* Memory management */
6298 gen_low_BATs(env);
6299 gen_high_BATs(env);
6300 gen_6xx_7xx_soft_tlb(env, 64, 2);
6301 init_excp_7x5(env);
6302 env->dcache_line_size = 32;
6303 env->icache_line_size = 32;
6304 /* Allocate hardware IRQ controller */
6305 ppc6xx_irq_init(ppc_env_get_cpu(env));
6306 }
6307
6308 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
6309 {
6310 DeviceClass *dc = DEVICE_CLASS(oc);
6311 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6312
6313 dc->desc = "PowerPC 745";
6314 pcc->init_proc = init_proc_745;
6315 pcc->check_pow = check_pow_hid0;
6316 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6317 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6318 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6319 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6320 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6321 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6322 PPC_SEGMENT | PPC_EXTERN;
6323 pcc->msr_mask = (1ull << MSR_POW) |
6324 (1ull << MSR_ILE) |
6325 (1ull << MSR_EE) |
6326 (1ull << MSR_PR) |
6327 (1ull << MSR_FP) |
6328 (1ull << MSR_ME) |
6329 (1ull << MSR_FE0) |
6330 (1ull << MSR_SE) |
6331 (1ull << MSR_DE) |
6332 (1ull << MSR_FE1) |
6333 (1ull << MSR_EP) |
6334 (1ull << MSR_IR) |
6335 (1ull << MSR_DR) |
6336 (1ull << MSR_PMM) |
6337 (1ull << MSR_RI) |
6338 (1ull << MSR_LE);
6339 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6340 pcc->excp_model = POWERPC_EXCP_7x5;
6341 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6342 pcc->bfd_mach = bfd_mach_ppc_750;
6343 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6344 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6345 }
6346
6347 static void init_proc_755 (CPUPPCState *env)
6348 {
6349 gen_spr_ne_601(env);
6350 gen_spr_7xx(env);
6351 gen_spr_G2_755(env);
6352 /* Time base */
6353 gen_tbl(env);
6354 /* L2 cache control */
6355 /* XXX : not implemented */
6356 spr_register(env, SPR_L2CR, "L2CR",
6357 SPR_NOACCESS, SPR_NOACCESS,
6358 &spr_read_generic, spr_access_nop,
6359 0x00000000);
6360 /* XXX : not implemented */
6361 spr_register(env, SPR_L2PMCR, "L2PMCR",
6362 SPR_NOACCESS, SPR_NOACCESS,
6363 &spr_read_generic, &spr_write_generic,
6364 0x00000000);
6365 /* Thermal management */
6366 gen_spr_thrm(env);
6367 /* Hardware implementation registers */
6368 /* XXX : not implemented */
6369 spr_register(env, SPR_HID0, "HID0",
6370 SPR_NOACCESS, SPR_NOACCESS,
6371 &spr_read_generic, &spr_write_generic,
6372 0x00000000);
6373 /* XXX : not implemented */
6374 spr_register(env, SPR_HID1, "HID1",
6375 SPR_NOACCESS, SPR_NOACCESS,
6376 &spr_read_generic, &spr_write_generic,
6377 0x00000000);
6378 /* XXX : not implemented */
6379 spr_register(env, SPR_HID2, "HID2",
6380 SPR_NOACCESS, SPR_NOACCESS,
6381 &spr_read_generic, &spr_write_generic,
6382 0x00000000);
6383 /* Memory management */
6384 gen_low_BATs(env);
6385 gen_high_BATs(env);
6386 gen_6xx_7xx_soft_tlb(env, 64, 2);
6387 init_excp_7x5(env);
6388 env->dcache_line_size = 32;
6389 env->icache_line_size = 32;
6390 /* Allocate hardware IRQ controller */
6391 ppc6xx_irq_init(ppc_env_get_cpu(env));
6392 }
6393
6394 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
6395 {
6396 DeviceClass *dc = DEVICE_CLASS(oc);
6397 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6398
6399 dc->desc = "PowerPC 755";
6400 pcc->init_proc = init_proc_755;
6401 pcc->check_pow = check_pow_hid0;
6402 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6403 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6404 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6405 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6406 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6407 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6408 PPC_SEGMENT | PPC_EXTERN;
6409 pcc->msr_mask = (1ull << MSR_POW) |
6410 (1ull << MSR_ILE) |
6411 (1ull << MSR_EE) |
6412 (1ull << MSR_PR) |
6413 (1ull << MSR_FP) |
6414 (1ull << MSR_ME) |
6415 (1ull << MSR_FE0) |
6416 (1ull << MSR_SE) |
6417 (1ull << MSR_DE) |
6418 (1ull << MSR_FE1) |
6419 (1ull << MSR_EP) |
6420 (1ull << MSR_IR) |
6421 (1ull << MSR_DR) |
6422 (1ull << MSR_PMM) |
6423 (1ull << MSR_RI) |
6424 (1ull << MSR_LE);
6425 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6426 pcc->excp_model = POWERPC_EXCP_7x5;
6427 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6428 pcc->bfd_mach = bfd_mach_ppc_750;
6429 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6430 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6431 }
6432
6433 static void init_proc_7400 (CPUPPCState *env)
6434 {
6435 gen_spr_ne_601(env);
6436 gen_spr_7xx(env);
6437 /* Time base */
6438 gen_tbl(env);
6439 /* 74xx specific SPR */
6440 gen_spr_74xx(env);
6441 /* XXX : not implemented */
6442 spr_register(env, SPR_UBAMR, "UBAMR",
6443 &spr_read_ureg, SPR_NOACCESS,
6444 &spr_read_ureg, SPR_NOACCESS,
6445 0x00000000);
6446 /* XXX: this seems not implemented on all revisions. */
6447 /* XXX : not implemented */
6448 spr_register(env, SPR_MSSCR1, "MSSCR1",
6449 SPR_NOACCESS, SPR_NOACCESS,
6450 &spr_read_generic, &spr_write_generic,
6451 0x00000000);
6452 /* Thermal management */
6453 gen_spr_thrm(env);
6454 /* Memory management */
6455 gen_low_BATs(env);
6456 init_excp_7400(env);
6457 env->dcache_line_size = 32;
6458 env->icache_line_size = 32;
6459 /* Allocate hardware IRQ controller */
6460 ppc6xx_irq_init(ppc_env_get_cpu(env));
6461 }
6462
6463 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
6464 {
6465 DeviceClass *dc = DEVICE_CLASS(oc);
6466 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6467
6468 dc->desc = "PowerPC 7400 (aka G4)";
6469 pcc->init_proc = init_proc_7400;
6470 pcc->check_pow = check_pow_hid0;
6471 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6472 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6473 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6474 PPC_FLOAT_STFIWX |
6475 PPC_CACHE | PPC_CACHE_ICBI |
6476 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6477 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6478 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6479 PPC_MEM_TLBIA |
6480 PPC_SEGMENT | PPC_EXTERN |
6481 PPC_ALTIVEC;
6482 pcc->msr_mask = (1ull << MSR_VR) |
6483 (1ull << MSR_POW) |
6484 (1ull << MSR_ILE) |
6485 (1ull << MSR_EE) |
6486 (1ull << MSR_PR) |
6487 (1ull << MSR_FP) |
6488 (1ull << MSR_ME) |
6489 (1ull << MSR_FE0) |
6490 (1ull << MSR_SE) |
6491 (1ull << MSR_DE) |
6492 (1ull << MSR_FE1) |
6493 (1ull << MSR_EP) |
6494 (1ull << MSR_IR) |
6495 (1ull << MSR_DR) |
6496 (1ull << MSR_PMM) |
6497 (1ull << MSR_RI) |
6498 (1ull << MSR_LE);
6499 pcc->mmu_model = POWERPC_MMU_32B;
6500 #if defined(CONFIG_SOFTMMU)
6501 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6502 #endif
6503 pcc->excp_model = POWERPC_EXCP_74xx;
6504 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6505 pcc->bfd_mach = bfd_mach_ppc_7400;
6506 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6507 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6508 POWERPC_FLAG_BUS_CLK;
6509 }
6510
6511 static void init_proc_7410 (CPUPPCState *env)
6512 {
6513 gen_spr_ne_601(env);
6514 gen_spr_7xx(env);
6515 /* Time base */
6516 gen_tbl(env);
6517 /* 74xx specific SPR */
6518 gen_spr_74xx(env);
6519 /* XXX : not implemented */
6520 spr_register(env, SPR_UBAMR, "UBAMR",
6521 &spr_read_ureg, SPR_NOACCESS,
6522 &spr_read_ureg, SPR_NOACCESS,
6523 0x00000000);
6524 /* Thermal management */
6525 gen_spr_thrm(env);
6526 /* L2PMCR */
6527 /* XXX : not implemented */
6528 spr_register(env, SPR_L2PMCR, "L2PMCR",
6529 SPR_NOACCESS, SPR_NOACCESS,
6530 &spr_read_generic, &spr_write_generic,
6531 0x00000000);
6532 /* LDSTDB */
6533 /* XXX : not implemented */
6534 spr_register(env, SPR_LDSTDB, "LDSTDB",
6535 SPR_NOACCESS, SPR_NOACCESS,
6536 &spr_read_generic, &spr_write_generic,
6537 0x00000000);
6538 /* Memory management */
6539 gen_low_BATs(env);
6540 init_excp_7400(env);
6541 env->dcache_line_size = 32;
6542 env->icache_line_size = 32;
6543 /* Allocate hardware IRQ controller */
6544 ppc6xx_irq_init(ppc_env_get_cpu(env));
6545 }
6546
6547 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
6548 {
6549 DeviceClass *dc = DEVICE_CLASS(oc);
6550 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6551
6552 dc->desc = "PowerPC 7410 (aka G4)";
6553 pcc->init_proc = init_proc_7410;
6554 pcc->check_pow = check_pow_hid0;
6555 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6556 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6557 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6558 PPC_FLOAT_STFIWX |
6559 PPC_CACHE | PPC_CACHE_ICBI |
6560 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6561 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6562 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6563 PPC_MEM_TLBIA |
6564 PPC_SEGMENT | PPC_EXTERN |
6565 PPC_ALTIVEC;
6566 pcc->msr_mask = (1ull << MSR_VR) |
6567 (1ull << MSR_POW) |
6568 (1ull << MSR_ILE) |
6569 (1ull << MSR_EE) |
6570 (1ull << MSR_PR) |
6571 (1ull << MSR_FP) |
6572 (1ull << MSR_ME) |
6573 (1ull << MSR_FE0) |
6574 (1ull << MSR_SE) |
6575 (1ull << MSR_DE) |
6576 (1ull << MSR_FE1) |
6577 (1ull << MSR_EP) |
6578 (1ull << MSR_IR) |
6579 (1ull << MSR_DR) |
6580 (1ull << MSR_PMM) |
6581 (1ull << MSR_RI) |
6582 (1ull << MSR_LE);
6583 pcc->mmu_model = POWERPC_MMU_32B;
6584 #if defined(CONFIG_SOFTMMU)
6585 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6586 #endif
6587 pcc->excp_model = POWERPC_EXCP_74xx;
6588 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6589 pcc->bfd_mach = bfd_mach_ppc_7400;
6590 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6591 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6592 POWERPC_FLAG_BUS_CLK;
6593 }
6594
6595 static void init_proc_7440 (CPUPPCState *env)
6596 {
6597 gen_spr_ne_601(env);
6598 gen_spr_7xx(env);
6599 /* Time base */
6600 gen_tbl(env);
6601 /* 74xx specific SPR */
6602 gen_spr_74xx(env);
6603 /* XXX : not implemented */
6604 spr_register(env, SPR_UBAMR, "UBAMR",
6605 &spr_read_ureg, SPR_NOACCESS,
6606 &spr_read_ureg, SPR_NOACCESS,
6607 0x00000000);
6608 /* LDSTCR */
6609 /* XXX : not implemented */
6610 spr_register(env, SPR_LDSTCR, "LDSTCR",
6611 SPR_NOACCESS, SPR_NOACCESS,
6612 &spr_read_generic, &spr_write_generic,
6613 0x00000000);
6614 /* ICTRL */
6615 /* XXX : not implemented */
6616 spr_register(env, SPR_ICTRL, "ICTRL",
6617 SPR_NOACCESS, SPR_NOACCESS,
6618 &spr_read_generic, &spr_write_generic,
6619 0x00000000);
6620 /* MSSSR0 */
6621 /* XXX : not implemented */
6622 spr_register(env, SPR_MSSSR0, "MSSSR0",
6623 SPR_NOACCESS, SPR_NOACCESS,
6624 &spr_read_generic, &spr_write_generic,
6625 0x00000000);
6626 /* PMC */
6627 /* XXX : not implemented */
6628 spr_register(env, SPR_7XX_PMC5, "PMC5",
6629 SPR_NOACCESS, SPR_NOACCESS,
6630 &spr_read_generic, &spr_write_generic,
6631 0x00000000);
6632 /* XXX : not implemented */
6633 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6634 &spr_read_ureg, SPR_NOACCESS,
6635 &spr_read_ureg, SPR_NOACCESS,
6636 0x00000000);
6637 /* XXX : not implemented */
6638 spr_register(env, SPR_7XX_PMC6, "PMC6",
6639 SPR_NOACCESS, SPR_NOACCESS,
6640 &spr_read_generic, &spr_write_generic,
6641 0x00000000);
6642 /* XXX : not implemented */
6643 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6644 &spr_read_ureg, SPR_NOACCESS,
6645 &spr_read_ureg, SPR_NOACCESS,
6646 0x00000000);
6647 /* Memory management */
6648 gen_low_BATs(env);
6649 gen_74xx_soft_tlb(env, 128, 2);
6650 init_excp_7450(env);
6651 env->dcache_line_size = 32;
6652 env->icache_line_size = 32;
6653 /* Allocate hardware IRQ controller */
6654 ppc6xx_irq_init(ppc_env_get_cpu(env));
6655 }
6656
6657 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
6658 {
6659 DeviceClass *dc = DEVICE_CLASS(oc);
6660 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6661
6662 dc->desc = "PowerPC 7440 (aka G4)";
6663 pcc->init_proc = init_proc_7440;
6664 pcc->check_pow = check_pow_hid0_74xx;
6665 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6666 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6667 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6668 PPC_FLOAT_STFIWX |
6669 PPC_CACHE | PPC_CACHE_ICBI |
6670 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6671 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6672 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6673 PPC_MEM_TLBIA | PPC_74xx_TLB |
6674 PPC_SEGMENT | PPC_EXTERN |
6675 PPC_ALTIVEC;
6676 pcc->msr_mask = (1ull << MSR_VR) |
6677 (1ull << MSR_POW) |
6678 (1ull << MSR_ILE) |
6679 (1ull << MSR_EE) |
6680 (1ull << MSR_PR) |
6681 (1ull << MSR_FP) |
6682 (1ull << MSR_ME) |
6683 (1ull << MSR_FE0) |
6684 (1ull << MSR_SE) |
6685 (1ull << MSR_DE) |
6686 (1ull << MSR_FE1) |
6687 (1ull << MSR_EP) |
6688 (1ull << MSR_IR) |
6689 (1ull << MSR_DR) |
6690 (1ull << MSR_PMM) |
6691 (1ull << MSR_RI) |
6692 (1ull << MSR_LE);
6693 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6694 pcc->excp_model = POWERPC_EXCP_74xx;
6695 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6696 pcc->bfd_mach = bfd_mach_ppc_7400;
6697 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6698 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6699 POWERPC_FLAG_BUS_CLK;
6700 }
6701
6702 static void init_proc_7450 (CPUPPCState *env)
6703 {
6704 gen_spr_ne_601(env);
6705 gen_spr_7xx(env);
6706 /* Time base */
6707 gen_tbl(env);
6708 /* 74xx specific SPR */
6709 gen_spr_74xx(env);
6710 /* Level 3 cache control */
6711 gen_l3_ctrl(env);
6712 /* L3ITCR1 */
6713 /* XXX : not implemented */
6714 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6715 SPR_NOACCESS, SPR_NOACCESS,
6716 &spr_read_generic, &spr_write_generic,
6717 0x00000000);
6718 /* L3ITCR2 */
6719 /* XXX : not implemented */
6720 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6721 SPR_NOACCESS, SPR_NOACCESS,
6722 &spr_read_generic, &spr_write_generic,
6723 0x00000000);
6724 /* L3ITCR3 */
6725 /* XXX : not implemented */
6726 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6727 SPR_NOACCESS, SPR_NOACCESS,
6728 &spr_read_generic, &spr_write_generic,
6729 0x00000000);
6730 /* L3OHCR */
6731 /* XXX : not implemented */
6732 spr_register(env, SPR_L3OHCR, "L3OHCR",
6733 SPR_NOACCESS, SPR_NOACCESS,
6734 &spr_read_generic, &spr_write_generic,
6735 0x00000000);
6736 /* XXX : not implemented */
6737 spr_register(env, SPR_UBAMR, "UBAMR",
6738 &spr_read_ureg, SPR_NOACCESS,
6739 &spr_read_ureg, SPR_NOACCESS,
6740 0x00000000);
6741 /* LDSTCR */
6742 /* XXX : not implemented */
6743 spr_register(env, SPR_LDSTCR, "LDSTCR",
6744 SPR_NOACCESS, SPR_NOACCESS,
6745 &spr_read_generic, &spr_write_generic,
6746 0x00000000);
6747 /* ICTRL */
6748 /* XXX : not implemented */
6749 spr_register(env, SPR_ICTRL, "ICTRL",
6750 SPR_NOACCESS, SPR_NOACCESS,
6751 &spr_read_generic, &spr_write_generic,
6752 0x00000000);
6753 /* MSSSR0 */
6754 /* XXX : not implemented */
6755 spr_register(env, SPR_MSSSR0, "MSSSR0",
6756 SPR_NOACCESS, SPR_NOACCESS,
6757 &spr_read_generic, &spr_write_generic,
6758 0x00000000);
6759 /* PMC */
6760 /* XXX : not implemented */
6761 spr_register(env, SPR_7XX_PMC5, "PMC5",
6762 SPR_NOACCESS, SPR_NOACCESS,
6763 &spr_read_generic, &spr_write_generic,
6764 0x00000000);
6765 /* XXX : not implemented */
6766 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6767 &spr_read_ureg, SPR_NOACCESS,
6768 &spr_read_ureg, SPR_NOACCESS,
6769 0x00000000);
6770 /* XXX : not implemented */
6771 spr_register(env, SPR_7XX_PMC6, "PMC6",
6772 SPR_NOACCESS, SPR_NOACCESS,
6773 &spr_read_generic, &spr_write_generic,
6774 0x00000000);
6775 /* XXX : not implemented */
6776 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6777 &spr_read_ureg, SPR_NOACCESS,
6778 &spr_read_ureg, SPR_NOACCESS,
6779 0x00000000);
6780 /* Memory management */
6781 gen_low_BATs(env);
6782 gen_74xx_soft_tlb(env, 128, 2);
6783 init_excp_7450(env);
6784 env->dcache_line_size = 32;
6785 env->icache_line_size = 32;
6786 /* Allocate hardware IRQ controller */
6787 ppc6xx_irq_init(ppc_env_get_cpu(env));
6788 }
6789
6790 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6791 {
6792 DeviceClass *dc = DEVICE_CLASS(oc);
6793 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6794
6795 dc->desc = "PowerPC 7450 (aka G4)";
6796 pcc->init_proc = init_proc_7450;
6797 pcc->check_pow = check_pow_hid0_74xx;
6798 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6799 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6800 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6801 PPC_FLOAT_STFIWX |
6802 PPC_CACHE | PPC_CACHE_ICBI |
6803 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6804 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6805 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6806 PPC_MEM_TLBIA | PPC_74xx_TLB |
6807 PPC_SEGMENT | PPC_EXTERN |
6808 PPC_ALTIVEC;
6809 pcc->msr_mask = (1ull << MSR_VR) |
6810 (1ull << MSR_POW) |
6811 (1ull << MSR_ILE) |
6812 (1ull << MSR_EE) |
6813 (1ull << MSR_PR) |
6814 (1ull << MSR_FP) |
6815 (1ull << MSR_ME) |
6816 (1ull << MSR_FE0) |
6817 (1ull << MSR_SE) |
6818 (1ull << MSR_DE) |
6819 (1ull << MSR_FE1) |
6820 (1ull << MSR_EP) |
6821 (1ull << MSR_IR) |
6822 (1ull << MSR_DR) |
6823 (1ull << MSR_PMM) |
6824 (1ull << MSR_RI) |
6825 (1ull << MSR_LE);
6826 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6827 pcc->excp_model = POWERPC_EXCP_74xx;
6828 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6829 pcc->bfd_mach = bfd_mach_ppc_7400;
6830 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6831 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6832 POWERPC_FLAG_BUS_CLK;
6833 }
6834
6835 static void init_proc_7445 (CPUPPCState *env)
6836 {
6837 gen_spr_ne_601(env);
6838 gen_spr_7xx(env);
6839 /* Time base */
6840 gen_tbl(env);
6841 /* 74xx specific SPR */
6842 gen_spr_74xx(env);
6843 /* LDSTCR */
6844 /* XXX : not implemented */
6845 spr_register(env, SPR_LDSTCR, "LDSTCR",
6846 SPR_NOACCESS, SPR_NOACCESS,
6847 &spr_read_generic, &spr_write_generic,
6848 0x00000000);
6849 /* ICTRL */
6850 /* XXX : not implemented */
6851 spr_register(env, SPR_ICTRL, "ICTRL",
6852 SPR_NOACCESS, SPR_NOACCESS,
6853 &spr_read_generic, &spr_write_generic,
6854 0x00000000);
6855 /* MSSSR0 */
6856 /* XXX : not implemented */
6857 spr_register(env, SPR_MSSSR0, "MSSSR0",
6858 SPR_NOACCESS, SPR_NOACCESS,
6859 &spr_read_generic, &spr_write_generic,
6860 0x00000000);
6861 /* PMC */
6862 /* XXX : not implemented */
6863 spr_register(env, SPR_7XX_PMC5, "PMC5",
6864 SPR_NOACCESS, SPR_NOACCESS,
6865 &spr_read_generic, &spr_write_generic,
6866 0x00000000);
6867 /* XXX : not implemented */
6868 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6869 &spr_read_ureg, SPR_NOACCESS,
6870 &spr_read_ureg, SPR_NOACCESS,
6871 0x00000000);
6872 /* XXX : not implemented */
6873 spr_register(env, SPR_7XX_PMC6, "PMC6",
6874 SPR_NOACCESS, SPR_NOACCESS,
6875 &spr_read_generic, &spr_write_generic,
6876 0x00000000);
6877 /* XXX : not implemented */
6878 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6879 &spr_read_ureg, SPR_NOACCESS,
6880 &spr_read_ureg, SPR_NOACCESS,
6881 0x00000000);
6882 /* SPRGs */
6883 spr_register(env, SPR_SPRG4, "SPRG4",
6884 SPR_NOACCESS, SPR_NOACCESS,
6885 &spr_read_generic, &spr_write_generic,
6886 0x00000000);
6887 spr_register(env, SPR_USPRG4, "USPRG4",
6888 &spr_read_ureg, SPR_NOACCESS,
6889 &spr_read_ureg, SPR_NOACCESS,
6890 0x00000000);
6891 spr_register(env, SPR_SPRG5, "SPRG5",
6892 SPR_NOACCESS, SPR_NOACCESS,
6893 &spr_read_generic, &spr_write_generic,
6894 0x00000000);
6895 spr_register(env, SPR_USPRG5, "USPRG5",
6896 &spr_read_ureg, SPR_NOACCESS,
6897 &spr_read_ureg, SPR_NOACCESS,
6898 0x00000000);
6899 spr_register(env, SPR_SPRG6, "SPRG6",
6900 SPR_NOACCESS, SPR_NOACCESS,
6901 &spr_read_generic, &spr_write_generic,
6902 0x00000000);
6903 spr_register(env, SPR_USPRG6, "USPRG6",
6904 &spr_read_ureg, SPR_NOACCESS,
6905 &spr_read_ureg, SPR_NOACCESS,
6906 0x00000000);
6907 spr_register(env, SPR_SPRG7, "SPRG7",
6908 SPR_NOACCESS, SPR_NOACCESS,
6909 &spr_read_generic, &spr_write_generic,
6910 0x00000000);
6911 spr_register(env, SPR_USPRG7, "USPRG7",
6912 &spr_read_ureg, SPR_NOACCESS,
6913 &spr_read_ureg, SPR_NOACCESS,
6914 0x00000000);
6915 /* Memory management */
6916 gen_low_BATs(env);
6917 gen_high_BATs(env);
6918 gen_74xx_soft_tlb(env, 128, 2);
6919 init_excp_7450(env);
6920 env->dcache_line_size = 32;
6921 env->icache_line_size = 32;
6922 /* Allocate hardware IRQ controller */
6923 ppc6xx_irq_init(ppc_env_get_cpu(env));
6924 }
6925
6926 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6927 {
6928 DeviceClass *dc = DEVICE_CLASS(oc);
6929 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6930
6931 dc->desc = "PowerPC 7445 (aka G4)";
6932 pcc->init_proc = init_proc_7445;
6933 pcc->check_pow = check_pow_hid0_74xx;
6934 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6935 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6936 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6937 PPC_FLOAT_STFIWX |
6938 PPC_CACHE | PPC_CACHE_ICBI |
6939 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6940 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6941 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6942 PPC_MEM_TLBIA | PPC_74xx_TLB |
6943 PPC_SEGMENT | PPC_EXTERN |
6944 PPC_ALTIVEC;
6945 pcc->msr_mask = (1ull << MSR_VR) |
6946 (1ull << MSR_POW) |
6947 (1ull << MSR_ILE) |
6948 (1ull << MSR_EE) |
6949 (1ull << MSR_PR) |
6950 (1ull << MSR_FP) |
6951 (1ull << MSR_ME) |
6952 (1ull << MSR_FE0) |
6953 (1ull << MSR_SE) |
6954 (1ull << MSR_DE) |
6955 (1ull << MSR_FE1) |
6956 (1ull << MSR_EP) |
6957 (1ull << MSR_IR) |
6958 (1ull << MSR_DR) |
6959 (1ull << MSR_PMM) |
6960 (1ull << MSR_RI) |
6961 (1ull << MSR_LE);
6962 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6963 pcc->excp_model = POWERPC_EXCP_74xx;
6964 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6965 pcc->bfd_mach = bfd_mach_ppc_7400;
6966 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6967 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6968 POWERPC_FLAG_BUS_CLK;
6969 }
6970
6971 static void init_proc_7455 (CPUPPCState *env)
6972 {
6973 gen_spr_ne_601(env);
6974 gen_spr_7xx(env);
6975 /* Time base */
6976 gen_tbl(env);
6977 /* 74xx specific SPR */
6978 gen_spr_74xx(env);
6979 /* Level 3 cache control */
6980 gen_l3_ctrl(env);
6981 /* LDSTCR */
6982 /* XXX : not implemented */
6983 spr_register(env, SPR_LDSTCR, "LDSTCR",
6984 SPR_NOACCESS, SPR_NOACCESS,
6985 &spr_read_generic, &spr_write_generic,
6986 0x00000000);
6987 /* ICTRL */
6988 /* XXX : not implemented */
6989 spr_register(env, SPR_ICTRL, "ICTRL",
6990 SPR_NOACCESS, SPR_NOACCESS,
6991 &spr_read_generic, &spr_write_generic,
6992 0x00000000);
6993 /* MSSSR0 */
6994 /* XXX : not implemented */
6995 spr_register(env, SPR_MSSSR0, "MSSSR0",
6996 SPR_NOACCESS, SPR_NOACCESS,
6997 &spr_read_generic, &spr_write_generic,
6998 0x00000000);
6999 /* PMC */
7000 /* XXX : not implemented */
7001 spr_register(env, SPR_7XX_PMC5, "PMC5",
7002 SPR_NOACCESS, SPR_NOACCESS,
7003 &spr_read_generic, &spr_write_generic,
7004 0x00000000);
7005 /* XXX : not implemented */
7006 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7007 &spr_read_ureg, SPR_NOACCESS,
7008 &spr_read_ureg, SPR_NOACCESS,
7009 0x00000000);
7010 /* XXX : not implemented */
7011 spr_register(env, SPR_7XX_PMC6, "PMC6",
7012 SPR_NOACCESS, SPR_NOACCESS,
7013 &spr_read_generic, &spr_write_generic,
7014 0x00000000);
7015 /* XXX : not implemented */
7016 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7017 &spr_read_ureg, SPR_NOACCESS,
7018 &spr_read_ureg, SPR_NOACCESS,
7019 0x00000000);
7020 /* SPRGs */
7021 spr_register(env, SPR_SPRG4, "SPRG4",
7022 SPR_NOACCESS, SPR_NOACCESS,
7023 &spr_read_generic, &spr_write_generic,
7024 0x00000000);
7025 spr_register(env, SPR_USPRG4, "USPRG4",
7026 &spr_read_ureg, SPR_NOACCESS,
7027 &spr_read_ureg, SPR_NOACCESS,
7028 0x00000000);
7029 spr_register(env, SPR_SPRG5, "SPRG5",
7030 SPR_NOACCESS, SPR_NOACCESS,
7031 &spr_read_generic, &spr_write_generic,
7032 0x00000000);
7033 spr_register(env, SPR_USPRG5, "USPRG5",
7034 &spr_read_ureg, SPR_NOACCESS,
7035 &spr_read_ureg, SPR_NOACCESS,
7036 0x00000000);
7037 spr_register(env, SPR_SPRG6, "SPRG6",
7038 SPR_NOACCESS, SPR_NOACCESS,
7039 &spr_read_generic, &spr_write_generic,
7040 0x00000000);
7041 spr_register(env, SPR_USPRG6, "USPRG6",
7042 &spr_read_ureg, SPR_NOACCESS,
7043 &spr_read_ureg, SPR_NOACCESS,
7044 0x00000000);
7045 spr_register(env, SPR_SPRG7, "SPRG7",
7046 SPR_NOACCESS, SPR_NOACCESS,
7047 &spr_read_generic, &spr_write_generic,
7048 0x00000000);
7049 spr_register(env, SPR_USPRG7, "USPRG7",
7050 &spr_read_ureg, SPR_NOACCESS,
7051 &spr_read_ureg, SPR_NOACCESS,
7052 0x00000000);
7053 /* Memory management */
7054 gen_low_BATs(env);
7055 gen_high_BATs(env);
7056 gen_74xx_soft_tlb(env, 128, 2);
7057 init_excp_7450(env);
7058 env->dcache_line_size = 32;
7059 env->icache_line_size = 32;
7060 /* Allocate hardware IRQ controller */
7061 ppc6xx_irq_init(ppc_env_get_cpu(env));
7062 }
7063
7064 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
7065 {
7066 DeviceClass *dc = DEVICE_CLASS(oc);
7067 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7068
7069 dc->desc = "PowerPC 7455 (aka G4)";
7070 pcc->init_proc = init_proc_7455;
7071 pcc->check_pow = check_pow_hid0_74xx;
7072 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7073 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7074 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7075 PPC_FLOAT_STFIWX |
7076 PPC_CACHE | PPC_CACHE_ICBI |
7077 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7078 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7079 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7080 PPC_MEM_TLBIA | PPC_74xx_TLB |
7081 PPC_SEGMENT | PPC_EXTERN |
7082 PPC_ALTIVEC;
7083 pcc->msr_mask = (1ull << MSR_VR) |
7084 (1ull << MSR_POW) |
7085 (1ull << MSR_ILE) |
7086 (1ull << MSR_EE) |
7087 (1ull << MSR_PR) |
7088 (1ull << MSR_FP) |
7089 (1ull << MSR_ME) |
7090 (1ull << MSR_FE0) |
7091 (1ull << MSR_SE) |
7092 (1ull << MSR_DE) |
7093 (1ull << MSR_FE1) |
7094 (1ull << MSR_EP) |
7095 (1ull << MSR_IR) |
7096 (1ull << MSR_DR) |
7097 (1ull << MSR_PMM) |
7098 (1ull << MSR_RI) |
7099 (1ull << MSR_LE);
7100 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7101 pcc->excp_model = POWERPC_EXCP_74xx;
7102 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7103 pcc->bfd_mach = bfd_mach_ppc_7400;
7104 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7105 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7106 POWERPC_FLAG_BUS_CLK;
7107 }
7108
7109 static void init_proc_7457 (CPUPPCState *env)
7110 {
7111 gen_spr_ne_601(env);
7112 gen_spr_7xx(env);
7113 /* Time base */
7114 gen_tbl(env);
7115 /* 74xx specific SPR */
7116 gen_spr_74xx(env);
7117 /* Level 3 cache control */
7118 gen_l3_ctrl(env);
7119 /* L3ITCR1 */
7120 /* XXX : not implemented */
7121 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
7122 SPR_NOACCESS, SPR_NOACCESS,
7123 &spr_read_generic, &spr_write_generic,
7124 0x00000000);
7125 /* L3ITCR2 */
7126 /* XXX : not implemented */
7127 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
7128 SPR_NOACCESS, SPR_NOACCESS,
7129 &spr_read_generic, &spr_write_generic,
7130 0x00000000);
7131 /* L3ITCR3 */
7132 /* XXX : not implemented */
7133 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
7134 SPR_NOACCESS, SPR_NOACCESS,
7135 &spr_read_generic, &spr_write_generic,
7136 0x00000000);
7137 /* L3OHCR */
7138 /* XXX : not implemented */
7139 spr_register(env, SPR_L3OHCR, "L3OHCR",
7140 SPR_NOACCESS, SPR_NOACCESS,
7141 &spr_read_generic, &spr_write_generic,
7142 0x00000000);
7143 /* LDSTCR */
7144 /* XXX : not implemented */
7145 spr_register(env, SPR_LDSTCR, "LDSTCR",
7146 SPR_NOACCESS, SPR_NOACCESS,
7147 &spr_read_generic, &spr_write_generic,
7148 0x00000000);
7149 /* ICTRL */
7150 /* XXX : not implemented */
7151 spr_register(env, SPR_ICTRL, "ICTRL",
7152 SPR_NOACCESS, SPR_NOACCESS,
7153 &spr_read_generic, &spr_write_generic,
7154 0x00000000);
7155 /* MSSSR0 */
7156 /* XXX : not implemented */
7157 spr_register(env, SPR_MSSSR0, "MSSSR0",
7158 SPR_NOACCESS, SPR_NOACCESS,
7159 &spr_read_generic, &spr_write_generic,
7160 0x00000000);
7161 /* PMC */
7162 /* XXX : not implemented */
7163 spr_register(env, SPR_7XX_PMC5, "PMC5",
7164 SPR_NOACCESS, SPR_NOACCESS,
7165 &spr_read_generic, &spr_write_generic,
7166 0x00000000);
7167 /* XXX : not implemented */
7168 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7169 &spr_read_ureg, SPR_NOACCESS,
7170 &spr_read_ureg, SPR_NOACCESS,
7171 0x00000000);
7172 /* XXX : not implemented */
7173 spr_register(env, SPR_7XX_PMC6, "PMC6",
7174 SPR_NOACCESS, SPR_NOACCESS,
7175 &spr_read_generic, &spr_write_generic,
7176 0x00000000);
7177 /* XXX : not implemented */
7178 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7179 &spr_read_ureg, SPR_NOACCESS,
7180 &spr_read_ureg, SPR_NOACCESS,
7181 0x00000000);
7182 /* SPRGs */
7183 spr_register(env, SPR_SPRG4, "SPRG4",
7184 SPR_NOACCESS, SPR_NOACCESS,
7185 &spr_read_generic, &spr_write_generic,
7186 0x00000000);
7187 spr_register(env, SPR_USPRG4, "USPRG4",
7188 &spr_read_ureg, SPR_NOACCESS,
7189 &spr_read_ureg, SPR_NOACCESS,
7190 0x00000000);
7191 spr_register(env, SPR_SPRG5, "SPRG5",
7192 SPR_NOACCESS, SPR_NOACCESS,
7193 &spr_read_generic, &spr_write_generic,
7194 0x00000000);
7195 spr_register(env, SPR_USPRG5, "USPRG5",
7196 &spr_read_ureg, SPR_NOACCESS,
7197 &spr_read_ureg, SPR_NOACCESS,
7198 0x00000000);
7199 spr_register(env, SPR_SPRG6, "SPRG6",
7200 SPR_NOACCESS, SPR_NOACCESS,
7201 &spr_read_generic, &spr_write_generic,
7202 0x00000000);
7203 spr_register(env, SPR_USPRG6, "USPRG6",
7204 &spr_read_ureg, SPR_NOACCESS,
7205 &spr_read_ureg, SPR_NOACCESS,
7206 0x00000000);
7207 spr_register(env, SPR_SPRG7, "SPRG7",
7208 SPR_NOACCESS, SPR_NOACCESS,
7209 &spr_read_generic, &spr_write_generic,
7210 0x00000000);
7211 spr_register(env, SPR_USPRG7, "USPRG7",
7212 &spr_read_ureg, SPR_NOACCESS,
7213 &spr_read_ureg, SPR_NOACCESS,
7214 0x00000000);
7215 /* Memory management */
7216 gen_low_BATs(env);
7217 gen_high_BATs(env);
7218 gen_74xx_soft_tlb(env, 128, 2);
7219 init_excp_7450(env);
7220 env->dcache_line_size = 32;
7221 env->icache_line_size = 32;
7222 /* Allocate hardware IRQ controller */
7223 ppc6xx_irq_init(ppc_env_get_cpu(env));
7224 }
7225
7226 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
7227 {
7228 DeviceClass *dc = DEVICE_CLASS(oc);
7229 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7230
7231 dc->desc = "PowerPC 7457 (aka G4)";
7232 pcc->init_proc = init_proc_7457;
7233 pcc->check_pow = check_pow_hid0_74xx;
7234 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7235 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7236 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7237 PPC_FLOAT_STFIWX |
7238 PPC_CACHE | PPC_CACHE_ICBI |
7239 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7240 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7241 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7242 PPC_MEM_TLBIA | PPC_74xx_TLB |
7243 PPC_SEGMENT | PPC_EXTERN |
7244 PPC_ALTIVEC;
7245 pcc->msr_mask = (1ull << MSR_VR) |
7246 (1ull << MSR_POW) |
7247 (1ull << MSR_ILE) |
7248 (1ull << MSR_EE) |
7249 (1ull << MSR_PR) |
7250 (1ull << MSR_FP) |
7251 (1ull << MSR_ME) |
7252 (1ull << MSR_FE0) |
7253 (1ull << MSR_SE) |
7254 (1ull << MSR_DE) |
7255 (1ull << MSR_FE1) |
7256 (1ull << MSR_EP) |
7257 (1ull << MSR_IR) |
7258 (1ull << MSR_DR) |
7259 (1ull << MSR_PMM) |
7260 (1ull << MSR_RI) |
7261 (1ull << MSR_LE);
7262 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7263 pcc->excp_model = POWERPC_EXCP_74xx;
7264 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7265 pcc->bfd_mach = bfd_mach_ppc_7400;
7266 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7267 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7268 POWERPC_FLAG_BUS_CLK;
7269 }
7270
7271 static void init_proc_e600 (CPUPPCState *env)
7272 {
7273 gen_spr_ne_601(env);
7274 gen_spr_7xx(env);
7275 /* Time base */
7276 gen_tbl(env);
7277 /* 74xx specific SPR */
7278 gen_spr_74xx(env);
7279 /* XXX : not implemented */
7280 spr_register(env, SPR_UBAMR, "UBAMR",
7281 &spr_read_ureg, SPR_NOACCESS,
7282 &spr_read_ureg, SPR_NOACCESS,
7283 0x00000000);
7284 /* XXX : not implemented */
7285 spr_register(env, SPR_LDSTCR, "LDSTCR",
7286 SPR_NOACCESS, SPR_NOACCESS,
7287 &spr_read_generic, &spr_write_generic,
7288 0x00000000);
7289 /* XXX : not implemented */
7290 spr_register(env, SPR_ICTRL, "ICTRL",
7291 SPR_NOACCESS, SPR_NOACCESS,
7292 &spr_read_generic, &spr_write_generic,
7293 0x00000000);
7294 /* XXX : not implemented */
7295 spr_register(env, SPR_MSSSR0, "MSSSR0",
7296 SPR_NOACCESS, SPR_NOACCESS,
7297 &spr_read_generic, &spr_write_generic,
7298 0x00000000);
7299 /* XXX : not implemented */
7300 spr_register(env, SPR_7XX_PMC5, "PMC5",
7301 SPR_NOACCESS, SPR_NOACCESS,
7302 &spr_read_generic, &spr_write_generic,
7303 0x00000000);
7304 /* XXX : not implemented */
7305 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7306 &spr_read_ureg, SPR_NOACCESS,
7307 &spr_read_ureg, SPR_NOACCESS,
7308 0x00000000);
7309 /* XXX : not implemented */
7310 spr_register(env, SPR_7XX_PMC6, "PMC6",
7311 SPR_NOACCESS, SPR_NOACCESS,
7312 &spr_read_generic, &spr_write_generic,
7313 0x00000000);
7314 /* XXX : not implemented */
7315 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7316 &spr_read_ureg, SPR_NOACCESS,
7317 &spr_read_ureg, SPR_NOACCESS,
7318 0x00000000);
7319 /* SPRGs */
7320 spr_register(env, SPR_SPRG4, "SPRG4",
7321 SPR_NOACCESS, SPR_NOACCESS,
7322 &spr_read_generic, &spr_write_generic,
7323 0x00000000);
7324 spr_register(env, SPR_USPRG4, "USPRG4",
7325 &spr_read_ureg, SPR_NOACCESS,
7326 &spr_read_ureg, SPR_NOACCESS,
7327 0x00000000);
7328 spr_register(env, SPR_SPRG5, "SPRG5",
7329 SPR_NOACCESS, SPR_NOACCESS,
7330 &spr_read_generic, &spr_write_generic,
7331 0x00000000);
7332 spr_register(env, SPR_USPRG5, "USPRG5",
7333 &spr_read_ureg, SPR_NOACCESS,
7334 &spr_read_ureg, SPR_NOACCESS,
7335 0x00000000);
7336 spr_register(env, SPR_SPRG6, "SPRG6",
7337 SPR_NOACCESS, SPR_NOACCESS,
7338 &spr_read_generic, &spr_write_generic,
7339 0x00000000);
7340 spr_register(env, SPR_USPRG6, "USPRG6",
7341 &spr_read_ureg, SPR_NOACCESS,
7342 &spr_read_ureg, SPR_NOACCESS,
7343 0x00000000);
7344 spr_register(env, SPR_SPRG7, "SPRG7",
7345 SPR_NOACCESS, SPR_NOACCESS,
7346 &spr_read_generic, &spr_write_generic,
7347 0x00000000);
7348 spr_register(env, SPR_USPRG7, "USPRG7",
7349 &spr_read_ureg, SPR_NOACCESS,
7350 &spr_read_ureg, SPR_NOACCESS,
7351 0x00000000);
7352 /* Memory management */
7353 gen_low_BATs(env);
7354 gen_high_BATs(env);
7355 gen_74xx_soft_tlb(env, 128, 2);
7356 init_excp_7450(env);
7357 env->dcache_line_size = 32;
7358 env->icache_line_size = 32;
7359 /* Allocate hardware IRQ controller */
7360 ppc6xx_irq_init(ppc_env_get_cpu(env));
7361 }
7362
7363 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
7364 {
7365 DeviceClass *dc = DEVICE_CLASS(oc);
7366 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7367
7368 dc->desc = "PowerPC e600";
7369 pcc->init_proc = init_proc_e600;
7370 pcc->check_pow = check_pow_hid0_74xx;
7371 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7372 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7373 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7374 PPC_FLOAT_STFIWX |
7375 PPC_CACHE | PPC_CACHE_ICBI |
7376 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7377 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7378 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7379 PPC_MEM_TLBIA | PPC_74xx_TLB |
7380 PPC_SEGMENT | PPC_EXTERN |
7381 PPC_ALTIVEC;
7382 pcc->insns_flags2 = PPC_NONE;
7383 pcc->msr_mask = (1ull << MSR_VR) |
7384 (1ull << MSR_POW) |
7385 (1ull << MSR_ILE) |
7386 (1ull << MSR_EE) |
7387 (1ull << MSR_PR) |
7388 (1ull << MSR_FP) |
7389 (1ull << MSR_ME) |
7390 (1ull << MSR_FE0) |
7391 (1ull << MSR_SE) |
7392 (1ull << MSR_DE) |
7393 (1ull << MSR_FE1) |
7394 (1ull << MSR_EP) |
7395 (1ull << MSR_IR) |
7396 (1ull << MSR_DR) |
7397 (1ull << MSR_PMM) |
7398 (1ull << MSR_RI) |
7399 (1ull << MSR_LE);
7400 pcc->mmu_model = POWERPC_MMU_32B;
7401 #if defined(CONFIG_SOFTMMU)
7402 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
7403 #endif
7404 pcc->excp_model = POWERPC_EXCP_74xx;
7405 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7406 pcc->bfd_mach = bfd_mach_ppc_7400;
7407 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7408 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7409 POWERPC_FLAG_BUS_CLK;
7410 }
7411
7412 #if defined (TARGET_PPC64)
7413 #if defined(CONFIG_USER_ONLY)
7414 #define POWERPC970_HID5_INIT 0x00000080
7415 #else
7416 #define POWERPC970_HID5_INIT 0x00000000
7417 #endif
7418
7419 enum BOOK3S_CPU_TYPE {
7420 BOOK3S_CPU_970,
7421 BOOK3S_CPU_POWER5PLUS,
7422 BOOK3S_CPU_POWER6,
7423 BOOK3S_CPU_POWER7,
7424 BOOK3S_CPU_POWER8
7425 };
7426
7427 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
7428 int bit, int sprn, int cause)
7429 {
7430 TCGv_i32 t1 = tcg_const_i32(bit);
7431 TCGv_i32 t2 = tcg_const_i32(sprn);
7432 TCGv_i32 t3 = tcg_const_i32(cause);
7433
7434 gen_update_current_nip(ctx);
7435 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
7436
7437 tcg_temp_free_i32(t3);
7438 tcg_temp_free_i32(t2);
7439 tcg_temp_free_i32(t1);
7440 }
7441
7442 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
7443 int bit, int sprn, int cause)
7444 {
7445 TCGv_i32 t1 = tcg_const_i32(bit);
7446 TCGv_i32 t2 = tcg_const_i32(sprn);
7447 TCGv_i32 t3 = tcg_const_i32(cause);
7448
7449 gen_update_current_nip(ctx);
7450 gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
7451
7452 tcg_temp_free_i32(t3);
7453 tcg_temp_free_i32(t2);
7454 tcg_temp_free_i32(t1);
7455 }
7456
7457 static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
7458 {
7459 TCGv spr_up = tcg_temp_new();
7460 TCGv spr = tcg_temp_new();
7461
7462 gen_load_spr(spr, sprn - 1);
7463 tcg_gen_shri_tl(spr_up, spr, 32);
7464 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
7465
7466 tcg_temp_free(spr);
7467 tcg_temp_free(spr_up);
7468 }
7469
7470 static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
7471 {
7472 TCGv spr = tcg_temp_new();
7473
7474 gen_load_spr(spr, sprn - 1);
7475 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
7476 gen_store_spr(sprn - 1, spr);
7477
7478 tcg_temp_free(spr);
7479 }
7480
7481 static int check_pow_970 (CPUPPCState *env)
7482 {
7483 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
7484 return 1;
7485 }
7486
7487 return 0;
7488 }
7489
7490 static void gen_spr_970_hid(CPUPPCState *env)
7491 {
7492 /* Hardware implementation registers */
7493 /* XXX : not implemented */
7494 spr_register(env, SPR_HID0, "HID0",
7495 SPR_NOACCESS, SPR_NOACCESS,
7496 &spr_read_generic, &spr_write_clear,
7497 0x60000000);
7498 spr_register(env, SPR_HID1, "HID1",
7499 SPR_NOACCESS, SPR_NOACCESS,
7500 &spr_read_generic, &spr_write_generic,
7501 0x00000000);
7502 spr_register(env, SPR_970_HID5, "HID5",
7503 SPR_NOACCESS, SPR_NOACCESS,
7504 &spr_read_generic, &spr_write_generic,
7505 POWERPC970_HID5_INIT);
7506 }
7507
7508 static void gen_spr_970_hior(CPUPPCState *env)
7509 {
7510 spr_register(env, SPR_HIOR, "SPR_HIOR",
7511 SPR_NOACCESS, SPR_NOACCESS,
7512 &spr_read_hior, &spr_write_hior,
7513 0x00000000);
7514 }
7515
7516 static void gen_spr_970_lpar(CPUPPCState *env)
7517 {
7518 /* Logical partitionning */
7519 /* PPC970: HID4 is effectively the LPCR */
7520 spr_register(env, SPR_970_HID4, "HID4",
7521 SPR_NOACCESS, SPR_NOACCESS,
7522 &spr_read_generic, &spr_write_generic,
7523 0x00000000);
7524 }
7525
7526 static void gen_spr_book3s_common(CPUPPCState *env)
7527 {
7528 spr_register(env, SPR_CTRL, "SPR_CTRL",
7529 SPR_NOACCESS, SPR_NOACCESS,
7530 SPR_NOACCESS, &spr_write_generic,
7531 0x00000000);
7532 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
7533 &spr_read_ureg, SPR_NOACCESS,
7534 &spr_read_ureg, SPR_NOACCESS,
7535 0x00000000);
7536 }
7537
7538 static void gen_spr_book3s_altivec(CPUPPCState *env)
7539 {
7540 if (!(env->insns_flags & PPC_ALTIVEC)) {
7541 return;
7542 }
7543
7544 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
7545 &spr_read_generic, &spr_write_generic,
7546 &spr_read_generic, &spr_write_generic,
7547 KVM_REG_PPC_VRSAVE, 0x00000000);
7548
7549 /* Can't find information on what this should be on reset. This
7550 * value is the one used by 74xx processors. */
7551 vscr_init(env, 0x00010000);
7552 }
7553
7554 static void gen_spr_book3s_dbg(CPUPPCState *env)
7555 {
7556 /*
7557 * TODO: different specs define different scopes for these,
7558 * will have to address this:
7559 * 970: super/write and super/read
7560 * powerisa 2.03..2.04: hypv/write and super/read.
7561 * powerisa 2.05 and newer: hypv/write and hypv/read.
7562 */
7563 spr_register_kvm(env, SPR_DABR, "DABR",
7564 SPR_NOACCESS, SPR_NOACCESS,
7565 &spr_read_generic, &spr_write_generic,
7566 KVM_REG_PPC_DABR, 0x00000000);
7567 spr_register_kvm(env, SPR_DABRX, "DABRX",
7568 SPR_NOACCESS, SPR_NOACCESS,
7569 &spr_read_generic, &spr_write_generic,
7570 KVM_REG_PPC_DABRX, 0x00000000);
7571 }
7572
7573 static void gen_spr_book3s_207_dbg(CPUPPCState *env)
7574 {
7575 spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
7576 SPR_NOACCESS, SPR_NOACCESS,
7577 SPR_NOACCESS, SPR_NOACCESS,
7578 &spr_read_generic, &spr_write_generic,
7579 KVM_REG_PPC_DAWR, 0x00000000);
7580 spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX",
7581 SPR_NOACCESS, SPR_NOACCESS,
7582 SPR_NOACCESS, SPR_NOACCESS,
7583 &spr_read_generic, &spr_write_generic,
7584 KVM_REG_PPC_DAWRX, 0x00000000);
7585 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
7586 SPR_NOACCESS, SPR_NOACCESS,
7587 SPR_NOACCESS, SPR_NOACCESS,
7588 &spr_read_generic, &spr_write_generic,
7589 KVM_REG_PPC_CIABR, 0x00000000);
7590 }
7591
7592 static void gen_spr_970_dbg(CPUPPCState *env)
7593 {
7594 /* Breakpoints */
7595 spr_register(env, SPR_IABR, "IABR",
7596 SPR_NOACCESS, SPR_NOACCESS,
7597 &spr_read_generic, &spr_write_generic,
7598 0x00000000);
7599 }
7600
7601 static void gen_spr_book3s_pmu_sup(CPUPPCState *env)
7602 {
7603 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
7604 SPR_NOACCESS, SPR_NOACCESS,
7605 &spr_read_generic, &spr_write_generic,
7606 KVM_REG_PPC_MMCR0, 0x00000000);
7607 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
7608 SPR_NOACCESS, SPR_NOACCESS,
7609 &spr_read_generic, &spr_write_generic,
7610 KVM_REG_PPC_MMCR1, 0x00000000);
7611 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
7612 SPR_NOACCESS, SPR_NOACCESS,
7613 &spr_read_generic, &spr_write_generic,
7614 KVM_REG_PPC_MMCRA, 0x00000000);
7615 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
7616 SPR_NOACCESS, SPR_NOACCESS,
7617 &spr_read_generic, &spr_write_generic,
7618 KVM_REG_PPC_PMC1, 0x00000000);
7619 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
7620 SPR_NOACCESS, SPR_NOACCESS,
7621 &spr_read_generic, &spr_write_generic,
7622 KVM_REG_PPC_PMC2, 0x00000000);
7623 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
7624 SPR_NOACCESS, SPR_NOACCESS,
7625 &spr_read_generic, &spr_write_generic,
7626 KVM_REG_PPC_PMC3, 0x00000000);
7627 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
7628 SPR_NOACCESS, SPR_NOACCESS,
7629 &spr_read_generic, &spr_write_generic,
7630 KVM_REG_PPC_PMC4, 0x00000000);
7631 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
7632 SPR_NOACCESS, SPR_NOACCESS,
7633 &spr_read_generic, &spr_write_generic,
7634 KVM_REG_PPC_PMC5, 0x00000000);
7635 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
7636 SPR_NOACCESS, SPR_NOACCESS,
7637 &spr_read_generic, &spr_write_generic,
7638 KVM_REG_PPC_PMC6, 0x00000000);
7639 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
7640 SPR_NOACCESS, SPR_NOACCESS,
7641 &spr_read_generic, &spr_write_generic,
7642 KVM_REG_PPC_SIAR, 0x00000000);
7643 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
7644 SPR_NOACCESS, SPR_NOACCESS,
7645 &spr_read_generic, &spr_write_generic,
7646 KVM_REG_PPC_SDAR, 0x00000000);
7647 }
7648
7649 static void gen_spr_book3s_pmu_user(CPUPPCState *env)
7650 {
7651 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
7652 &spr_read_ureg, SPR_NOACCESS,
7653 &spr_read_ureg, &spr_write_ureg,
7654 0x00000000);
7655 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
7656 &spr_read_ureg, SPR_NOACCESS,
7657 &spr_read_ureg, &spr_write_ureg,
7658 0x00000000);
7659 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
7660 &spr_read_ureg, SPR_NOACCESS,
7661 &spr_read_ureg, &spr_write_ureg,
7662 0x00000000);
7663 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
7664 &spr_read_ureg, SPR_NOACCESS,
7665 &spr_read_ureg, &spr_write_ureg,
7666 0x00000000);
7667 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
7668 &spr_read_ureg, SPR_NOACCESS,
7669 &spr_read_ureg, &spr_write_ureg,
7670 0x00000000);
7671 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
7672 &spr_read_ureg, SPR_NOACCESS,
7673 &spr_read_ureg, &spr_write_ureg,
7674 0x00000000);
7675 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
7676 &spr_read_ureg, SPR_NOACCESS,
7677 &spr_read_ureg, &spr_write_ureg,
7678 0x00000000);
7679 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
7680 &spr_read_ureg, SPR_NOACCESS,
7681 &spr_read_ureg, &spr_write_ureg,
7682 0x00000000);
7683 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
7684 &spr_read_ureg, SPR_NOACCESS,
7685 &spr_read_ureg, &spr_write_ureg,
7686 0x00000000);
7687 spr_register(env, SPR_POWER_USIAR, "USIAR",
7688 &spr_read_ureg, SPR_NOACCESS,
7689 &spr_read_ureg, &spr_write_ureg,
7690 0x00000000);
7691 spr_register(env, SPR_POWER_USDAR, "USDAR",
7692 &spr_read_ureg, SPR_NOACCESS,
7693 &spr_read_ureg, &spr_write_ureg,
7694 0x00000000);
7695 }
7696
7697 static void gen_spr_970_pmu_sup(CPUPPCState *env)
7698 {
7699 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
7700 SPR_NOACCESS, SPR_NOACCESS,
7701 &spr_read_generic, &spr_write_generic,
7702 KVM_REG_PPC_PMC7, 0x00000000);
7703 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
7704 SPR_NOACCESS, SPR_NOACCESS,
7705 &spr_read_generic, &spr_write_generic,
7706 KVM_REG_PPC_PMC8, 0x00000000);
7707 }
7708
7709 static void gen_spr_970_pmu_user(CPUPPCState *env)
7710 {
7711 spr_register(env, SPR_970_UPMC7, "UPMC7",
7712 &spr_read_ureg, SPR_NOACCESS,
7713 &spr_read_ureg, &spr_write_ureg,
7714 0x00000000);
7715 spr_register(env, SPR_970_UPMC8, "UPMC8",
7716 &spr_read_ureg, SPR_NOACCESS,
7717 &spr_read_ureg, &spr_write_ureg,
7718 0x00000000);
7719 }
7720
7721 static void gen_spr_power8_pmu_sup(CPUPPCState *env)
7722 {
7723 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
7724 SPR_NOACCESS, SPR_NOACCESS,
7725 &spr_read_generic, &spr_write_generic,
7726 KVM_REG_PPC_MMCR2, 0x00000000);
7727 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
7728 SPR_NOACCESS, SPR_NOACCESS,
7729 &spr_read_generic, &spr_write_generic,
7730 KVM_REG_PPC_MMCRS, 0x00000000);
7731 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
7732 SPR_NOACCESS, SPR_NOACCESS,
7733 &spr_read_generic, &spr_write_generic,
7734 KVM_REG_PPC_SIER, 0x00000000);
7735 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
7736 SPR_NOACCESS, SPR_NOACCESS,
7737 &spr_read_generic, &spr_write_generic,
7738 KVM_REG_PPC_SPMC1, 0x00000000);
7739 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
7740 SPR_NOACCESS, SPR_NOACCESS,
7741 &spr_read_generic, &spr_write_generic,
7742 KVM_REG_PPC_SPMC2, 0x00000000);
7743 spr_register_kvm(env, SPR_TACR, "TACR",
7744 SPR_NOACCESS, SPR_NOACCESS,
7745 &spr_read_generic, &spr_write_generic,
7746 KVM_REG_PPC_TACR, 0x00000000);
7747 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
7748 SPR_NOACCESS, SPR_NOACCESS,
7749 &spr_read_generic, &spr_write_generic,
7750 KVM_REG_PPC_TCSCR, 0x00000000);
7751 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
7752 SPR_NOACCESS, SPR_NOACCESS,
7753 &spr_read_generic, &spr_write_generic,
7754 KVM_REG_PPC_CSIGR, 0x00000000);
7755 }
7756
7757 static void gen_spr_power8_pmu_user(CPUPPCState *env)
7758 {
7759 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
7760 &spr_read_ureg, SPR_NOACCESS,
7761 &spr_read_ureg, &spr_write_ureg,
7762 0x00000000);
7763 spr_register(env, SPR_POWER_USIER, "USIER",
7764 &spr_read_generic, SPR_NOACCESS,
7765 &spr_read_generic, &spr_write_generic,
7766 0x00000000);
7767 }
7768
7769 static void gen_spr_power5p_ear(CPUPPCState *env)
7770 {
7771 /* External access control */
7772 spr_register(env, SPR_EAR, "EAR",
7773 SPR_NOACCESS, SPR_NOACCESS,
7774 &spr_read_generic, &spr_write_generic,
7775 0x00000000);
7776 }
7777
7778 static void gen_spr_power5p_lpar(CPUPPCState *env)
7779 {
7780 /* Logical partitionning */
7781 spr_register_kvm(env, SPR_LPCR, "LPCR",
7782 SPR_NOACCESS, SPR_NOACCESS,
7783 &spr_read_generic, &spr_write_generic,
7784 KVM_REG_PPC_LPCR, 0x00000000);
7785 }
7786
7787 static void gen_spr_book3s_ids(CPUPPCState *env)
7788 {
7789 /* Processor identification */
7790 spr_register(env, SPR_PIR, "PIR",
7791 SPR_NOACCESS, SPR_NOACCESS,
7792 &spr_read_generic, &spr_write_pir,
7793 0x00000000);
7794 }
7795
7796 static void gen_spr_power8_ids(CPUPPCState *env)
7797 {
7798 /* Thread identification */
7799 spr_register(env, SPR_TIR, "TIR",
7800 SPR_NOACCESS, SPR_NOACCESS,
7801 &spr_read_generic, SPR_NOACCESS,
7802 0x00000000);
7803 }
7804
7805 static void gen_spr_book3s_purr(CPUPPCState *env)
7806 {
7807 #if !defined(CONFIG_USER_ONLY)
7808 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
7809 spr_register_kvm(env, SPR_PURR, "PURR",
7810 &spr_read_purr, SPR_NOACCESS,
7811 &spr_read_purr, SPR_NOACCESS,
7812 KVM_REG_PPC_PURR, 0x00000000);
7813 spr_register_kvm(env, SPR_SPURR, "SPURR",
7814 &spr_read_purr, SPR_NOACCESS,
7815 &spr_read_purr, SPR_NOACCESS,
7816 KVM_REG_PPC_SPURR, 0x00000000);
7817 #endif
7818 }
7819
7820 static void gen_spr_power6_dbg(CPUPPCState *env)
7821 {
7822 #if !defined(CONFIG_USER_ONLY)
7823 spr_register(env, SPR_CFAR, "SPR_CFAR",
7824 SPR_NOACCESS, SPR_NOACCESS,
7825 &spr_read_cfar, &spr_write_cfar,
7826 0x00000000);
7827 #endif
7828 }
7829
7830 static void gen_spr_power5p_common(CPUPPCState *env)
7831 {
7832 spr_register_kvm(env, SPR_PPR, "PPR",
7833 &spr_read_generic, &spr_write_generic,
7834 &spr_read_generic, &spr_write_generic,
7835 KVM_REG_PPC_PPR, 0x00000000);
7836 }
7837
7838 static void gen_spr_power6_common(CPUPPCState *env)
7839 {
7840 #if !defined(CONFIG_USER_ONLY)
7841 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
7842 SPR_NOACCESS, SPR_NOACCESS,
7843 &spr_read_generic, &spr_write_generic,
7844 KVM_REG_PPC_DSCR, 0x00000000);
7845 #endif
7846 /*
7847 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
7848 * POWERPC_EXCP_INVAL_SPR.
7849 */
7850 spr_register(env, SPR_PCR, "PCR",
7851 SPR_NOACCESS, SPR_NOACCESS,
7852 SPR_NOACCESS, SPR_NOACCESS,
7853 0x00000000);
7854 }
7855
7856 static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
7857 {
7858 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
7859 spr_read_generic(ctx, gprn, sprn);
7860 }
7861
7862 static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
7863 {
7864 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
7865 spr_write_generic(ctx, sprn, gprn);
7866 }
7867
7868 static void gen_spr_power8_tce_address_control(CPUPPCState *env)
7869 {
7870 spr_register_kvm(env, SPR_TAR, "TAR",
7871 &spr_read_tar, &spr_write_tar,
7872 &spr_read_generic, &spr_write_generic,
7873 KVM_REG_PPC_TAR, 0x00000000);
7874 }
7875
7876 static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
7877 {
7878 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
7879 spr_read_generic(ctx, gprn, sprn);
7880 }
7881
7882 static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
7883 {
7884 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
7885 spr_write_generic(ctx, sprn, gprn);
7886 }
7887
7888 static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
7889 {
7890 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
7891 spr_read_prev_upper32(ctx, gprn, sprn);
7892 }
7893
7894 static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
7895 {
7896 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
7897 spr_write_prev_upper32(ctx, sprn, gprn);
7898 }
7899
7900 static void gen_spr_power8_tm(CPUPPCState *env)
7901 {
7902 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
7903 &spr_read_tm, &spr_write_tm,
7904 &spr_read_tm, &spr_write_tm,
7905 KVM_REG_PPC_TFHAR, 0x00000000);
7906 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
7907 &spr_read_tm, &spr_write_tm,
7908 &spr_read_tm, &spr_write_tm,
7909 KVM_REG_PPC_TFIAR, 0x00000000);
7910 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
7911 &spr_read_tm, &spr_write_tm,
7912 &spr_read_tm, &spr_write_tm,
7913 KVM_REG_PPC_TEXASR, 0x00000000);
7914 spr_register(env, SPR_TEXASRU, "TEXASRU",
7915 &spr_read_tm_upper32, &spr_write_tm_upper32,
7916 &spr_read_tm_upper32, &spr_write_tm_upper32,
7917 0x00000000);
7918 }
7919
7920 static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
7921 {
7922 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
7923 spr_read_generic(ctx, gprn, sprn);
7924 }
7925
7926 static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
7927 {
7928 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
7929 spr_write_generic(ctx, sprn, gprn);
7930 }
7931
7932 static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
7933 {
7934 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
7935 spr_read_prev_upper32(ctx, gprn, sprn);
7936 }
7937
7938 static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
7939 {
7940 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
7941 spr_write_prev_upper32(ctx, sprn, gprn);
7942 }
7943
7944 static void gen_spr_power8_ebb(CPUPPCState *env)
7945 {
7946 spr_register(env, SPR_BESCRS, "BESCRS",
7947 &spr_read_ebb, &spr_write_ebb,
7948 &spr_read_generic, &spr_write_generic,
7949 0x00000000);
7950 spr_register(env, SPR_BESCRSU, "BESCRSU",
7951 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
7952 &spr_read_prev_upper32, &spr_write_prev_upper32,
7953 0x00000000);
7954 spr_register(env, SPR_BESCRR, "BESCRR",
7955 &spr_read_ebb, &spr_write_ebb,
7956 &spr_read_generic, &spr_write_generic,
7957 0x00000000);
7958 spr_register(env, SPR_BESCRRU, "BESCRRU",
7959 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
7960 &spr_read_prev_upper32, &spr_write_prev_upper32,
7961 0x00000000);
7962 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
7963 &spr_read_ebb, &spr_write_ebb,
7964 &spr_read_generic, &spr_write_generic,
7965 KVM_REG_PPC_EBBHR, 0x00000000);
7966 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
7967 &spr_read_ebb, &spr_write_ebb,
7968 &spr_read_generic, &spr_write_generic,
7969 KVM_REG_PPC_EBBRR, 0x00000000);
7970 spr_register_kvm(env, SPR_BESCR, "BESCR",
7971 &spr_read_ebb, &spr_write_ebb,
7972 &spr_read_generic, &spr_write_generic,
7973 KVM_REG_PPC_BESCR, 0x00000000);
7974 }
7975
7976 /* Virtual Time Base */
7977 static void gen_spr_vtb(CPUPPCState *env)
7978 {
7979 spr_register(env, SPR_VTB, "VTB",
7980 SPR_NOACCESS, SPR_NOACCESS,
7981 &spr_read_tbl, SPR_NOACCESS,
7982 0x00000000);
7983 }
7984
7985 static void gen_spr_power8_fscr(CPUPPCState *env)
7986 {
7987 #if defined(CONFIG_USER_ONLY)
7988 target_ulong initval = 1ULL << FSCR_TAR;
7989 #else
7990 target_ulong initval = 0;
7991 #endif
7992 spr_register_kvm(env, SPR_FSCR, "FSCR",
7993 SPR_NOACCESS, SPR_NOACCESS,
7994 &spr_read_generic, &spr_write_generic,
7995 KVM_REG_PPC_FSCR, initval);
7996 }
7997
7998 static void gen_spr_power8_pspb(CPUPPCState *env)
7999 {
8000 spr_register_kvm(env, SPR_PSPB, "PSPB",
8001 SPR_NOACCESS, SPR_NOACCESS,
8002 &spr_read_generic, &spr_write_generic32,
8003 KVM_REG_PPC_PSPB, 0);
8004 }
8005
8006 static void gen_spr_power8_ic(CPUPPCState *env)
8007 {
8008 #if !defined(CONFIG_USER_ONLY)
8009 spr_register_hv(env, SPR_IC, "IC",
8010 SPR_NOACCESS, SPR_NOACCESS,
8011 &spr_read_generic, SPR_NOACCESS,
8012 &spr_read_generic, &spr_write_generic,
8013 0);
8014 #endif
8015 }
8016
8017 static void gen_spr_power8_book4(CPUPPCState *env)
8018 {
8019 /* Add a number of P8 book4 registers */
8020 #if !defined(CONFIG_USER_ONLY)
8021 spr_register_kvm(env, SPR_ACOP, "ACOP",
8022 SPR_NOACCESS, SPR_NOACCESS,
8023 &spr_read_generic, &spr_write_generic,
8024 KVM_REG_PPC_ACOP, 0);
8025 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
8026 SPR_NOACCESS, SPR_NOACCESS,
8027 &spr_read_generic, &spr_write_generic,
8028 KVM_REG_PPC_PID, 0);
8029 spr_register_kvm(env, SPR_WORT, "WORT",
8030 SPR_NOACCESS, SPR_NOACCESS,
8031 &spr_read_generic, &spr_write_generic,
8032 KVM_REG_PPC_WORT, 0);
8033 #endif
8034 }
8035
8036 static void gen_spr_power7_book4(CPUPPCState *env)
8037 {
8038 /* Add a number of P7 book4 registers */
8039 #if !defined(CONFIG_USER_ONLY)
8040 spr_register_kvm(env, SPR_ACOP, "ACOP",
8041 SPR_NOACCESS, SPR_NOACCESS,
8042 &spr_read_generic, &spr_write_generic,
8043 KVM_REG_PPC_ACOP, 0);
8044 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
8045 SPR_NOACCESS, SPR_NOACCESS,
8046 &spr_read_generic, &spr_write_generic,
8047 KVM_REG_PPC_PID, 0);
8048 #endif
8049 }
8050
8051 static void init_proc_book3s_64(CPUPPCState *env, int version)
8052 {
8053 gen_spr_ne_601(env);
8054 gen_tbl(env);
8055 gen_spr_book3s_altivec(env);
8056 gen_spr_book3s_pmu_sup(env);
8057 gen_spr_book3s_pmu_user(env);
8058 gen_spr_book3s_common(env);
8059
8060 switch (version) {
8061 case BOOK3S_CPU_970:
8062 case BOOK3S_CPU_POWER5PLUS:
8063 gen_spr_970_hid(env);
8064 gen_spr_970_hior(env);
8065 gen_low_BATs(env);
8066 gen_spr_970_pmu_sup(env);
8067 gen_spr_970_pmu_user(env);
8068 break;
8069 case BOOK3S_CPU_POWER7:
8070 case BOOK3S_CPU_POWER8:
8071 gen_spr_book3s_ids(env);
8072 gen_spr_amr(env, version >= BOOK3S_CPU_POWER8);
8073 gen_spr_book3s_purr(env);
8074 env->ci_large_pages = true;
8075 break;
8076 default:
8077 g_assert_not_reached();
8078 }
8079 if (version >= BOOK3S_CPU_POWER5PLUS) {
8080 gen_spr_power5p_common(env);
8081 gen_spr_power5p_lpar(env);
8082 gen_spr_power5p_ear(env);
8083 } else {
8084 gen_spr_970_lpar(env);
8085 }
8086 if (version == BOOK3S_CPU_970) {
8087 gen_spr_970_dbg(env);
8088 }
8089 if (version >= BOOK3S_CPU_POWER6) {
8090 gen_spr_power6_common(env);
8091 gen_spr_power6_dbg(env);
8092 }
8093 if (version == BOOK3S_CPU_POWER7) {
8094 gen_spr_power7_book4(env);
8095 }
8096 if (version >= BOOK3S_CPU_POWER8) {
8097 gen_spr_power8_tce_address_control(env);
8098 gen_spr_power8_ids(env);
8099 gen_spr_power8_ebb(env);
8100 gen_spr_power8_fscr(env);
8101 gen_spr_power8_pmu_sup(env);
8102 gen_spr_power8_pmu_user(env);
8103 gen_spr_power8_tm(env);
8104 gen_spr_power8_pspb(env);
8105 gen_spr_vtb(env);
8106 gen_spr_power8_ic(env);
8107 gen_spr_power8_book4(env);
8108 }
8109 if (version < BOOK3S_CPU_POWER8) {
8110 gen_spr_book3s_dbg(env);
8111 } else {
8112 gen_spr_book3s_207_dbg(env);
8113 }
8114 #if !defined(CONFIG_USER_ONLY)
8115 switch (version) {
8116 case BOOK3S_CPU_970:
8117 case BOOK3S_CPU_POWER5PLUS:
8118 env->slb_nr = 64;
8119 break;
8120 case BOOK3S_CPU_POWER7:
8121 case BOOK3S_CPU_POWER8:
8122 default:
8123 env->slb_nr = 32;
8124 break;
8125 }
8126 #endif
8127 /* Allocate hardware IRQ controller */
8128 switch (version) {
8129 case BOOK3S_CPU_970:
8130 case BOOK3S_CPU_POWER5PLUS:
8131 init_excp_970(env);
8132 ppc970_irq_init(ppc_env_get_cpu(env));
8133 break;
8134 case BOOK3S_CPU_POWER7:
8135 case BOOK3S_CPU_POWER8:
8136 init_excp_POWER7(env);
8137 ppcPOWER7_irq_init(ppc_env_get_cpu(env));
8138 break;
8139 default:
8140 g_assert_not_reached();
8141 }
8142
8143 env->dcache_line_size = 128;
8144 env->icache_line_size = 128;
8145 }
8146
8147 static void init_proc_970(CPUPPCState *env)
8148 {
8149 init_proc_book3s_64(env, BOOK3S_CPU_970);
8150 }
8151
8152 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
8153 {
8154 DeviceClass *dc = DEVICE_CLASS(oc);
8155 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8156
8157 dc->desc = "PowerPC 970";
8158 pcc->init_proc = init_proc_970;
8159 pcc->check_pow = check_pow_970;
8160 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
8161 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8162 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8163 PPC_FLOAT_STFIWX |
8164 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8165 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8166 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8167 PPC_64B | PPC_ALTIVEC |
8168 PPC_SEGMENT_64B | PPC_SLBI;
8169 pcc->insns_flags2 = PPC2_FP_CVT_S64;
8170 pcc->msr_mask = (1ull << MSR_SF) |
8171 (1ull << MSR_VR) |
8172 (1ull << MSR_POW) |
8173 (1ull << MSR_EE) |
8174 (1ull << MSR_PR) |
8175 (1ull << MSR_FP) |
8176 (1ull << MSR_ME) |
8177 (1ull << MSR_FE0) |
8178 (1ull << MSR_SE) |
8179 (1ull << MSR_DE) |
8180 (1ull << MSR_FE1) |
8181 (1ull << MSR_IR) |
8182 (1ull << MSR_DR) |
8183 (1ull << MSR_PMM) |
8184 (1ull << MSR_RI);
8185 pcc->mmu_model = POWERPC_MMU_64B;
8186 #if defined(CONFIG_SOFTMMU)
8187 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8188 #endif
8189 pcc->excp_model = POWERPC_EXCP_970;
8190 pcc->bus_model = PPC_FLAGS_INPUT_970;
8191 pcc->bfd_mach = bfd_mach_ppc64;
8192 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8193 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8194 POWERPC_FLAG_BUS_CLK;
8195 pcc->l1_dcache_size = 0x8000;
8196 pcc->l1_icache_size = 0x10000;
8197 }
8198
8199 static void init_proc_power5plus(CPUPPCState *env)
8200 {
8201 init_proc_book3s_64(env, BOOK3S_CPU_POWER5PLUS);
8202 }
8203
8204 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
8205 {
8206 DeviceClass *dc = DEVICE_CLASS(oc);
8207 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8208
8209 dc->fw_name = "PowerPC,POWER5";
8210 dc->desc = "POWER5+";
8211 pcc->init_proc = init_proc_power5plus;
8212 pcc->check_pow = check_pow_970;
8213 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
8214 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8215 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8216 PPC_FLOAT_STFIWX |
8217 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8218 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8219 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8220 PPC_64B |
8221 PPC_SEGMENT_64B | PPC_SLBI;
8222 pcc->insns_flags2 = PPC2_FP_CVT_S64;
8223 pcc->msr_mask = (1ull << MSR_SF) |
8224 (1ull << MSR_VR) |
8225 (1ull << MSR_POW) |
8226 (1ull << MSR_EE) |
8227 (1ull << MSR_PR) |
8228 (1ull << MSR_FP) |
8229 (1ull << MSR_ME) |
8230 (1ull << MSR_FE0) |
8231 (1ull << MSR_SE) |
8232 (1ull << MSR_DE) |
8233 (1ull << MSR_FE1) |
8234 (1ull << MSR_IR) |
8235 (1ull << MSR_DR) |
8236 (1ull << MSR_PMM) |
8237 (1ull << MSR_RI);
8238 pcc->mmu_model = POWERPC_MMU_2_03;
8239 #if defined(CONFIG_SOFTMMU)
8240 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8241 #endif
8242 pcc->excp_model = POWERPC_EXCP_970;
8243 pcc->bus_model = PPC_FLAGS_INPUT_970;
8244 pcc->bfd_mach = bfd_mach_ppc64;
8245 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8246 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8247 POWERPC_FLAG_BUS_CLK;
8248 pcc->l1_dcache_size = 0x8000;
8249 pcc->l1_icache_size = 0x10000;
8250 }
8251
8252 static void powerpc_get_compat(Object *obj, Visitor *v, const char *name,
8253 void *opaque, Error **errp)
8254 {
8255 char *value = (char *)"";
8256 Property *prop = opaque;
8257 uint32_t *max_compat = qdev_get_prop_ptr(DEVICE(obj), prop);
8258
8259 switch (*max_compat) {
8260 case CPU_POWERPC_LOGICAL_2_05:
8261 value = (char *)"power6";
8262 break;
8263 case CPU_POWERPC_LOGICAL_2_06:
8264 value = (char *)"power7";
8265 break;
8266 case CPU_POWERPC_LOGICAL_2_07:
8267 value = (char *)"power8";
8268 break;
8269 case 0:
8270 break;
8271 default:
8272 error_setg(errp, "Internal error: compat is set to %x",
8273 max_compat ? *max_compat : -1);
8274 break;
8275 }
8276
8277 visit_type_str(v, name, &value, errp);
8278 }
8279
8280 static void powerpc_set_compat(Object *obj, Visitor *v, const char *name,
8281 void *opaque, Error **errp)
8282 {
8283 Error *error = NULL;
8284 char *value = NULL;
8285 Property *prop = opaque;
8286 uint32_t *max_compat = qdev_get_prop_ptr(DEVICE(obj), prop);
8287
8288 visit_type_str(v, name, &value, &error);
8289 if (error) {
8290 error_propagate(errp, error);
8291 return;
8292 }
8293
8294 if (strcmp(value, "power6") == 0) {
8295 *max_compat = CPU_POWERPC_LOGICAL_2_05;
8296 } else if (strcmp(value, "power7") == 0) {
8297 *max_compat = CPU_POWERPC_LOGICAL_2_06;
8298 } else if (strcmp(value, "power8") == 0) {
8299 *max_compat = CPU_POWERPC_LOGICAL_2_07;
8300 } else {
8301 error_setg(errp, "Invalid compatibility mode \"%s\"", value);
8302 }
8303
8304 g_free(value);
8305 }
8306
8307 static PropertyInfo powerpc_compat_propinfo = {
8308 .name = "str",
8309 .description = "compatibility mode, power6/power7/power8",
8310 .get = powerpc_get_compat,
8311 .set = powerpc_set_compat,
8312 };
8313
8314 #define DEFINE_PROP_POWERPC_COMPAT(_n, _s, _f) \
8315 DEFINE_PROP(_n, _s, _f, powerpc_compat_propinfo, uint32_t)
8316
8317 static Property powerpc_servercpu_properties[] = {
8318 DEFINE_PROP_POWERPC_COMPAT("compat", PowerPCCPU, max_compat),
8319 DEFINE_PROP_END_OF_LIST(),
8320 };
8321
8322 #ifdef CONFIG_SOFTMMU
8323 static const struct ppc_segment_page_sizes POWER7_POWER8_sps = {
8324 .sps = {
8325 {
8326 .page_shift = 12, /* 4K */
8327 .slb_enc = 0,
8328 .enc = { { .page_shift = 12, .pte_enc = 0 },
8329 { .page_shift = 16, .pte_enc = 0x7 },
8330 { .page_shift = 24, .pte_enc = 0x38 }, },
8331 },
8332 {
8333 .page_shift = 16, /* 64K */
8334 .slb_enc = SLB_VSID_64K,
8335 .enc = { { .page_shift = 16, .pte_enc = 0x1 },
8336 { .page_shift = 24, .pte_enc = 0x8 }, },
8337 },
8338 {
8339 .page_shift = 24, /* 16M */
8340 .slb_enc = SLB_VSID_16M,
8341 .enc = { { .page_shift = 24, .pte_enc = 0 }, },
8342 },
8343 {
8344 .page_shift = 34, /* 16G */
8345 .slb_enc = SLB_VSID_16G,
8346 .enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
8347 },
8348 }
8349 };
8350 #endif /* CONFIG_SOFTMMU */
8351
8352 static void init_proc_POWER7 (CPUPPCState *env)
8353 {
8354 init_proc_book3s_64(env, BOOK3S_CPU_POWER7);
8355 }
8356
8357 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
8358 {
8359 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
8360 return true;
8361 }
8362 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
8363 return true;
8364 }
8365 return false;
8366 }
8367
8368 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
8369 {
8370 DeviceClass *dc = DEVICE_CLASS(oc);
8371 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8372
8373 dc->fw_name = "PowerPC,POWER7";
8374 dc->desc = "POWER7";
8375 dc->props = powerpc_servercpu_properties;
8376 pcc->pvr_match = ppc_pvr_match_power7;
8377 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
8378 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8379 pcc->init_proc = init_proc_POWER7;
8380 pcc->check_pow = check_pow_nocheck;
8381 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8382 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8383 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8384 PPC_FLOAT_FRSQRTES |
8385 PPC_FLOAT_STFIWX |
8386 PPC_FLOAT_EXT |
8387 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8388 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8389 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8390 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8391 PPC_SEGMENT_64B | PPC_SLBI |
8392 PPC_POPCNTB | PPC_POPCNTWD;
8393 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
8394 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8395 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8396 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64;
8397 pcc->msr_mask = (1ull << MSR_SF) |
8398 (1ull << MSR_VR) |
8399 (1ull << MSR_VSX) |
8400 (1ull << MSR_EE) |
8401 (1ull << MSR_PR) |
8402 (1ull << MSR_FP) |
8403 (1ull << MSR_ME) |
8404 (1ull << MSR_FE0) |
8405 (1ull << MSR_SE) |
8406 (1ull << MSR_DE) |
8407 (1ull << MSR_FE1) |
8408 (1ull << MSR_IR) |
8409 (1ull << MSR_DR) |
8410 (1ull << MSR_PMM) |
8411 (1ull << MSR_RI) |
8412 (1ull << MSR_LE);
8413 pcc->mmu_model = POWERPC_MMU_2_06;
8414 #if defined(CONFIG_SOFTMMU)
8415 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8416 pcc->sps = &POWER7_POWER8_sps;
8417 #endif
8418 pcc->excp_model = POWERPC_EXCP_POWER7;
8419 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8420 pcc->bfd_mach = bfd_mach_ppc64;
8421 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8422 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8423 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8424 POWERPC_FLAG_VSX;
8425 pcc->l1_dcache_size = 0x8000;
8426 pcc->l1_icache_size = 0x8000;
8427 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8428 }
8429
8430 static void init_proc_POWER8(CPUPPCState *env)
8431 {
8432 init_proc_book3s_64(env, BOOK3S_CPU_POWER8);
8433 }
8434
8435 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
8436 {
8437 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
8438 return true;
8439 }
8440 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
8441 return true;
8442 }
8443 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
8444 return true;
8445 }
8446 return false;
8447 }
8448
8449 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
8450 {
8451 DeviceClass *dc = DEVICE_CLASS(oc);
8452 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8453
8454 dc->fw_name = "PowerPC,POWER8";
8455 dc->desc = "POWER8";
8456 dc->props = powerpc_servercpu_properties;
8457 pcc->pvr_match = ppc_pvr_match_power8;
8458 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8459 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
8460 pcc->init_proc = init_proc_POWER8;
8461 pcc->check_pow = check_pow_nocheck;
8462 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8463 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8464 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8465 PPC_FLOAT_FRSQRTES |
8466 PPC_FLOAT_STFIWX |
8467 PPC_FLOAT_EXT |
8468 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8469 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8470 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8471 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8472 PPC_SEGMENT_64B | PPC_SLBI |
8473 PPC_POPCNTB | PPC_POPCNTWD;
8474 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8475 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8476 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8477 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8478 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8479 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8480 PPC2_TM;
8481 pcc->msr_mask = (1ull << MSR_SF) |
8482 (1ull << MSR_SHV) |
8483 (1ull << MSR_TM) |
8484 (1ull << MSR_VR) |
8485 (1ull << MSR_VSX) |
8486 (1ull << MSR_EE) |
8487 (1ull << MSR_PR) |
8488 (1ull << MSR_FP) |
8489 (1ull << MSR_ME) |
8490 (1ull << MSR_FE0) |
8491 (1ull << MSR_SE) |
8492 (1ull << MSR_DE) |
8493 (1ull << MSR_FE1) |
8494 (1ull << MSR_IR) |
8495 (1ull << MSR_DR) |
8496 (1ull << MSR_PMM) |
8497 (1ull << MSR_RI) |
8498 (1ull << MSR_LE);
8499 pcc->mmu_model = POWERPC_MMU_2_07;
8500 #if defined(CONFIG_SOFTMMU)
8501 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8502 pcc->sps = &POWER7_POWER8_sps;
8503 #endif
8504 pcc->excp_model = POWERPC_EXCP_POWER8;
8505 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8506 pcc->bfd_mach = bfd_mach_ppc64;
8507 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8508 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8509 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8510 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
8511 pcc->l1_dcache_size = 0x8000;
8512 pcc->l1_icache_size = 0x8000;
8513 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8514 }
8515
8516 #if !defined(CONFIG_USER_ONLY)
8517
8518 void cpu_ppc_set_papr(PowerPCCPU *cpu)
8519 {
8520 CPUPPCState *env = &cpu->env;
8521 ppc_spr_t *amor = &env->spr_cb[SPR_AMOR];
8522
8523 /* PAPR always has exception vectors in RAM not ROM. To ensure this,
8524 * MSR[IP] should never be set.
8525 *
8526 * We also disallow setting of MSR_HV
8527 */
8528 env->msr_mask &= ~((1ull << MSR_EP) | MSR_HVB);
8529
8530 /* Set a full AMOR so guest can use the AMR as it sees fit */
8531 env->spr[SPR_AMOR] = amor->default_value = 0xffffffffffffffffull;
8532
8533 /* Tell KVM that we're in PAPR mode */
8534 if (kvm_enabled()) {
8535 kvmppc_set_papr(cpu);
8536 }
8537 }
8538
8539 #endif /* !defined(CONFIG_USER_ONLY) */
8540
8541 #endif /* defined (TARGET_PPC64) */
8542
8543 /*****************************************************************************/
8544 /* Generic CPU instantiation routine */
8545 static void init_ppc_proc(PowerPCCPU *cpu)
8546 {
8547 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8548 CPUPPCState *env = &cpu->env;
8549 #if !defined(CONFIG_USER_ONLY)
8550 int i;
8551
8552 env->irq_inputs = NULL;
8553 /* Set all exception vectors to an invalid address */
8554 for (i = 0; i < POWERPC_EXCP_NB; i++)
8555 env->excp_vectors[i] = (target_ulong)(-1ULL);
8556 env->ivor_mask = 0x00000000;
8557 env->ivpr_mask = 0x00000000;
8558 /* Default MMU definitions */
8559 env->nb_BATs = 0;
8560 env->nb_tlb = 0;
8561 env->nb_ways = 0;
8562 env->tlb_type = TLB_NONE;
8563 #endif
8564 /* Register SPR common to all PowerPC implementations */
8565 gen_spr_generic(env);
8566 spr_register(env, SPR_PVR, "PVR",
8567 /* Linux permits userspace to read PVR */
8568 #if defined(CONFIG_LINUX_USER)
8569 &spr_read_generic,
8570 #else
8571 SPR_NOACCESS,
8572 #endif
8573 SPR_NOACCESS,
8574 &spr_read_generic, SPR_NOACCESS,
8575 pcc->pvr);
8576 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8577 if (pcc->svr != POWERPC_SVR_NONE) {
8578 if (pcc->svr & POWERPC_SVR_E500) {
8579 spr_register(env, SPR_E500_SVR, "SVR",
8580 SPR_NOACCESS, SPR_NOACCESS,
8581 &spr_read_generic, SPR_NOACCESS,
8582 pcc->svr & ~POWERPC_SVR_E500);
8583 } else {
8584 spr_register(env, SPR_SVR, "SVR",
8585 SPR_NOACCESS, SPR_NOACCESS,
8586 &spr_read_generic, SPR_NOACCESS,
8587 pcc->svr);
8588 }
8589 }
8590 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8591 (*pcc->init_proc)(env);
8592
8593 /* MSR bits & flags consistency checks */
8594 if (env->msr_mask & (1 << 25)) {
8595 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8596 case POWERPC_FLAG_SPE:
8597 case POWERPC_FLAG_VRE:
8598 break;
8599 default:
8600 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8601 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8602 exit(1);
8603 }
8604 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8605 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8606 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8607 exit(1);
8608 }
8609 if (env->msr_mask & (1 << 17)) {
8610 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8611 case POWERPC_FLAG_TGPR:
8612 case POWERPC_FLAG_CE:
8613 break;
8614 default:
8615 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8616 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8617 exit(1);
8618 }
8619 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8620 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8621 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8622 exit(1);
8623 }
8624 if (env->msr_mask & (1 << 10)) {
8625 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8626 POWERPC_FLAG_UBLE)) {
8627 case POWERPC_FLAG_SE:
8628 case POWERPC_FLAG_DWE:
8629 case POWERPC_FLAG_UBLE:
8630 break;
8631 default:
8632 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8633 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8634 "POWERPC_FLAG_UBLE\n");
8635 exit(1);
8636 }
8637 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8638 POWERPC_FLAG_UBLE)) {
8639 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8640 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8641 "POWERPC_FLAG_UBLE\n");
8642 exit(1);
8643 }
8644 if (env->msr_mask & (1 << 9)) {
8645 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8646 case POWERPC_FLAG_BE:
8647 case POWERPC_FLAG_DE:
8648 break;
8649 default:
8650 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8651 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8652 exit(1);
8653 }
8654 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8655 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8656 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8657 exit(1);
8658 }
8659 if (env->msr_mask & (1 << 2)) {
8660 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8661 case POWERPC_FLAG_PX:
8662 case POWERPC_FLAG_PMM:
8663 break;
8664 default:
8665 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8666 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
8667 exit(1);
8668 }
8669 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8670 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8671 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
8672 exit(1);
8673 }
8674 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
8675 fprintf(stderr, "PowerPC flags inconsistency\n"
8676 "Should define the time-base and decrementer clock source\n");
8677 exit(1);
8678 }
8679 /* Allocate TLBs buffer when needed */
8680 #if !defined(CONFIG_USER_ONLY)
8681 if (env->nb_tlb != 0) {
8682 int nb_tlb = env->nb_tlb;
8683 if (env->id_tlbs != 0)
8684 nb_tlb *= 2;
8685 switch (env->tlb_type) {
8686 case TLB_6XX:
8687 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
8688 break;
8689 case TLB_EMB:
8690 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
8691 break;
8692 case TLB_MAS:
8693 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
8694 break;
8695 }
8696 /* Pre-compute some useful values */
8697 env->tlb_per_way = env->nb_tlb / env->nb_ways;
8698 }
8699 if (env->irq_inputs == NULL) {
8700 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
8701 " Attempt QEMU to crash very soon !\n");
8702 }
8703 #endif
8704 if (env->check_pow == NULL) {
8705 fprintf(stderr, "WARNING: no power management check handler "
8706 "registered.\n"
8707 " Attempt QEMU to crash very soon !\n");
8708 }
8709 }
8710
8711 #if defined(PPC_DUMP_CPU)
8712 static void dump_ppc_sprs (CPUPPCState *env)
8713 {
8714 ppc_spr_t *spr;
8715 #if !defined(CONFIG_USER_ONLY)
8716 uint32_t sr, sw;
8717 #endif
8718 uint32_t ur, uw;
8719 int i, j, n;
8720
8721 printf("Special purpose registers:\n");
8722 for (i = 0; i < 32; i++) {
8723 for (j = 0; j < 32; j++) {
8724 n = (i << 5) | j;
8725 spr = &env->spr_cb[n];
8726 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
8727 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
8728 #if !defined(CONFIG_USER_ONLY)
8729 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
8730 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
8731 if (sw || sr || uw || ur) {
8732 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
8733 (i << 5) | j, (i << 5) | j, spr->name,
8734 sw ? 'w' : '-', sr ? 'r' : '-',
8735 uw ? 'w' : '-', ur ? 'r' : '-');
8736 }
8737 #else
8738 if (uw || ur) {
8739 printf("SPR: %4d (%03x) %-8s u%c%c\n",
8740 (i << 5) | j, (i << 5) | j, spr->name,
8741 uw ? 'w' : '-', ur ? 'r' : '-');
8742 }
8743 #endif
8744 }
8745 }
8746 fflush(stdout);
8747 fflush(stderr);
8748 }
8749 #endif
8750
8751 /*****************************************************************************/
8752
8753 /* Opcode types */
8754 enum {
8755 PPC_DIRECT = 0, /* Opcode routine */
8756 PPC_INDIRECT = 1, /* Indirect opcode table */
8757 };
8758
8759 #define PPC_OPCODE_MASK 0x3
8760
8761 static inline int is_indirect_opcode (void *handler)
8762 {
8763 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT;
8764 }
8765
8766 static inline opc_handler_t **ind_table(void *handler)
8767 {
8768 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK);
8769 }
8770
8771 /* Instruction table creation */
8772 /* Opcodes tables creation */
8773 static void fill_new_table (opc_handler_t **table, int len)
8774 {
8775 int i;
8776
8777 for (i = 0; i < len; i++)
8778 table[i] = &invalid_handler;
8779 }
8780
8781 static int create_new_table (opc_handler_t **table, unsigned char idx)
8782 {
8783 opc_handler_t **tmp;
8784
8785 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN);
8786 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN);
8787 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
8788
8789 return 0;
8790 }
8791
8792 static int insert_in_table (opc_handler_t **table, unsigned char idx,
8793 opc_handler_t *handler)
8794 {
8795 if (table[idx] != &invalid_handler)
8796 return -1;
8797 table[idx] = handler;
8798
8799 return 0;
8800 }
8801
8802 static int register_direct_insn (opc_handler_t **ppc_opcodes,
8803 unsigned char idx, opc_handler_t *handler)
8804 {
8805 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
8806 printf("*** ERROR: opcode %02x already assigned in main "
8807 "opcode table\n", idx);
8808 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8809 printf(" Registered handler '%s' - new handler '%s'\n",
8810 ppc_opcodes[idx]->oname, handler->oname);
8811 #endif
8812 return -1;
8813 }
8814
8815 return 0;
8816 }
8817
8818 static int register_ind_in_table (opc_handler_t **table,
8819 unsigned char idx1, unsigned char idx2,
8820 opc_handler_t *handler)
8821 {
8822 if (table[idx1] == &invalid_handler) {
8823 if (create_new_table(table, idx1) < 0) {
8824 printf("*** ERROR: unable to create indirect table "
8825 "idx=%02x\n", idx1);
8826 return -1;
8827 }
8828 } else {
8829 if (!is_indirect_opcode(table[idx1])) {
8830 printf("*** ERROR: idx %02x already assigned to a direct "
8831 "opcode\n", idx1);
8832 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8833 printf(" Registered handler '%s' - new handler '%s'\n",
8834 ind_table(table[idx1])[idx2]->oname, handler->oname);
8835 #endif
8836 return -1;
8837 }
8838 }
8839 if (handler != NULL &&
8840 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
8841 printf("*** ERROR: opcode %02x already assigned in "
8842 "opcode table %02x\n", idx2, idx1);
8843 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8844 printf(" Registered handler '%s' - new handler '%s'\n",
8845 ind_table(table[idx1])[idx2]->oname, handler->oname);
8846 #endif
8847 return -1;
8848 }
8849
8850 return 0;
8851 }
8852
8853 static int register_ind_insn (opc_handler_t **ppc_opcodes,
8854 unsigned char idx1, unsigned char idx2,
8855 opc_handler_t *handler)
8856 {
8857 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
8858 }
8859
8860 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
8861 unsigned char idx1, unsigned char idx2,
8862 unsigned char idx3, opc_handler_t *handler)
8863 {
8864 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
8865 printf("*** ERROR: unable to join indirect table idx "
8866 "[%02x-%02x]\n", idx1, idx2);
8867 return -1;
8868 }
8869 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
8870 handler) < 0) {
8871 printf("*** ERROR: unable to insert opcode "
8872 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
8873 return -1;
8874 }
8875
8876 return 0;
8877 }
8878
8879 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
8880 {
8881 if (insn->opc2 != 0xFF) {
8882 if (insn->opc3 != 0xFF) {
8883 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
8884 insn->opc3, &insn->handler) < 0)
8885 return -1;
8886 } else {
8887 if (register_ind_insn(ppc_opcodes, insn->opc1,
8888 insn->opc2, &insn->handler) < 0)
8889 return -1;
8890 }
8891 } else {
8892 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
8893 return -1;
8894 }
8895
8896 return 0;
8897 }
8898
8899 static int test_opcode_table (opc_handler_t **table, int len)
8900 {
8901 int i, count, tmp;
8902
8903 for (i = 0, count = 0; i < len; i++) {
8904 /* Consistency fixup */
8905 if (table[i] == NULL)
8906 table[i] = &invalid_handler;
8907 if (table[i] != &invalid_handler) {
8908 if (is_indirect_opcode(table[i])) {
8909 tmp = test_opcode_table(ind_table(table[i]),
8910 PPC_CPU_INDIRECT_OPCODES_LEN);
8911 if (tmp == 0) {
8912 free(table[i]);
8913 table[i] = &invalid_handler;
8914 } else {
8915 count++;
8916 }
8917 } else {
8918 count++;
8919 }
8920 }
8921 }
8922
8923 return count;
8924 }
8925
8926 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
8927 {
8928 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0)
8929 printf("*** WARNING: no opcode defined !\n");
8930 }
8931
8932 /*****************************************************************************/
8933 static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
8934 {
8935 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8936 CPUPPCState *env = &cpu->env;
8937 opcode_t *opc;
8938
8939 fill_new_table(env->opcodes, PPC_CPU_OPCODES_LEN);
8940 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
8941 if (((opc->handler.type & pcc->insns_flags) != 0) ||
8942 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
8943 if (register_insn(env->opcodes, opc) < 0) {
8944 error_setg(errp, "ERROR initializing PowerPC instruction "
8945 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
8946 opc->opc3);
8947 return;
8948 }
8949 }
8950 }
8951 fix_opcode_tables(env->opcodes);
8952 fflush(stdout);
8953 fflush(stderr);
8954 }
8955
8956 #if defined(PPC_DUMP_CPU)
8957 static void dump_ppc_insns (CPUPPCState *env)
8958 {
8959 opc_handler_t **table, *handler;
8960 const char *p, *q;
8961 uint8_t opc1, opc2, opc3;
8962
8963 printf("Instructions set:\n");
8964 /* opc1 is 6 bits long */
8965 for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) {
8966 table = env->opcodes;
8967 handler = table[opc1];
8968 if (is_indirect_opcode(handler)) {
8969 /* opc2 is 5 bits long */
8970 for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) {
8971 table = env->opcodes;
8972 handler = env->opcodes[opc1];
8973 table = ind_table(handler);
8974 handler = table[opc2];
8975 if (is_indirect_opcode(handler)) {
8976 table = ind_table(handler);
8977 /* opc3 is 5 bits long */
8978 for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN;
8979 opc3++) {
8980 handler = table[opc3];
8981 if (handler->handler != &gen_invalid) {
8982 /* Special hack to properly dump SPE insns */
8983 p = strchr(handler->oname, '_');
8984 if (p == NULL) {
8985 printf("INSN: %02x %02x %02x (%02d %04d) : "
8986 "%s\n",
8987 opc1, opc2, opc3, opc1,
8988 (opc3 << 5) | opc2,
8989 handler->oname);
8990 } else {
8991 q = "speundef";
8992 if ((p - handler->oname) != strlen(q) ||
8993 memcmp(handler->oname, q, strlen(q)) != 0) {
8994 /* First instruction */
8995 printf("INSN: %02x %02x %02x (%02d %04d) : "
8996 "%.*s\n",
8997 opc1, opc2 << 1, opc3, opc1,
8998 (opc3 << 6) | (opc2 << 1),
8999 (int)(p - handler->oname),
9000 handler->oname);
9001 }
9002 if (strcmp(p + 1, q) != 0) {
9003 /* Second instruction */
9004 printf("INSN: %02x %02x %02x (%02d %04d) : "
9005 "%s\n",
9006 opc1, (opc2 << 1) | 1, opc3, opc1,
9007 (opc3 << 6) | (opc2 << 1) | 1,
9008 p + 1);
9009 }
9010 }
9011 }
9012 }
9013 } else {
9014 if (handler->handler != &gen_invalid) {
9015 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9016 opc1, opc2, opc1, opc2, handler->oname);
9017 }
9018 }
9019 }
9020 } else {
9021 if (handler->handler != &gen_invalid) {
9022 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9023 opc1, opc1, handler->oname);
9024 }
9025 }
9026 }
9027 }
9028 #endif
9029
9030 static bool avr_need_swap(CPUPPCState *env)
9031 {
9032 #ifdef HOST_WORDS_BIGENDIAN
9033 return msr_le;
9034 #else
9035 return !msr_le;
9036 #endif
9037 }
9038
9039 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9040 {
9041 if (n < 32) {
9042 stfq_p(mem_buf, env->fpr[n]);
9043 ppc_maybe_bswap_register(env, mem_buf, 8);
9044 return 8;
9045 }
9046 if (n == 32) {
9047 stl_p(mem_buf, env->fpscr);
9048 ppc_maybe_bswap_register(env, mem_buf, 4);
9049 return 4;
9050 }
9051 return 0;
9052 }
9053
9054 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9055 {
9056 if (n < 32) {
9057 ppc_maybe_bswap_register(env, mem_buf, 8);
9058 env->fpr[n] = ldfq_p(mem_buf);
9059 return 8;
9060 }
9061 if (n == 32) {
9062 ppc_maybe_bswap_register(env, mem_buf, 4);
9063 helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
9064 return 4;
9065 }
9066 return 0;
9067 }
9068
9069 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9070 {
9071 if (n < 32) {
9072 if (!avr_need_swap(env)) {
9073 stq_p(mem_buf, env->avr[n].u64[0]);
9074 stq_p(mem_buf+8, env->avr[n].u64[1]);
9075 } else {
9076 stq_p(mem_buf, env->avr[n].u64[1]);
9077 stq_p(mem_buf+8, env->avr[n].u64[0]);
9078 }
9079 ppc_maybe_bswap_register(env, mem_buf, 8);
9080 ppc_maybe_bswap_register(env, mem_buf + 8, 8);
9081 return 16;
9082 }
9083 if (n == 32) {
9084 stl_p(mem_buf, env->vscr);
9085 ppc_maybe_bswap_register(env, mem_buf, 4);
9086 return 4;
9087 }
9088 if (n == 33) {
9089 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9090 ppc_maybe_bswap_register(env, mem_buf, 4);
9091 return 4;
9092 }
9093 return 0;
9094 }
9095
9096 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9097 {
9098 if (n < 32) {
9099 ppc_maybe_bswap_register(env, mem_buf, 8);
9100 ppc_maybe_bswap_register(env, mem_buf + 8, 8);
9101 if (!avr_need_swap(env)) {
9102 env->avr[n].u64[0] = ldq_p(mem_buf);
9103 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9104 } else {
9105 env->avr[n].u64[1] = ldq_p(mem_buf);
9106 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9107 }
9108 return 16;
9109 }
9110 if (n == 32) {
9111 ppc_maybe_bswap_register(env, mem_buf, 4);
9112 env->vscr = ldl_p(mem_buf);
9113 return 4;
9114 }
9115 if (n == 33) {
9116 ppc_maybe_bswap_register(env, mem_buf, 4);
9117 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9118 return 4;
9119 }
9120 return 0;
9121 }
9122
9123 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9124 {
9125 if (n < 32) {
9126 #if defined(TARGET_PPC64)
9127 stl_p(mem_buf, env->gpr[n] >> 32);
9128 ppc_maybe_bswap_register(env, mem_buf, 4);
9129 #else
9130 stl_p(mem_buf, env->gprh[n]);
9131 #endif
9132 return 4;
9133 }
9134 if (n == 32) {
9135 stq_p(mem_buf, env->spe_acc);
9136 ppc_maybe_bswap_register(env, mem_buf, 8);
9137 return 8;
9138 }
9139 if (n == 33) {
9140 stl_p(mem_buf, env->spe_fscr);
9141 ppc_maybe_bswap_register(env, mem_buf, 4);
9142 return 4;
9143 }
9144 return 0;
9145 }
9146
9147 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9148 {
9149 if (n < 32) {
9150 #if defined(TARGET_PPC64)
9151 target_ulong lo = (uint32_t)env->gpr[n];
9152 target_ulong hi;
9153
9154 ppc_maybe_bswap_register(env, mem_buf, 4);
9155
9156 hi = (target_ulong)ldl_p(mem_buf) << 32;
9157 env->gpr[n] = lo | hi;
9158 #else
9159 env->gprh[n] = ldl_p(mem_buf);
9160 #endif
9161 return 4;
9162 }
9163 if (n == 32) {
9164 ppc_maybe_bswap_register(env, mem_buf, 8);
9165 env->spe_acc = ldq_p(mem_buf);
9166 return 8;
9167 }
9168 if (n == 33) {
9169 ppc_maybe_bswap_register(env, mem_buf, 4);
9170 env->spe_fscr = ldl_p(mem_buf);
9171 return 4;
9172 }
9173 return 0;
9174 }
9175
9176 static int gdb_get_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9177 {
9178 if (n < 32) {
9179 stq_p(mem_buf, env->vsr[n]);
9180 ppc_maybe_bswap_register(env, mem_buf, 8);
9181 return 8;
9182 }
9183 return 0;
9184 }
9185
9186 static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9187 {
9188 if (n < 32) {
9189 ppc_maybe_bswap_register(env, mem_buf, 8);
9190 env->vsr[n] = ldq_p(mem_buf);
9191 return 8;
9192 }
9193 return 0;
9194 }
9195
9196 static int ppc_fixup_cpu(PowerPCCPU *cpu)
9197 {
9198 CPUPPCState *env = &cpu->env;
9199
9200 /* TCG doesn't (yet) emulate some groups of instructions that
9201 * are implemented on some otherwise supported CPUs (e.g. VSX
9202 * and decimal floating point instructions on POWER7). We
9203 * remove unsupported instruction groups from the cpu state's
9204 * instruction masks and hope the guest can cope. For at
9205 * least the pseries machine, the unavailability of these
9206 * instructions can be advertised to the guest via the device
9207 * tree. */
9208 if ((env->insns_flags & ~PPC_TCG_INSNS)
9209 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
9210 fprintf(stderr, "Warning: Disabling some instructions which are not "
9211 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
9212 env->insns_flags & ~PPC_TCG_INSNS,
9213 env->insns_flags2 & ~PPC_TCG_INSNS2);
9214 }
9215 env->insns_flags &= PPC_TCG_INSNS;
9216 env->insns_flags2 &= PPC_TCG_INSNS2;
9217 return 0;
9218 }
9219
9220 static inline bool ppc_cpu_is_valid(PowerPCCPUClass *pcc)
9221 {
9222 #ifdef TARGET_PPCEMB
9223 return pcc->mmu_model == POWERPC_MMU_BOOKE ||
9224 pcc->mmu_model == POWERPC_MMU_SOFT_4xx ||
9225 pcc->mmu_model == POWERPC_MMU_SOFT_4xx_Z;
9226 #else
9227 return true;
9228 #endif
9229 }
9230
9231 static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
9232 {
9233 CPUState *cs = CPU(dev);
9234 PowerPCCPU *cpu = POWERPC_CPU(dev);
9235 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9236 Error *local_err = NULL;
9237 #if !defined(CONFIG_USER_ONLY)
9238 int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1;
9239 #endif
9240
9241 #if !defined(CONFIG_USER_ONLY)
9242 if (smp_threads > max_smt) {
9243 error_setg(errp, "Cannot support more than %d threads on PPC with %s",
9244 max_smt, kvm_enabled() ? "KVM" : "TCG");
9245 return;
9246 }
9247 if (!is_power_of_2(smp_threads)) {
9248 error_setg(errp, "Cannot support %d threads on PPC with %s, "
9249 "threads count must be a power of 2.",
9250 smp_threads, kvm_enabled() ? "KVM" : "TCG");
9251 return;
9252 }
9253 #endif
9254
9255 cpu_exec_init(cs, &local_err);
9256 if (local_err != NULL) {
9257 error_propagate(errp, local_err);
9258 return;
9259 }
9260
9261 #if !defined(CONFIG_USER_ONLY)
9262 cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt
9263 + (cs->cpu_index % smp_threads);
9264
9265 if (kvm_enabled() && !kvm_vcpu_id_is_valid(cpu->cpu_dt_id)) {
9266 error_setg(errp, "Can't create CPU with id %d in KVM", cpu->cpu_dt_id);
9267 error_append_hint(errp, "Adjust the number of cpus to %d "
9268 "or try to raise the number of threads per core\n",
9269 cpu->cpu_dt_id * smp_threads / max_smt);
9270 return;
9271 }
9272 #endif
9273
9274 if (tcg_enabled()) {
9275 if (ppc_fixup_cpu(cpu) != 0) {
9276 error_setg(errp, "Unable to emulate selected CPU with TCG");
9277 return;
9278 }
9279 }
9280
9281 #if defined(TARGET_PPCEMB)
9282 if (!ppc_cpu_is_valid(pcc)) {
9283 error_setg(errp, "CPU does not possess a BookE or 4xx MMU. "
9284 "Please use qemu-system-ppc or qemu-system-ppc64 instead "
9285 "or choose another CPU model.");
9286 return;
9287 }
9288 #endif
9289
9290 create_ppc_opcodes(cpu, &local_err);
9291 if (local_err != NULL) {
9292 error_propagate(errp, local_err);
9293 return;
9294 }
9295 init_ppc_proc(cpu);
9296
9297 if (pcc->insns_flags & PPC_FLOAT) {
9298 gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
9299 33, "power-fpu.xml", 0);
9300 }
9301 if (pcc->insns_flags & PPC_ALTIVEC) {
9302 gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
9303 34, "power-altivec.xml", 0);
9304 }
9305 if (pcc->insns_flags & PPC_SPE) {
9306 gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
9307 34, "power-spe.xml", 0);
9308 }
9309 if (pcc->insns_flags2 & PPC2_VSX) {
9310 gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg,
9311 32, "power-vsx.xml", 0);
9312 }
9313
9314 qemu_init_vcpu(cs);
9315
9316 pcc->parent_realize(dev, errp);
9317
9318 #if defined(PPC_DUMP_CPU)
9319 {
9320 CPUPPCState *env = &cpu->env;
9321 const char *mmu_model, *excp_model, *bus_model;
9322 switch (env->mmu_model) {
9323 case POWERPC_MMU_32B:
9324 mmu_model = "PowerPC 32";
9325 break;
9326 case POWERPC_MMU_SOFT_6xx:
9327 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9328 break;
9329 case POWERPC_MMU_SOFT_74xx:
9330 mmu_model = "PowerPC 74xx with software driven TLBs";
9331 break;
9332 case POWERPC_MMU_SOFT_4xx:
9333 mmu_model = "PowerPC 4xx with software driven TLBs";
9334 break;
9335 case POWERPC_MMU_SOFT_4xx_Z:
9336 mmu_model = "PowerPC 4xx with software driven TLBs "
9337 "and zones protections";
9338 break;
9339 case POWERPC_MMU_REAL:
9340 mmu_model = "PowerPC real mode only";
9341 break;
9342 case POWERPC_MMU_MPC8xx:
9343 mmu_model = "PowerPC MPC8xx";
9344 break;
9345 case POWERPC_MMU_BOOKE:
9346 mmu_model = "PowerPC BookE";
9347 break;
9348 case POWERPC_MMU_BOOKE206:
9349 mmu_model = "PowerPC BookE 2.06";
9350 break;
9351 case POWERPC_MMU_601:
9352 mmu_model = "PowerPC 601";
9353 break;
9354 #if defined (TARGET_PPC64)
9355 case POWERPC_MMU_64B:
9356 mmu_model = "PowerPC 64";
9357 break;
9358 #endif
9359 default:
9360 mmu_model = "Unknown or invalid";
9361 break;
9362 }
9363 switch (env->excp_model) {
9364 case POWERPC_EXCP_STD:
9365 excp_model = "PowerPC";
9366 break;
9367 case POWERPC_EXCP_40x:
9368 excp_model = "PowerPC 40x";
9369 break;
9370 case POWERPC_EXCP_601:
9371 excp_model = "PowerPC 601";
9372 break;
9373 case POWERPC_EXCP_602:
9374 excp_model = "PowerPC 602";
9375 break;
9376 case POWERPC_EXCP_603:
9377 excp_model = "PowerPC 603";
9378 break;
9379 case POWERPC_EXCP_603E:
9380 excp_model = "PowerPC 603e";
9381 break;
9382 case POWERPC_EXCP_604:
9383 excp_model = "PowerPC 604";
9384 break;
9385 case POWERPC_EXCP_7x0:
9386 excp_model = "PowerPC 740/750";
9387 break;
9388 case POWERPC_EXCP_7x5:
9389 excp_model = "PowerPC 745/755";
9390 break;
9391 case POWERPC_EXCP_74xx:
9392 excp_model = "PowerPC 74xx";
9393 break;
9394 case POWERPC_EXCP_BOOKE:
9395 excp_model = "PowerPC BookE";
9396 break;
9397 #if defined (TARGET_PPC64)
9398 case POWERPC_EXCP_970:
9399 excp_model = "PowerPC 970";
9400 break;
9401 #endif
9402 default:
9403 excp_model = "Unknown or invalid";
9404 break;
9405 }
9406 switch (env->bus_model) {
9407 case PPC_FLAGS_INPUT_6xx:
9408 bus_model = "PowerPC 6xx";
9409 break;
9410 case PPC_FLAGS_INPUT_BookE:
9411 bus_model = "PowerPC BookE";
9412 break;
9413 case PPC_FLAGS_INPUT_405:
9414 bus_model = "PowerPC 405";
9415 break;
9416 case PPC_FLAGS_INPUT_401:
9417 bus_model = "PowerPC 401/403";
9418 break;
9419 case PPC_FLAGS_INPUT_RCPU:
9420 bus_model = "RCPU / MPC8xx";
9421 break;
9422 #if defined (TARGET_PPC64)
9423 case PPC_FLAGS_INPUT_970:
9424 bus_model = "PowerPC 970";
9425 break;
9426 #endif
9427 default:
9428 bus_model = "Unknown or invalid";
9429 break;
9430 }
9431 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9432 " MMU model : %s\n",
9433 object_class_get_name(OBJECT_CLASS(pcc)),
9434 pcc->pvr, pcc->msr_mask, mmu_model);
9435 #if !defined(CONFIG_USER_ONLY)
9436 if (env->tlb.tlb6) {
9437 printf(" %d %s TLB in %d ways\n",
9438 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9439 env->nb_ways);
9440 }
9441 #endif
9442 printf(" Exceptions model : %s\n"
9443 " Bus model : %s\n",
9444 excp_model, bus_model);
9445 printf(" MSR features :\n");
9446 if (env->flags & POWERPC_FLAG_SPE)
9447 printf(" signal processing engine enable"
9448 "\n");
9449 else if (env->flags & POWERPC_FLAG_VRE)
9450 printf(" vector processor enable\n");
9451 if (env->flags & POWERPC_FLAG_TGPR)
9452 printf(" temporary GPRs\n");
9453 else if (env->flags & POWERPC_FLAG_CE)
9454 printf(" critical input enable\n");
9455 if (env->flags & POWERPC_FLAG_SE)
9456 printf(" single-step trace mode\n");
9457 else if (env->flags & POWERPC_FLAG_DWE)
9458 printf(" debug wait enable\n");
9459 else if (env->flags & POWERPC_FLAG_UBLE)
9460 printf(" user BTB lock enable\n");
9461 if (env->flags & POWERPC_FLAG_BE)
9462 printf(" branch-step trace mode\n");
9463 else if (env->flags & POWERPC_FLAG_DE)
9464 printf(" debug interrupt enable\n");
9465 if (env->flags & POWERPC_FLAG_PX)
9466 printf(" inclusive protection\n");
9467 else if (env->flags & POWERPC_FLAG_PMM)
9468 printf(" performance monitor mark\n");
9469 if (env->flags == POWERPC_FLAG_NONE)
9470 printf(" none\n");
9471 printf(" Time-base/decrementer clock source: %s\n",
9472 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
9473 dump_ppc_insns(env);
9474 dump_ppc_sprs(env);
9475 fflush(stdout);
9476 }
9477 #endif
9478 }
9479
9480 static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
9481 {
9482 PowerPCCPU *cpu = POWERPC_CPU(dev);
9483 CPUPPCState *env = &cpu->env;
9484 opc_handler_t **table;
9485 int i, j;
9486
9487 cpu_exec_exit(CPU(dev));
9488
9489 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
9490 if (env->opcodes[i] == &invalid_handler) {
9491 continue;
9492 }
9493 if (is_indirect_opcode(env->opcodes[i])) {
9494 table = ind_table(env->opcodes[i]);
9495 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
9496 if (table[j] != &invalid_handler &&
9497 is_indirect_opcode(table[j])) {
9498 g_free((opc_handler_t *)((uintptr_t)table[j] &
9499 ~PPC_INDIRECT));
9500 }
9501 }
9502 g_free((opc_handler_t *)((uintptr_t)env->opcodes[i] &
9503 ~PPC_INDIRECT));
9504 }
9505 }
9506 }
9507
9508 int ppc_get_compat_smt_threads(PowerPCCPU *cpu)
9509 {
9510 int ret = MIN(smp_threads, kvmppc_smt_threads());
9511
9512 switch (cpu->cpu_version) {
9513 case CPU_POWERPC_LOGICAL_2_05:
9514 ret = MIN(ret, 2);
9515 break;
9516 case CPU_POWERPC_LOGICAL_2_06:
9517 ret = MIN(ret, 4);
9518 break;
9519 case CPU_POWERPC_LOGICAL_2_07:
9520 ret = MIN(ret, 8);
9521 break;
9522 }
9523
9524 return ret;
9525 }
9526
9527 #ifdef TARGET_PPC64
9528 void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp)
9529 {
9530 int ret = 0;
9531 CPUPPCState *env = &cpu->env;
9532 PowerPCCPUClass *host_pcc;
9533
9534 cpu->cpu_version = cpu_version;
9535
9536 switch (cpu_version) {
9537 case CPU_POWERPC_LOGICAL_2_05:
9538 env->spr[SPR_PCR] = PCR_TM_DIS | PCR_VSX_DIS | PCR_COMPAT_2_07 |
9539 PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
9540 break;
9541 case CPU_POWERPC_LOGICAL_2_06:
9542 case CPU_POWERPC_LOGICAL_2_06_PLUS:
9543 env->spr[SPR_PCR] = PCR_TM_DIS | PCR_COMPAT_2_07 | PCR_COMPAT_2_06;
9544 break;
9545 case CPU_POWERPC_LOGICAL_2_07:
9546 env->spr[SPR_PCR] = PCR_COMPAT_2_07;
9547 break;
9548 default:
9549 env->spr[SPR_PCR] = 0;
9550 break;
9551 }
9552
9553 host_pcc = kvm_ppc_get_host_cpu_class();
9554 if (host_pcc) {
9555 env->spr[SPR_PCR] &= host_pcc->pcr_mask;
9556 }
9557
9558 if (kvm_enabled()) {
9559 ret = kvmppc_set_compat(cpu, cpu->cpu_version);
9560 if (ret < 0) {
9561 error_setg_errno(errp, -ret,
9562 "Unable to set CPU compatibility mode in KVM");
9563 }
9564 }
9565 }
9566 #endif
9567
9568 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
9569 {
9570 ObjectClass *oc = (ObjectClass *)a;
9571 uint32_t pvr = *(uint32_t *)b;
9572 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
9573
9574 /* -cpu host does a PVR lookup during construction */
9575 if (unlikely(strcmp(object_class_get_name(oc),
9576 TYPE_HOST_POWERPC_CPU) == 0)) {
9577 return -1;
9578 }
9579
9580 if (!ppc_cpu_is_valid(pcc)) {
9581 return -1;
9582 }
9583
9584 return pcc->pvr == pvr ? 0 : -1;
9585 }
9586
9587 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
9588 {
9589 GSList *list, *item;
9590 PowerPCCPUClass *pcc = NULL;
9591
9592 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9593 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
9594 if (item != NULL) {
9595 pcc = POWERPC_CPU_CLASS(item->data);
9596 }
9597 g_slist_free(list);
9598
9599 return pcc;
9600 }
9601
9602 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
9603 {
9604 ObjectClass *oc = (ObjectClass *)a;
9605 uint32_t pvr = *(uint32_t *)b;
9606 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
9607
9608 /* -cpu host does a PVR lookup during construction */
9609 if (unlikely(strcmp(object_class_get_name(oc),
9610 TYPE_HOST_POWERPC_CPU) == 0)) {
9611 return -1;
9612 }
9613
9614 if (!ppc_cpu_is_valid(pcc)) {
9615 return -1;
9616 }
9617
9618 if (pcc->pvr_match(pcc, pvr)) {
9619 return 0;
9620 }
9621
9622 return -1;
9623 }
9624
9625 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
9626 {
9627 GSList *list, *item;
9628 PowerPCCPUClass *pcc = NULL;
9629
9630 list = object_class_get_list(TYPE_POWERPC_CPU, true);
9631 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
9632 if (item != NULL) {
9633 pcc = POWERPC_CPU_CLASS(item->data);
9634 }
9635 g_slist_free(list);
9636
9637 return pcc;
9638 }
9639
9640 static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
9641 {
9642 ObjectClass *oc = (ObjectClass *)a;
9643 const char *name = b;
9644 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9645
9646 if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
9647 ppc_cpu_is_valid(pcc) &&
9648 strcmp(object_class_get_name(oc) + strlen(name),
9649 "-" TYPE_POWERPC_CPU) == 0) {
9650 return 0;
9651 }
9652 return -1;
9653 }
9654
9655
9656 static ObjectClass *ppc_cpu_class_by_name(const char *name);
9657
9658 static ObjectClass *ppc_cpu_class_by_alias(PowerPCCPUAlias *alias)
9659 {
9660 ObjectClass *invalid_class = (void*)ppc_cpu_class_by_alias;
9661
9662 /* Cache target class lookups in the alias table */
9663 if (!alias->oc) {
9664 alias->oc = ppc_cpu_class_by_name(alias->model);
9665 if (!alias->oc) {
9666 /* Fast check for non-existing aliases */
9667 alias->oc = invalid_class;
9668 }
9669 }
9670
9671 if (alias->oc == invalid_class) {
9672 return NULL;
9673 } else {
9674 return alias->oc;
9675 }
9676 }
9677
9678 static ObjectClass *ppc_cpu_class_by_name(const char *name)
9679 {
9680 GSList *list, *item;
9681 ObjectClass *ret = NULL;
9682 const char *p;
9683 int i, len;
9684
9685 /* Check if the given name is a PVR */
9686 len = strlen(name);
9687 if (len == 10 && name[0] == '0' && name[1] == 'x') {
9688 p = name + 2;
9689 goto check_pvr;
9690 } else if (len == 8) {
9691 p = name;
9692 check_pvr:
9693 for (i = 0; i < 8; i++) {
9694 if (!qemu_isxdigit(*p++))
9695 break;
9696 }
9697 if (i == 8) {
9698 return OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
9699 }
9700 }
9701
9702 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9703 item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
9704 if (item != NULL) {
9705 ret = OBJECT_CLASS(item->data);
9706 }
9707 g_slist_free(list);
9708
9709 if (ret) {
9710 return ret;
9711 }
9712
9713 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9714 if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
9715 return ppc_cpu_class_by_alias(&ppc_cpu_aliases[i]);
9716 }
9717 }
9718
9719 return NULL;
9720 }
9721
9722 PowerPCCPU *cpu_ppc_init(const char *cpu_model)
9723 {
9724 return POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model));
9725 }
9726
9727 /* Sort by PVR, ordering special case "host" last. */
9728 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
9729 {
9730 ObjectClass *oc_a = (ObjectClass *)a;
9731 ObjectClass *oc_b = (ObjectClass *)b;
9732 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
9733 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
9734 const char *name_a = object_class_get_name(oc_a);
9735 const char *name_b = object_class_get_name(oc_b);
9736
9737 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
9738 return 1;
9739 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
9740 return -1;
9741 } else {
9742 /* Avoid an integer overflow during subtraction */
9743 if (pcc_a->pvr < pcc_b->pvr) {
9744 return -1;
9745 } else if (pcc_a->pvr > pcc_b->pvr) {
9746 return 1;
9747 } else {
9748 return 0;
9749 }
9750 }
9751 }
9752
9753 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
9754 {
9755 ObjectClass *oc = data;
9756 CPUListState *s = user_data;
9757 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9758 const char *typename = object_class_get_name(oc);
9759 char *name;
9760 int i;
9761
9762 if (!ppc_cpu_is_valid(pcc)) {
9763 return;
9764 }
9765 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
9766 return;
9767 }
9768
9769 name = g_strndup(typename,
9770 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
9771 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
9772 name, pcc->pvr);
9773 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9774 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
9775 ObjectClass *alias_oc = ppc_cpu_class_by_alias(alias);
9776
9777 if (alias_oc != oc) {
9778 continue;
9779 }
9780 (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n",
9781 alias->alias, name);
9782 }
9783 g_free(name);
9784 }
9785
9786 void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
9787 {
9788 CPUListState s = {
9789 .file = f,
9790 .cpu_fprintf = cpu_fprintf,
9791 };
9792 GSList *list;
9793
9794 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9795 list = g_slist_sort(list, ppc_cpu_list_compare);
9796 g_slist_foreach(list, ppc_cpu_list_entry, &s);
9797 g_slist_free(list);
9798
9799 #ifdef CONFIG_KVM
9800 cpu_fprintf(f, "\n");
9801 cpu_fprintf(f, "PowerPC %-16s\n", "host");
9802 #endif
9803 }
9804
9805 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
9806 {
9807 ObjectClass *oc = data;
9808 CpuDefinitionInfoList **first = user_data;
9809 const char *typename;
9810 CpuDefinitionInfoList *entry;
9811 CpuDefinitionInfo *info;
9812 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9813
9814 if (!ppc_cpu_is_valid(pcc)) {
9815 return;
9816 }
9817
9818 typename = object_class_get_name(oc);
9819 info = g_malloc0(sizeof(*info));
9820 info->name = g_strndup(typename,
9821 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
9822
9823 entry = g_malloc0(sizeof(*entry));
9824 entry->value = info;
9825 entry->next = *first;
9826 *first = entry;
9827 }
9828
9829 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
9830 {
9831 CpuDefinitionInfoList *cpu_list = NULL;
9832 GSList *list;
9833 int i;
9834
9835 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9836 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
9837 g_slist_free(list);
9838
9839 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9840 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
9841 ObjectClass *oc;
9842 CpuDefinitionInfoList *entry;
9843 CpuDefinitionInfo *info;
9844
9845 oc = ppc_cpu_class_by_alias(alias);
9846 if (oc == NULL) {
9847 continue;
9848 }
9849
9850 info = g_malloc0(sizeof(*info));
9851 info->name = g_strdup(alias->alias);
9852
9853 entry = g_malloc0(sizeof(*entry));
9854 entry->value = info;
9855 entry->next = cpu_list;
9856 cpu_list = entry;
9857 }
9858
9859 return cpu_list;
9860 }
9861
9862 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
9863 {
9864 PowerPCCPU *cpu = POWERPC_CPU(cs);
9865
9866 cpu->env.nip = value;
9867 }
9868
9869 static bool ppc_cpu_has_work(CPUState *cs)
9870 {
9871 PowerPCCPU *cpu = POWERPC_CPU(cs);
9872 CPUPPCState *env = &cpu->env;
9873
9874 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
9875 }
9876
9877 static void ppc_cpu_exec_enter(CPUState *cs)
9878 {
9879 PowerPCCPU *cpu = POWERPC_CPU(cs);
9880 CPUPPCState *env = &cpu->env;
9881
9882 env->reserve_addr = -1;
9883 }
9884
9885 /* CPUClass::reset() */
9886 static void ppc_cpu_reset(CPUState *s)
9887 {
9888 PowerPCCPU *cpu = POWERPC_CPU(s);
9889 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9890 CPUPPCState *env = &cpu->env;
9891 target_ulong msr;
9892 int i;
9893
9894 pcc->parent_reset(s);
9895
9896 msr = (target_ulong)0;
9897 msr |= (target_ulong)MSR_HVB;
9898 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
9899 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
9900 msr |= (target_ulong)1 << MSR_EP;
9901 #if defined(DO_SINGLE_STEP) && 0
9902 /* Single step trace mode */
9903 msr |= (target_ulong)1 << MSR_SE;
9904 msr |= (target_ulong)1 << MSR_BE;
9905 #endif
9906 #if defined(CONFIG_USER_ONLY)
9907 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
9908 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
9909 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
9910 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
9911 msr |= (target_ulong)1 << MSR_PR;
9912 #if defined(TARGET_PPC64)
9913 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
9914 #endif
9915 #if !defined(TARGET_WORDS_BIGENDIAN)
9916 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
9917 if (!((env->msr_mask >> MSR_LE) & 1)) {
9918 fprintf(stderr, "Selected CPU does not support little-endian.\n");
9919 exit(1);
9920 }
9921 #endif
9922 #endif
9923
9924 #if defined(TARGET_PPC64)
9925 if (env->mmu_model & POWERPC_MMU_64) {
9926 msr |= (1ULL << MSR_SF);
9927 }
9928 #endif
9929
9930 hreg_store_msr(env, msr, 1);
9931
9932 #if !defined(CONFIG_USER_ONLY)
9933 env->nip = env->hreset_vector | env->excp_prefix;
9934 if (env->mmu_model != POWERPC_MMU_REAL) {
9935 ppc_tlb_invalidate_all(env);
9936 }
9937 #endif
9938
9939 hreg_compute_hflags(env);
9940 env->reserve_addr = (target_ulong)-1ULL;
9941 /* Be sure no exception or interrupt is pending */
9942 env->pending_interrupts = 0;
9943 s->exception_index = POWERPC_EXCP_NONE;
9944 env->error_code = 0;
9945
9946 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
9947 env->vpa_addr = 0;
9948 env->slb_shadow_addr = 0;
9949 env->slb_shadow_size = 0;
9950 env->dtl_addr = 0;
9951 env->dtl_size = 0;
9952 #endif /* TARGET_PPC64 */
9953
9954 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
9955 ppc_spr_t *spr = &env->spr_cb[i];
9956
9957 if (!spr->name) {
9958 continue;
9959 }
9960 env->spr[i] = spr->default_value;
9961 }
9962
9963 /* Flush all TLBs */
9964 tlb_flush(s, 1);
9965 }
9966
9967 #ifndef CONFIG_USER_ONLY
9968 static bool ppc_cpu_is_big_endian(CPUState *cs)
9969 {
9970 PowerPCCPU *cpu = POWERPC_CPU(cs);
9971 CPUPPCState *env = &cpu->env;
9972
9973 cpu_synchronize_state(cs);
9974
9975 return !msr_le;
9976 }
9977 #endif
9978
9979 static void ppc_cpu_initfn(Object *obj)
9980 {
9981 CPUState *cs = CPU(obj);
9982 PowerPCCPU *cpu = POWERPC_CPU(obj);
9983 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9984 CPUPPCState *env = &cpu->env;
9985
9986 cs->env_ptr = env;
9987
9988 env->msr_mask = pcc->msr_mask;
9989 env->mmu_model = pcc->mmu_model;
9990 env->excp_model = pcc->excp_model;
9991 env->bus_model = pcc->bus_model;
9992 env->insns_flags = pcc->insns_flags;
9993 env->insns_flags2 = pcc->insns_flags2;
9994 env->flags = pcc->flags;
9995 env->bfd_mach = pcc->bfd_mach;
9996 env->check_pow = pcc->check_pow;
9997
9998 /* Mark HV mode as supported if the CPU has an MSR_HV bit
9999 * in the msr_mask. The mask can later be cleared by PAPR
10000 * mode but the hv mode support will remain, thus enforcing
10001 * that we cannot use priv. instructions in guest in PAPR
10002 * mode. For 970 we currently simply don't set HV in msr_mask
10003 * thus simulating an "Apple mode" 970. If we ever want to
10004 * support 970 HV mode, we'll have to add a processor attribute
10005 * of some sort.
10006 */
10007 #if !defined(CONFIG_USER_ONLY)
10008 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
10009 #endif
10010
10011 #if defined(TARGET_PPC64)
10012 if (pcc->sps) {
10013 env->sps = *pcc->sps;
10014 } else if (env->mmu_model & POWERPC_MMU_64) {
10015 /* Use default sets of page sizes */
10016 static const struct ppc_segment_page_sizes defsps = {
10017 .sps = {
10018 { .page_shift = 12, /* 4K */
10019 .slb_enc = 0,
10020 .enc = { { .page_shift = 12, .pte_enc = 0 } }
10021 },
10022 { .page_shift = 24, /* 16M */
10023 .slb_enc = 0x100,
10024 .enc = { { .page_shift = 24, .pte_enc = 0 } }
10025 },
10026 },
10027 };
10028 env->sps = defsps;
10029 }
10030 #endif /* defined(TARGET_PPC64) */
10031
10032 if (tcg_enabled()) {
10033 ppc_translate_init();
10034 }
10035 }
10036
10037 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
10038 {
10039 return pcc->pvr == pvr;
10040 }
10041
10042 static gchar *ppc_gdb_arch_name(CPUState *cs)
10043 {
10044 #if defined(TARGET_PPC64)
10045 return g_strdup("powerpc:common64");
10046 #else
10047 return g_strdup("powerpc:common");
10048 #endif
10049 }
10050
10051 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
10052 {
10053 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10054 CPUClass *cc = CPU_CLASS(oc);
10055 DeviceClass *dc = DEVICE_CLASS(oc);
10056
10057 pcc->parent_realize = dc->realize;
10058 pcc->pvr_match = ppc_pvr_match_default;
10059 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
10060 dc->realize = ppc_cpu_realizefn;
10061 dc->unrealize = ppc_cpu_unrealizefn;
10062
10063 pcc->parent_reset = cc->reset;
10064 cc->reset = ppc_cpu_reset;
10065
10066 cc->class_by_name = ppc_cpu_class_by_name;
10067 cc->has_work = ppc_cpu_has_work;
10068 cc->do_interrupt = ppc_cpu_do_interrupt;
10069 cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt;
10070 cc->dump_state = ppc_cpu_dump_state;
10071 cc->dump_statistics = ppc_cpu_dump_statistics;
10072 cc->set_pc = ppc_cpu_set_pc;
10073 cc->gdb_read_register = ppc_cpu_gdb_read_register;
10074 cc->gdb_write_register = ppc_cpu_gdb_write_register;
10075 #ifdef CONFIG_USER_ONLY
10076 cc->handle_mmu_fault = ppc_cpu_handle_mmu_fault;
10077 #else
10078 cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
10079 cc->vmsd = &vmstate_ppc_cpu;
10080 #if defined(TARGET_PPC64)
10081 cc->write_elf64_note = ppc64_cpu_write_elf64_note;
10082 #endif
10083 #endif
10084 cc->cpu_exec_enter = ppc_cpu_exec_enter;
10085
10086 cc->gdb_num_core_regs = 71;
10087
10088 #ifdef USE_APPLE_GDB
10089 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
10090 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
10091 cc->gdb_num_core_regs = 71 + 32;
10092 #endif
10093
10094 cc->gdb_arch_name = ppc_gdb_arch_name;
10095 #if defined(TARGET_PPC64)
10096 cc->gdb_core_xml_file = "power64-core.xml";
10097 #else
10098 cc->gdb_core_xml_file = "power-core.xml";
10099 #endif
10100 #ifndef CONFIG_USER_ONLY
10101 cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
10102 #endif
10103
10104 dc->fw_name = "PowerPC,UNKNOWN";
10105 }
10106
10107 static const TypeInfo ppc_cpu_type_info = {
10108 .name = TYPE_POWERPC_CPU,
10109 .parent = TYPE_CPU,
10110 .instance_size = sizeof(PowerPCCPU),
10111 .instance_init = ppc_cpu_initfn,
10112 .abstract = true,
10113 .class_size = sizeof(PowerPCCPUClass),
10114 .class_init = ppc_cpu_class_init,
10115 };
10116
10117 static void ppc_cpu_register_types(void)
10118 {
10119 type_register_static(&ppc_cpu_type_info);
10120 }
10121
10122 type_init(ppc_cpu_register_types)
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