hw/ppc/spapr_iommu.c

   1 /*
   2  * QEMU sPAPR IOMMU (TCE) code
   3  *
   4  * Copyright (c) 2010 David Gibson, IBM Corporation <dwg@au1.ibm.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/error-report.h"
  22 #include "qemu/log.h"
  23 #include "qemu/module.h"
  24 #include "sysemu/kvm.h"
  25 #include "kvm_ppc.h"
  26 #include "migration/vmstate.h"
  27 #include "sysemu/dma.h"
  28 #include "trace.h"
  29
  30 #include "hw/ppc/spapr.h"
  31 #include "hw/ppc/spapr_vio.h"
  32
  33 #include <libfdt.h>
  34
  35 enum SpaprTceAccess {
  36     SPAPR_TCE_FAULT = 0,
  37     SPAPR_TCE_RO = 1,
  38     SPAPR_TCE_WO = 2,
  39     SPAPR_TCE_RW = 3,
  40 };
  41
  42 #define IOMMU_PAGE_SIZE(shift)      (1ULL << (shift))
  43 #define IOMMU_PAGE_MASK(shift)      (~(IOMMU_PAGE_SIZE(shift) - 1))
  44
  45 static QLIST_HEAD(, SpaprTceTable) spapr_tce_tables;
  46
  47 SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn)
  48 {
  49     SpaprTceTable *tcet;
  50
  51     if (liobn & 0xFFFFFFFF00000000ULL) {
  52         hcall_dprintf("Request for out-of-bounds LIOBN 0x" TARGET_FMT_lx "\n",
  53                       liobn);
  54         return NULL;
  55     }
  56
  57     QLIST_FOREACH(tcet, &spapr_tce_tables, list) {
  58         if (tcet->liobn == (uint32_t)liobn) {
  59             return tcet;
  60         }
  61     }
  62
  63     return NULL;
  64 }
  65
  66 static IOMMUAccessFlags spapr_tce_iommu_access_flags(uint64_t tce)
  67 {
  68     switch (tce & SPAPR_TCE_RW) {
  69     case SPAPR_TCE_FAULT:
  70         return IOMMU_NONE;
  71     case SPAPR_TCE_RO:
  72         return IOMMU_RO;
  73     case SPAPR_TCE_WO:
  74         return IOMMU_WO;
  75     default: /* SPAPR_TCE_RW */
  76         return IOMMU_RW;
  77     }
  78 }
  79
  80 static uint64_t *spapr_tce_alloc_table(uint32_t liobn,
  81                                        uint32_t page_shift,
  82                                        uint64_t bus_offset,
  83                                        uint32_t nb_table,
  84                                        int *fd,
  85                                        bool need_vfio)
  86 {
  87     uint64_t *table = NULL;
  88
  89     if (kvm_enabled()) {
  90         table = kvmppc_create_spapr_tce(liobn, page_shift, bus_offset, nb_table,
  91                                         fd, need_vfio);
  92     }
  93
  94     if (!table) {
  95         *fd = -1;
  96         table = g_new0(uint64_t, nb_table);
  97     }
  98
  99     trace_spapr_iommu_new_table(liobn, table, *fd);
 100
 101     return table;
 102 }
 103
 104 static void spapr_tce_free_table(uint64_t *table, int fd, uint32_t nb_table)
 105 {
 106     if (!kvm_enabled() ||
 107         (kvmppc_remove_spapr_tce(table, fd, nb_table) != 0)) {
 108         g_free(table);
 109     }
 110 }
 111
 112 /* Called from RCU critical section */
 113 static IOMMUTLBEntry spapr_tce_translate_iommu(IOMMUMemoryRegion *iommu,
 114                                                hwaddr addr,
 115                                                IOMMUAccessFlags flag,
 116                                                int iommu_idx)
 117 {
 118     SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu);
 119     uint64_t tce;
 120     IOMMUTLBEntry ret = {
 121         .target_as = &address_space_memory,
 122         .iova = 0,
 123         .translated_addr = 0,
 124         .addr_mask = ~(hwaddr)0,
 125         .perm = IOMMU_NONE,
 126     };
 127
 128     if ((addr >> tcet->page_shift) < tcet->nb_table) {
 129         /* Check if we are in bound */
 130         hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
 131
 132         tce = tcet->table[addr >> tcet->page_shift];
 133         ret.iova = addr & page_mask;
 134         ret.translated_addr = tce & page_mask;
 135         ret.addr_mask = ~page_mask;
 136         ret.perm = spapr_tce_iommu_access_flags(tce);
 137     }
 138     trace_spapr_iommu_xlate(tcet->liobn, addr, ret.translated_addr, ret.perm,
 139                             ret.addr_mask);
 140
 141     return ret;
 142 }
 143
 144 static void spapr_tce_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
 145 {
 146     MemoryRegion *mr = MEMORY_REGION(iommu_mr);
 147     IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
 148     hwaddr addr, granularity;
 149     IOMMUTLBEntry iotlb;
 150     SpaprTceTable *tcet = container_of(iommu_mr, SpaprTceTable, iommu);
 151
 152     if (tcet->skipping_replay) {
 153         return;
 154     }
 155
 156     granularity = memory_region_iommu_get_min_page_size(iommu_mr);
 157
 158     for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
 159         iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
 160         if (iotlb.perm != IOMMU_NONE) {
 161             n->notify(n, &iotlb);
 162         }
 163
 164         /*
 165          * if (2^64 - MR size) < granularity, it's possible to get an
 166          * infinite loop here.  This should catch such a wraparound.
 167          */
 168         if ((addr + granularity) < addr) {
 169             break;
 170         }
 171     }
 172 }
 173
 174 static int spapr_tce_table_pre_save(void *opaque)
 175 {
 176     SpaprTceTable *tcet = SPAPR_TCE_TABLE(opaque);
 177
 178     tcet->mig_table = tcet->table;
 179     tcet->mig_nb_table = tcet->nb_table;
 180
 181     trace_spapr_iommu_pre_save(tcet->liobn, tcet->mig_nb_table,
 182                                tcet->bus_offset, tcet->page_shift);
 183
 184     return 0;
 185 }
 186
 187 static uint64_t spapr_tce_get_min_page_size(IOMMUMemoryRegion *iommu)
 188 {
 189     SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu);
 190
 191     return 1ULL << tcet->page_shift;
 192 }
 193
 194 static int spapr_tce_get_attr(IOMMUMemoryRegion *iommu,
 195                               enum IOMMUMemoryRegionAttr attr, void *data)
 196 {
 197     SpaprTceTable *tcet = container_of(iommu, SpaprTceTable, iommu);
 198
 199     if (attr == IOMMU_ATTR_SPAPR_TCE_FD && kvmppc_has_cap_spapr_vfio()) {
 200         *(int *) data = tcet->fd;
 201         return 0;
 202     }
 203
 204     return -EINVAL;
 205 }
 206
 207 static int spapr_tce_notify_flag_changed(IOMMUMemoryRegion *iommu,
 208                                          IOMMUNotifierFlag old,
 209                                          IOMMUNotifierFlag new,
 210                                          Error **errp)
 211 {
 212     struct SpaprTceTable *tbl = container_of(iommu, SpaprTceTable, iommu);
 213
 214     if (new & IOMMU_NOTIFIER_DEVIOTLB_UNMAP) {
 215         error_setg(errp, "spart_tce does not support dev-iotlb yet");
 216         return -EINVAL;
 217     }
 218
 219     if (old == IOMMU_NOTIFIER_NONE && new != IOMMU_NOTIFIER_NONE) {
 220         spapr_tce_set_need_vfio(tbl, true);
 221     } else if (old != IOMMU_NOTIFIER_NONE && new == IOMMU_NOTIFIER_NONE) {
 222         spapr_tce_set_need_vfio(tbl, false);
 223     }
 224     return 0;
 225 }
 226
 227 static int spapr_tce_table_post_load(void *opaque, int version_id)
 228 {
 229     SpaprTceTable *tcet = SPAPR_TCE_TABLE(opaque);
 230     uint32_t old_nb_table = tcet->nb_table;
 231     uint64_t old_bus_offset = tcet->bus_offset;
 232     uint32_t old_page_shift = tcet->page_shift;
 233
 234     if (tcet->vdev) {
 235         spapr_vio_set_bypass(tcet->vdev, tcet->bypass);
 236     }
 237
 238     if (tcet->mig_nb_table != tcet->nb_table) {
 239         spapr_tce_table_disable(tcet);
 240     }
 241
 242     if (tcet->mig_nb_table) {
 243         if (!tcet->nb_table) {
 244             spapr_tce_table_enable(tcet, old_page_shift, old_bus_offset,
 245                                    tcet->mig_nb_table);
 246         }
 247
 248         memcpy(tcet->table, tcet->mig_table,
 249                tcet->nb_table * sizeof(tcet->table[0]));
 250
 251         free(tcet->mig_table);
 252         tcet->mig_table = NULL;
 253     }
 254
 255     trace_spapr_iommu_post_load(tcet->liobn, old_nb_table, tcet->nb_table,
 256                                 tcet->bus_offset, tcet->page_shift);
 257
 258     return 0;
 259 }
 260
 261 static bool spapr_tce_table_ex_needed(void *opaque)
 262 {
 263     SpaprTceTable *tcet = opaque;
 264
 265     return tcet->bus_offset || tcet->page_shift != 0xC;
 266 }
 267
 268 static const VMStateDescription vmstate_spapr_tce_table_ex = {
 269     .name = "spapr_iommu_ex",
 270     .version_id = 1,
 271     .minimum_version_id = 1,
 272     .needed = spapr_tce_table_ex_needed,
 273     .fields = (VMStateField[]) {
 274         VMSTATE_UINT64(bus_offset, SpaprTceTable),
 275         VMSTATE_UINT32(page_shift, SpaprTceTable),
 276         VMSTATE_END_OF_LIST()
 277     },
 278 };
 279
 280 static const VMStateDescription vmstate_spapr_tce_table = {
 281     .name = "spapr_iommu",
 282     .version_id = 2,
 283     .minimum_version_id = 2,
 284     .pre_save = spapr_tce_table_pre_save,
 285     .post_load = spapr_tce_table_post_load,
 286     .fields      = (VMStateField []) {
 287         /* Sanity check */
 288         VMSTATE_UINT32_EQUAL(liobn, SpaprTceTable, NULL),
 289
 290         /* IOMMU state */
 291         VMSTATE_UINT32(mig_nb_table, SpaprTceTable),
 292         VMSTATE_BOOL(bypass, SpaprTceTable),
 293         VMSTATE_VARRAY_UINT32_ALLOC(mig_table, SpaprTceTable, mig_nb_table, 0,
 294                                     vmstate_info_uint64, uint64_t),
 295
 296         VMSTATE_END_OF_LIST()
 297     },
 298     .subsections = (const VMStateDescription*[]) {
 299         &vmstate_spapr_tce_table_ex,
 300         NULL
 301     }
 302 };
 303
 304 static void spapr_tce_table_realize(DeviceState *dev, Error **errp)
 305 {
 306     SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev);
 307     Object *tcetobj = OBJECT(tcet);
 308     gchar *tmp;
 309
 310     tcet->fd = -1;
 311     tcet->need_vfio = false;
 312     tmp = g_strdup_printf("tce-root-%x", tcet->liobn);
 313     memory_region_init(&tcet->root, tcetobj, tmp, UINT64_MAX);
 314     g_free(tmp);
 315
 316     tmp = g_strdup_printf("tce-iommu-%x", tcet->liobn);
 317     memory_region_init_iommu(&tcet->iommu, sizeof(tcet->iommu),
 318                              TYPE_SPAPR_IOMMU_MEMORY_REGION,
 319                              tcetobj, tmp, 0);
 320     g_free(tmp);
 321
 322     QLIST_INSERT_HEAD(&spapr_tce_tables, tcet, list);
 323
 324     vmstate_register(VMSTATE_IF(tcet), tcet->liobn, &vmstate_spapr_tce_table,
 325                      tcet);
 326 }
 327
 328 void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio)
 329 {
 330     size_t table_size = tcet->nb_table * sizeof(uint64_t);
 331     uint64_t *oldtable;
 332     int newfd = -1;
 333
 334     g_assert(need_vfio != tcet->need_vfio);
 335
 336     tcet->need_vfio = need_vfio;
 337
 338     if (!need_vfio || (tcet->fd != -1 && kvmppc_has_cap_spapr_vfio())) {
 339         return;
 340     }
 341
 342     oldtable = tcet->table;
 343
 344     tcet->table = spapr_tce_alloc_table(tcet->liobn,
 345                                         tcet->page_shift,
 346                                         tcet->bus_offset,
 347                                         tcet->nb_table,
 348                                         &newfd,
 349                                         need_vfio);
 350     memcpy(tcet->table, oldtable, table_size);
 351
 352     spapr_tce_free_table(oldtable, tcet->fd, tcet->nb_table);
 353
 354     tcet->fd = newfd;
 355 }
 356
 357 SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn)
 358 {
 359     SpaprTceTable *tcet;
 360     gchar *tmp;
 361
 362     if (spapr_tce_find_by_liobn(liobn)) {
 363         error_report("Attempted to create TCE table with duplicate"
 364                 " LIOBN 0x%x", liobn);
 365         return NULL;
 366     }
 367
 368     tcet = SPAPR_TCE_TABLE(object_new(TYPE_SPAPR_TCE_TABLE));
 369     tcet->liobn = liobn;
 370
 371     tmp = g_strdup_printf("tce-table-%x", liobn);
 372     object_property_add_child(OBJECT(owner), tmp, OBJECT(tcet));
 373     g_free(tmp);
 374     object_unref(OBJECT(tcet));
 375
 376     qdev_realize(DEVICE(tcet), NULL, NULL);
 377
 378     return tcet;
 379 }
 380
 381 void spapr_tce_table_enable(SpaprTceTable *tcet,
 382                             uint32_t page_shift, uint64_t bus_offset,
 383                             uint32_t nb_table)
 384 {
 385     if (tcet->nb_table) {
 386         warn_report("trying to enable already enabled TCE table");
 387         return;
 388     }
 389
 390     tcet->bus_offset = bus_offset;
 391     tcet->page_shift = page_shift;
 392     tcet->nb_table = nb_table;
 393     tcet->table = spapr_tce_alloc_table(tcet->liobn,
 394                                         tcet->page_shift,
 395                                         tcet->bus_offset,
 396                                         tcet->nb_table,
 397                                         &tcet->fd,
 398                                         tcet->need_vfio);
 399
 400     memory_region_set_size(MEMORY_REGION(&tcet->iommu),
 401                            (uint64_t)tcet->nb_table << tcet->page_shift);
 402     memory_region_add_subregion(&tcet->root, tcet->bus_offset,
 403                                 MEMORY_REGION(&tcet->iommu));
 404 }
 405
 406 void spapr_tce_table_disable(SpaprTceTable *tcet)
 407 {
 408     if (!tcet->nb_table) {
 409         return;
 410     }
 411
 412     memory_region_del_subregion(&tcet->root, MEMORY_REGION(&tcet->iommu));
 413     memory_region_set_size(MEMORY_REGION(&tcet->iommu), 0);
 414
 415     spapr_tce_free_table(tcet->table, tcet->fd, tcet->nb_table);
 416     tcet->fd = -1;
 417     tcet->table = NULL;
 418     tcet->bus_offset = 0;
 419     tcet->page_shift = 0;
 420     tcet->nb_table = 0;
 421 }
 422
 423 static void spapr_tce_table_unrealize(DeviceState *dev)
 424 {
 425     SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev);
 426
 427     vmstate_unregister(VMSTATE_IF(tcet), &vmstate_spapr_tce_table, tcet);
 428
 429     QLIST_REMOVE(tcet, list);
 430
 431     spapr_tce_table_disable(tcet);
 432 }
 433
 434 MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet)
 435 {
 436     return &tcet->root;
 437 }
 438
 439 static void spapr_tce_reset(DeviceState *dev)
 440 {
 441     SpaprTceTable *tcet = SPAPR_TCE_TABLE(dev);
 442     size_t table_size = tcet->nb_table * sizeof(uint64_t);
 443
 444     if (tcet->nb_table) {
 445         memset(tcet->table, 0, table_size);
 446     }
 447 }
 448
 449 static target_ulong put_tce_emu(SpaprTceTable *tcet, target_ulong ioba,
 450                                 target_ulong tce)
 451 {
 452     IOMMUTLBEvent event;
 453     hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
 454     unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
 455
 456     if (index >= tcet->nb_table) {
 457         hcall_dprintf("spapr_vio_put_tce on out-of-bounds IOBA 0x"
 458                       TARGET_FMT_lx "\n", ioba);
 459         return H_PARAMETER;
 460     }
 461
 462     tcet->table[index] = tce;
 463
 464     event.entry.target_as = &address_space_memory,
 465     event.entry.iova = (ioba - tcet->bus_offset) & page_mask;
 466     event.entry.translated_addr = tce & page_mask;
 467     event.entry.addr_mask = ~page_mask;
 468     event.entry.perm = spapr_tce_iommu_access_flags(tce);
 469     event.type = event.entry.perm ? IOMMU_NOTIFIER_MAP : IOMMU_NOTIFIER_UNMAP;
 470     memory_region_notify_iommu(&tcet->iommu, 0, event);
 471
 472     return H_SUCCESS;
 473 }
 474
 475 static target_ulong h_put_tce_indirect(PowerPCCPU *cpu,
 476                                        SpaprMachineState *spapr,
 477                                        target_ulong opcode, target_ulong *args)
 478 {
 479     int i;
 480     target_ulong liobn = args[0];
 481     target_ulong ioba = args[1];
 482     target_ulong ioba1 = ioba;
 483     target_ulong tce_list = args[2];
 484     target_ulong npages = args[3];
 485     target_ulong ret = H_PARAMETER, tce = 0;
 486     SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn);
 487     CPUState *cs = CPU(cpu);
 488     hwaddr page_mask, page_size;
 489
 490     if (!tcet) {
 491         return H_PARAMETER;
 492     }
 493
 494     if ((npages > 512) || (tce_list & SPAPR_TCE_PAGE_MASK)) {
 495         return H_PARAMETER;
 496     }
 497
 498     page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
 499     page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
 500     ioba &= page_mask;
 501
 502     for (i = 0; i < npages; ++i, ioba += page_size) {
 503         tce = ldq_be_phys(cs->as, tce_list + i * sizeof(target_ulong));
 504
 505         ret = put_tce_emu(tcet, ioba, tce);
 506         if (ret) {
 507             break;
 508         }
 509     }
 510
 511     /* Trace last successful or the first problematic entry */
 512     i = i ? (i - 1) : 0;
 513     if (SPAPR_IS_PCI_LIOBN(liobn)) {
 514         trace_spapr_iommu_pci_indirect(liobn, ioba1, tce_list, i, tce, ret);
 515     } else {
 516         trace_spapr_iommu_indirect(liobn, ioba1, tce_list, i, tce, ret);
 517     }
 518     return ret;
 519 }
 520
 521 static target_ulong h_stuff_tce(PowerPCCPU *cpu, SpaprMachineState *spapr,
 522                               target_ulong opcode, target_ulong *args)
 523 {
 524     int i;
 525     target_ulong liobn = args[0];
 526     target_ulong ioba = args[1];
 527     target_ulong tce_value = args[2];
 528     target_ulong npages = args[3];
 529     target_ulong ret = H_PARAMETER;
 530     SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn);
 531     hwaddr page_mask, page_size;
 532
 533     if (!tcet) {
 534         return H_PARAMETER;
 535     }
 536
 537     if (npages > tcet->nb_table) {
 538         return H_PARAMETER;
 539     }
 540
 541     page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
 542     page_size = IOMMU_PAGE_SIZE(tcet->page_shift);
 543     ioba &= page_mask;
 544
 545     for (i = 0; i < npages; ++i, ioba += page_size) {
 546         ret = put_tce_emu(tcet, ioba, tce_value);
 547         if (ret) {
 548             break;
 549         }
 550     }
 551     if (SPAPR_IS_PCI_LIOBN(liobn)) {
 552         trace_spapr_iommu_pci_stuff(liobn, ioba, tce_value, npages, ret);
 553     } else {
 554         trace_spapr_iommu_stuff(liobn, ioba, tce_value, npages, ret);
 555     }
 556
 557     return ret;
 558 }
 559
 560 static target_ulong h_put_tce(PowerPCCPU *cpu, SpaprMachineState *spapr,
 561                               target_ulong opcode, target_ulong *args)
 562 {
 563     target_ulong liobn = args[0];
 564     target_ulong ioba = args[1];
 565     target_ulong tce = args[2];
 566     target_ulong ret = H_PARAMETER;
 567     SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn);
 568
 569     if (tcet) {
 570         hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
 571
 572         ioba &= page_mask;
 573
 574         ret = put_tce_emu(tcet, ioba, tce);
 575     }
 576     if (SPAPR_IS_PCI_LIOBN(liobn)) {
 577         trace_spapr_iommu_pci_put(liobn, ioba, tce, ret);
 578     } else {
 579         trace_spapr_iommu_put(liobn, ioba, tce, ret);
 580     }
 581
 582     return ret;
 583 }
 584
 585 static target_ulong get_tce_emu(SpaprTceTable *tcet, target_ulong ioba,
 586                                 target_ulong *tce)
 587 {
 588     unsigned long index = (ioba - tcet->bus_offset) >> tcet->page_shift;
 589
 590     if (index >= tcet->nb_table) {
 591         hcall_dprintf("spapr_iommu_get_tce on out-of-bounds IOBA 0x"
 592                       TARGET_FMT_lx "\n", ioba);
 593         return H_PARAMETER;
 594     }
 595
 596     *tce = tcet->table[index];
 597
 598     return H_SUCCESS;
 599 }
 600
 601 static target_ulong h_get_tce(PowerPCCPU *cpu, SpaprMachineState *spapr,
 602                               target_ulong opcode, target_ulong *args)
 603 {
 604     target_ulong liobn = args[0];
 605     target_ulong ioba = args[1];
 606     target_ulong tce = 0;
 607     target_ulong ret = H_PARAMETER;
 608     SpaprTceTable *tcet = spapr_tce_find_by_liobn(liobn);
 609
 610     if (tcet) {
 611         hwaddr page_mask = IOMMU_PAGE_MASK(tcet->page_shift);
 612
 613         ioba &= page_mask;
 614
 615         ret = get_tce_emu(tcet, ioba, &tce);
 616         if (!ret) {
 617             args[0] = tce;
 618         }
 619     }
 620     if (SPAPR_IS_PCI_LIOBN(liobn)) {
 621         trace_spapr_iommu_pci_get(liobn, ioba, ret, tce);
 622     } else {
 623         trace_spapr_iommu_get(liobn, ioba, ret, tce);
 624     }
 625
 626     return ret;
 627 }
 628
 629 int spapr_dma_dt(void *fdt, int node_off, const char *propname,
 630                  uint32_t liobn, uint64_t window, uint32_t size)
 631 {
 632     uint32_t dma_prop[5];
 633     int ret;
 634
 635     dma_prop[0] = cpu_to_be32(liobn);
 636     dma_prop[1] = cpu_to_be32(window >> 32);
 637     dma_prop[2] = cpu_to_be32(window & 0xFFFFFFFF);
 638     dma_prop[3] = 0; /* window size is 32 bits */
 639     dma_prop[4] = cpu_to_be32(size);
 640
 641     ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-address-cells", 2);
 642     if (ret < 0) {
 643         return ret;
 644     }
 645
 646     ret = fdt_setprop_cell(fdt, node_off, "ibm,#dma-size-cells", 2);
 647     if (ret < 0) {
 648         return ret;
 649     }
 650
 651     ret = fdt_setprop(fdt, node_off, propname, dma_prop, sizeof(dma_prop));
 652     if (ret < 0) {
 653         return ret;
 654     }
 655
 656     return 0;
 657 }
 658
 659 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
 660                       SpaprTceTable *tcet)
 661 {
 662     if (!tcet) {
 663         return 0;
 664     }
 665
 666     return spapr_dma_dt(fdt, node_off, propname,
 667                         tcet->liobn, 0, tcet->nb_table << tcet->page_shift);
 668 }
 669
 670 static void spapr_tce_table_class_init(ObjectClass *klass, void *data)
 671 {
 672     DeviceClass *dc = DEVICE_CLASS(klass);
 673     dc->realize = spapr_tce_table_realize;
 674     dc->reset = spapr_tce_reset;
 675     dc->unrealize = spapr_tce_table_unrealize;
 676     /* Reason: This is just an internal device for handling the hypercalls */
 677     dc->user_creatable = false;
 678
 679     QLIST_INIT(&spapr_tce_tables);
 680
 681     /* hcall-tce */
 682     spapr_register_hypercall(H_PUT_TCE, h_put_tce);
 683     spapr_register_hypercall(H_GET_TCE, h_get_tce);
 684     spapr_register_hypercall(H_PUT_TCE_INDIRECT, h_put_tce_indirect);
 685     spapr_register_hypercall(H_STUFF_TCE, h_stuff_tce);
 686 }
 687
 688 static TypeInfo spapr_tce_table_info = {
 689     .name = TYPE_SPAPR_TCE_TABLE,
 690     .parent = TYPE_DEVICE,
 691     .instance_size = sizeof(SpaprTceTable),
 692     .class_init = spapr_tce_table_class_init,
 693 };
 694
 695 static void spapr_iommu_memory_region_class_init(ObjectClass *klass, void *data)
 696 {
 697     IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
 698
 699     imrc->translate = spapr_tce_translate_iommu;
 700     imrc->replay = spapr_tce_replay;
 701     imrc->get_min_page_size = spapr_tce_get_min_page_size;
 702     imrc->notify_flag_changed = spapr_tce_notify_flag_changed;
 703     imrc->get_attr = spapr_tce_get_attr;
 704 }
 705
 706 static const TypeInfo spapr_iommu_memory_region_info = {
 707     .parent = TYPE_IOMMU_MEMORY_REGION,
 708     .name = TYPE_SPAPR_IOMMU_MEMORY_REGION,
 709     .class_init = spapr_iommu_memory_region_class_init,
 710 };
 711
 712 static void register_types(void)
 713 {
 714     type_register_static(&spapr_tce_table_info);
 715     type_register_static(&spapr_iommu_memory_region_info);
 716 }
 717
 718 type_init(register_types);