4 /* CPU interfaces that are target independent. */
6 #ifndef CONFIG_USER_ONLY
7 #include "exec/hwaddr.h"
10 #define EXCP_INTERRUPT 0x10000 /* async interruption */
11 #define EXCP_HLT 0x10001 /* hlt instruction reached */
12 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
13 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
14 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
15 #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */
19 * Type wide enough to contain any #target_ulong virtual address.
21 typedef uint64_t vaddr
;
22 #define VADDR_PRId PRId64
23 #define VADDR_PRIu PRIu64
24 #define VADDR_PRIo PRIo64
25 #define VADDR_PRIx PRIx64
26 #define VADDR_PRIX PRIX64
27 #define VADDR_MAX UINT64_MAX
29 void cpu_exec_init_all(void);
30 void cpu_exec_step_atomic(CPUState
*cpu
);
32 /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even
33 * when intptr_t is 32-bit and we are aligning a long long.
35 extern uintptr_t qemu_host_page_size
;
36 extern intptr_t qemu_host_page_mask
;
38 #define HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_host_page_size)
39 #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size())
41 /* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */
42 extern QemuMutex qemu_cpu_list_lock
;
43 void qemu_init_cpu_list(void);
44 void cpu_list_lock(void);
45 void cpu_list_unlock(void);
46 unsigned int cpu_list_generation_id_get(void);
48 void tcg_iommu_init_notifier_list(CPUState
*cpu
);
49 void tcg_iommu_free_notifier_list(CPUState
*cpu
);
51 #if !defined(CONFIG_USER_ONLY)
60 #define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN
62 #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN
65 /* address in the RAM (different from a physical address) */
66 #if defined(CONFIG_XEN_BACKEND)
67 typedef uint64_t ram_addr_t
;
68 # define RAM_ADDR_MAX UINT64_MAX
69 # define RAM_ADDR_FMT "%" PRIx64
71 typedef uintptr_t ram_addr_t
;
72 # define RAM_ADDR_MAX UINTPTR_MAX
73 # define RAM_ADDR_FMT "%" PRIxPTR
78 void qemu_ram_remap(ram_addr_t addr
, ram_addr_t length
);
79 /* This should not be used by devices. */
80 ram_addr_t
qemu_ram_addr_from_host(void *ptr
);
81 ram_addr_t
qemu_ram_addr_from_host_nofail(void *ptr
);
82 RAMBlock
*qemu_ram_block_by_name(const char *name
);
85 * Translates a host ptr back to a RAMBlock and an offset in that RAMBlock.
87 * @ptr: The host pointer to translate.
88 * @round_offset: Whether to round the result offset down to a target page
89 * @offset: Will be set to the offset within the returned RAMBlock.
91 * Returns: RAMBlock (or NULL if not found)
93 * By the time this function returns, the returned pointer is not protected
94 * by RCU anymore. If the caller is not within an RCU critical section and
95 * does not hold the BQL, it must have other means of protecting the
96 * pointer, such as a reference to the memory region that owns the RAMBlock.
98 RAMBlock
*qemu_ram_block_from_host(void *ptr
, bool round_offset
,
100 ram_addr_t
qemu_ram_block_host_offset(RAMBlock
*rb
, void *host
);
101 void qemu_ram_set_idstr(RAMBlock
*block
, const char *name
, DeviceState
*dev
);
102 void qemu_ram_unset_idstr(RAMBlock
*block
);
103 const char *qemu_ram_get_idstr(RAMBlock
*rb
);
104 void *qemu_ram_get_host_addr(RAMBlock
*rb
);
105 ram_addr_t
qemu_ram_get_offset(RAMBlock
*rb
);
106 ram_addr_t
qemu_ram_get_used_length(RAMBlock
*rb
);
107 ram_addr_t
qemu_ram_get_max_length(RAMBlock
*rb
);
108 bool qemu_ram_is_shared(RAMBlock
*rb
);
109 bool qemu_ram_is_noreserve(RAMBlock
*rb
);
110 bool qemu_ram_is_uf_zeroable(RAMBlock
*rb
);
111 void qemu_ram_set_uf_zeroable(RAMBlock
*rb
);
112 bool qemu_ram_is_migratable(RAMBlock
*rb
);
113 void qemu_ram_set_migratable(RAMBlock
*rb
);
114 void qemu_ram_unset_migratable(RAMBlock
*rb
);
115 bool qemu_ram_is_named_file(RAMBlock
*rb
);
116 int qemu_ram_get_fd(RAMBlock
*rb
);
118 size_t qemu_ram_pagesize(RAMBlock
*block
);
119 size_t qemu_ram_pagesize_largest(void);
122 * cpu_address_space_init:
123 * @cpu: CPU to add this address space to
124 * @asidx: integer index of this address space
125 * @prefix: prefix to be used as name of address space
126 * @mr: the root memory region of address space
128 * Add the specified address space to the CPU's cpu_ases list.
129 * The address space added with @asidx 0 is the one used for the
130 * convenience pointer cpu->as.
131 * The target-specific code which registers ASes is responsible
132 * for defining what semantics address space 0, 1, 2, etc have.
134 * Before the first call to this function, the caller must set
135 * cpu->num_ases to the total number of address spaces it needs
138 * Note that with KVM only one address space is supported.
140 void cpu_address_space_init(CPUState
*cpu
, int asidx
,
141 const char *prefix
, MemoryRegion
*mr
);
143 void cpu_physical_memory_rw(hwaddr addr
, void *buf
,
144 hwaddr len
, bool is_write
);
145 static inline void cpu_physical_memory_read(hwaddr addr
,
146 void *buf
, hwaddr len
)
148 cpu_physical_memory_rw(addr
, buf
, len
, false);
150 static inline void cpu_physical_memory_write(hwaddr addr
,
151 const void *buf
, hwaddr len
)
153 cpu_physical_memory_rw(addr
, (void *)buf
, len
, true);
155 void *cpu_physical_memory_map(hwaddr addr
,
158 void cpu_physical_memory_unmap(void *buffer
, hwaddr len
,
159 bool is_write
, hwaddr access_len
);
160 void cpu_register_map_client(QEMUBH
*bh
);
161 void cpu_unregister_map_client(QEMUBH
*bh
);
163 bool cpu_physical_memory_is_io(hwaddr phys_addr
);
165 /* Coalesced MMIO regions are areas where write operations can be reordered.
166 * This usually implies that write operations are side-effect free. This allows
167 * batching which can make a major impact on performance when using
170 void qemu_flush_coalesced_mmio_buffer(void);
172 void cpu_flush_icache_range(hwaddr start
, hwaddr len
);
174 typedef int (RAMBlockIterFunc
)(RAMBlock
*rb
, void *opaque
);
176 int qemu_ram_foreach_block(RAMBlockIterFunc func
, void *opaque
);
177 int ram_block_discard_range(RAMBlock
*rb
, uint64_t start
, size_t length
);
181 /* Returns: 0 on success, -1 on error */
182 int cpu_memory_rw_debug(CPUState
*cpu
, vaddr addr
,
183 void *ptr
, size_t len
, bool is_write
);
186 void list_cpus(void);
190 * cpu_unwind_state_data:
191 * @cpu: the cpu context
192 * @host_pc: the host pc within the translation
195 * Attempt to load the the unwind state for a host pc occurring in
196 * translated code. If @host_pc is not in translated code, the
197 * function returns false; otherwise @data is loaded.
198 * This is the same unwind info as given to restore_state_to_opc.
200 bool cpu_unwind_state_data(CPUState
*cpu
, uintptr_t host_pc
, uint64_t *data
);
204 * @cpu: the cpu context
205 * @host_pc: the host pc within the translation
206 * @return: true if state was restored, false otherwise
208 * Attempt to restore the state for a fault occurring in translated
209 * code. If @host_pc is not in translated code no state is
210 * restored and the function returns false.
212 bool cpu_restore_state(CPUState
*cpu
, uintptr_t host_pc
);
214 G_NORETURN
void cpu_loop_exit_noexc(CPUState
*cpu
);
215 G_NORETURN
void cpu_loop_exit_atomic(CPUState
*cpu
, uintptr_t pc
);
216 #endif /* CONFIG_TCG */
217 G_NORETURN
void cpu_loop_exit(CPUState
*cpu
);
218 G_NORETURN
void cpu_loop_exit_restore(CPUState
*cpu
, uintptr_t pc
);
220 #endif /* CPU_COMMON_H */