tests/libqos/virtio-pci.c

   1 /*
   2  * libqos virtio PCI driver
   3  *
   4  * Copyright (c) 2014 Marc Marí
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "libqtest.h"
  12 #include "libqos/virtio.h"
  13 #include "libqos/virtio-pci.h"
  14 #include "libqos/pci.h"
  15 #include "libqos/pci-pc.h"
  16 #include "libqos/malloc.h"
  17 #include "libqos/malloc-pc.h"
  18 #include "standard-headers/linux/virtio_ring.h"
  19
  20 #include "hw/pci/pci.h"
  21 #include "hw/pci/pci_regs.h"
  22
  23 typedef struct QVirtioPCIForeachData {
  24     void (*func)(QVirtioDevice *d, void *data);
  25     uint16_t device_type;
  26     void *user_data;
  27 } QVirtioPCIForeachData;
  28
  29 static QVirtioPCIDevice *qpcidevice_to_qvirtiodevice(QPCIDevice *pdev)
  30 {
  31     QVirtioPCIDevice *vpcidev;
  32     vpcidev = g_malloc0(sizeof(*vpcidev));
  33
  34     if (pdev) {
  35         vpcidev->pdev = pdev;
  36         vpcidev->vdev.device_type =
  37                             qpci_config_readw(vpcidev->pdev, PCI_SUBSYSTEM_ID);
  38     }
  39
  40     vpcidev->config_msix_entry = -1;
  41
  42     return vpcidev;
  43 }
  44
  45 static void qvirtio_pci_foreach_callback(
  46                         QPCIDevice *dev, int devfn, void *data)
  47 {
  48     QVirtioPCIForeachData *d = data;
  49     QVirtioPCIDevice *vpcidev = qpcidevice_to_qvirtiodevice(dev);
  50
  51     if (vpcidev->vdev.device_type == d->device_type) {
  52         d->func(&vpcidev->vdev, d->user_data);
  53     } else {
  54         g_free(vpcidev);
  55     }
  56 }
  57
  58 static void qvirtio_pci_assign_device(QVirtioDevice *d, void *data)
  59 {
  60     QVirtioPCIDevice **vpcidev = data;
  61     *vpcidev = (QVirtioPCIDevice *)d;
  62 }
  63
  64 static uint8_t qvirtio_pci_config_readb(QVirtioDevice *d, uint64_t addr)
  65 {
  66     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
  67     return qpci_io_readb(dev->pdev, (void *)(uintptr_t)addr);
  68 }
  69
  70 static uint16_t qvirtio_pci_config_readw(QVirtioDevice *d, uint64_t addr)
  71 {
  72     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
  73     return qpci_io_readw(dev->pdev, (void *)(uintptr_t)addr);
  74 }
  75
  76 static uint32_t qvirtio_pci_config_readl(QVirtioDevice *d, uint64_t addr)
  77 {
  78     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
  79     return qpci_io_readl(dev->pdev, (void *)(uintptr_t)addr);
  80 }
  81
  82 static uint64_t qvirtio_pci_config_readq(QVirtioDevice *d, uint64_t addr)
  83 {
  84     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
  85     int i;
  86     uint64_t u64 = 0;
  87
  88     if (qtest_big_endian()) {
  89         for (i = 0; i < 8; ++i) {
  90             u64 |= (uint64_t)qpci_io_readb(dev->pdev,
  91                                 (void *)(uintptr_t)addr + i) << (7 - i) * 8;
  92         }
  93     } else {
  94         for (i = 0; i < 8; ++i) {
  95             u64 |= (uint64_t)qpci_io_readb(dev->pdev,
  96                                 (void *)(uintptr_t)addr + i) << i * 8;
  97         }
  98     }
  99
 100     return u64;
 101 }
 102
 103 static uint32_t qvirtio_pci_get_features(QVirtioDevice *d)
 104 {
 105     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 106     return qpci_io_readl(dev->pdev, dev->addr + QVIRTIO_PCI_DEVICE_FEATURES);
 107 }
 108
 109 static void qvirtio_pci_set_features(QVirtioDevice *d, uint32_t features)
 110 {
 111     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 112     qpci_io_writel(dev->pdev, dev->addr + QVIRTIO_PCI_GUEST_FEATURES, features);
 113 }
 114
 115 static uint32_t qvirtio_pci_get_guest_features(QVirtioDevice *d)
 116 {
 117     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 118     return qpci_io_readl(dev->pdev, dev->addr + QVIRTIO_PCI_GUEST_FEATURES);
 119 }
 120
 121 static uint8_t qvirtio_pci_get_status(QVirtioDevice *d)
 122 {
 123     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 124     return qpci_io_readb(dev->pdev, dev->addr + QVIRTIO_PCI_DEVICE_STATUS);
 125 }
 126
 127 static void qvirtio_pci_set_status(QVirtioDevice *d, uint8_t status)
 128 {
 129     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 130     qpci_io_writeb(dev->pdev, dev->addr + QVIRTIO_PCI_DEVICE_STATUS, status);
 131 }
 132
 133 static bool qvirtio_pci_get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq)
 134 {
 135     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 136     QVirtQueuePCI *vqpci = (QVirtQueuePCI *)vq;
 137     uint32_t data;
 138
 139     if (dev->pdev->msix_enabled) {
 140         g_assert_cmpint(vqpci->msix_entry, !=, -1);
 141         if (qpci_msix_masked(dev->pdev, vqpci->msix_entry)) {
 142             /* No ISR checking should be done if masked, but read anyway */
 143             return qpci_msix_pending(dev->pdev, vqpci->msix_entry);
 144         } else {
 145             data = readl(vqpci->msix_addr);
 146             if (data == vqpci->msix_data) {
 147                 writel(vqpci->msix_addr, 0);
 148                 return true;
 149             } else {
 150                 return false;
 151             }
 152         }
 153     } else {
 154         return qpci_io_readb(dev->pdev, dev->addr + QVIRTIO_PCI_ISR_STATUS) & 1;
 155     }
 156 }
 157
 158 static bool qvirtio_pci_get_config_isr_status(QVirtioDevice *d)
 159 {
 160     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 161     uint32_t data;
 162
 163     if (dev->pdev->msix_enabled) {
 164         g_assert_cmpint(dev->config_msix_entry, !=, -1);
 165         if (qpci_msix_masked(dev->pdev, dev->config_msix_entry)) {
 166             /* No ISR checking should be done if masked, but read anyway */
 167             return qpci_msix_pending(dev->pdev, dev->config_msix_entry);
 168         } else {
 169             data = readl(dev->config_msix_addr);
 170             if (data == dev->config_msix_data) {
 171                 writel(dev->config_msix_addr, 0);
 172                 return true;
 173             } else {
 174                 return false;
 175             }
 176         }
 177     } else {
 178         return qpci_io_readb(dev->pdev, dev->addr + QVIRTIO_PCI_ISR_STATUS) & 2;
 179     }
 180 }
 181
 182 static void qvirtio_pci_queue_select(QVirtioDevice *d, uint16_t index)
 183 {
 184     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 185     qpci_io_writeb(dev->pdev, dev->addr + QVIRTIO_PCI_QUEUE_SELECT, index);
 186 }
 187
 188 static uint16_t qvirtio_pci_get_queue_size(QVirtioDevice *d)
 189 {
 190     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 191     return qpci_io_readw(dev->pdev, dev->addr + QVIRTIO_PCI_QUEUE_SIZE);
 192 }
 193
 194 static void qvirtio_pci_set_queue_address(QVirtioDevice *d, uint32_t pfn)
 195 {
 196     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 197     qpci_io_writel(dev->pdev, dev->addr + QVIRTIO_PCI_QUEUE_ADDRESS, pfn);
 198 }
 199
 200 static QVirtQueue *qvirtio_pci_virtqueue_setup(QVirtioDevice *d,
 201                                         QGuestAllocator *alloc, uint16_t index)
 202 {
 203     uint32_t feat;
 204     uint64_t addr;
 205     QVirtQueuePCI *vqpci;
 206
 207     vqpci = g_malloc0(sizeof(*vqpci));
 208     feat = qvirtio_pci_get_guest_features(d);
 209
 210     qvirtio_pci_queue_select(d, index);
 211     vqpci->vq.index = index;
 212     vqpci->vq.size = qvirtio_pci_get_queue_size(d);
 213     vqpci->vq.free_head = 0;
 214     vqpci->vq.num_free = vqpci->vq.size;
 215     vqpci->vq.align = QVIRTIO_PCI_ALIGN;
 216     vqpci->vq.indirect = (feat & (1u << VIRTIO_RING_F_INDIRECT_DESC)) != 0;
 217     vqpci->vq.event = (feat & (1u << VIRTIO_RING_F_EVENT_IDX)) != 0;
 218
 219     vqpci->msix_entry = -1;
 220     vqpci->msix_addr = 0;
 221     vqpci->msix_data = 0x12345678;
 222
 223     /* Check different than 0 */
 224     g_assert_cmpint(vqpci->vq.size, !=, 0);
 225
 226     /* Check power of 2 */
 227     g_assert_cmpint(vqpci->vq.size & (vqpci->vq.size - 1), ==, 0);
 228
 229     addr = guest_alloc(alloc, qvring_size(vqpci->vq.size, QVIRTIO_PCI_ALIGN));
 230     qvring_init(alloc, &vqpci->vq, addr);
 231     qvirtio_pci_set_queue_address(d, vqpci->vq.desc / QVIRTIO_PCI_ALIGN);
 232
 233     return &vqpci->vq;
 234 }
 235
 236 static void qvirtio_pci_virtqueue_kick(QVirtioDevice *d, QVirtQueue *vq)
 237 {
 238     QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
 239     qpci_io_writew(dev->pdev, dev->addr + QVIRTIO_PCI_QUEUE_NOTIFY, vq->index);
 240 }
 241
 242 const QVirtioBus qvirtio_pci = {
 243     .config_readb = qvirtio_pci_config_readb,
 244     .config_readw = qvirtio_pci_config_readw,
 245     .config_readl = qvirtio_pci_config_readl,
 246     .config_readq = qvirtio_pci_config_readq,
 247     .get_features = qvirtio_pci_get_features,
 248     .set_features = qvirtio_pci_set_features,
 249     .get_guest_features = qvirtio_pci_get_guest_features,
 250     .get_status = qvirtio_pci_get_status,
 251     .set_status = qvirtio_pci_set_status,
 252     .get_queue_isr_status = qvirtio_pci_get_queue_isr_status,
 253     .get_config_isr_status = qvirtio_pci_get_config_isr_status,
 254     .queue_select = qvirtio_pci_queue_select,
 255     .get_queue_size = qvirtio_pci_get_queue_size,
 256     .set_queue_address = qvirtio_pci_set_queue_address,
 257     .virtqueue_setup = qvirtio_pci_virtqueue_setup,
 258     .virtqueue_kick = qvirtio_pci_virtqueue_kick,
 259 };
 260
 261 void qvirtio_pci_foreach(QPCIBus *bus, uint16_t device_type,
 262                 void (*func)(QVirtioDevice *d, void *data), void *data)
 263 {
 264     QVirtioPCIForeachData d = { .func = func,
 265                                 .device_type = device_type,
 266                                 .user_data = data };
 267
 268     qpci_device_foreach(bus, PCI_VENDOR_ID_REDHAT_QUMRANET, -1,
 269                                 qvirtio_pci_foreach_callback, &d);
 270 }
 271
 272 QVirtioPCIDevice *qvirtio_pci_device_find(QPCIBus *bus, uint16_t device_type)
 273 {
 274     QVirtioPCIDevice *dev = NULL;
 275     qvirtio_pci_foreach(bus, device_type, qvirtio_pci_assign_device, &dev);
 276
 277     return dev;
 278 }
 279
 280 void qvirtio_pci_device_enable(QVirtioPCIDevice *d)
 281 {
 282     qpci_device_enable(d->pdev);
 283     d->addr = qpci_iomap(d->pdev, 0, NULL);
 284     g_assert(d->addr != NULL);
 285 }
 286
 287 void qvirtio_pci_device_disable(QVirtioPCIDevice *d)
 288 {
 289     qpci_iounmap(d->pdev, d->addr);
 290     d->addr = NULL;
 291 }
 292
 293 void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, QVirtQueuePCI *vqpci,
 294                                         QGuestAllocator *alloc, uint16_t entry)
 295 {
 296     uint16_t vector;
 297     uint32_t control;
 298     void *addr;
 299
 300     g_assert(d->pdev->msix_enabled);
 301     addr = d->pdev->msix_table + (entry * 16);
 302
 303     g_assert_cmpint(entry, >=, 0);
 304     g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev));
 305     vqpci->msix_entry = entry;
 306
 307     vqpci->msix_addr = guest_alloc(alloc, 4);
 308     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_LOWER_ADDR,
 309                                                     vqpci->msix_addr & ~0UL);
 310     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_UPPER_ADDR,
 311                                             (vqpci->msix_addr >> 32) & ~0UL);
 312     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_DATA, vqpci->msix_data);
 313
 314     control = qpci_io_readl(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
 315     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL,
 316                                         control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT);
 317
 318     qvirtio_pci_queue_select(&d->vdev, vqpci->vq.index);
 319     qpci_io_writew(d->pdev, d->addr + QVIRTIO_PCI_MSIX_QUEUE_VECTOR, entry);
 320     vector = qpci_io_readw(d->pdev, d->addr + QVIRTIO_PCI_MSIX_QUEUE_VECTOR);
 321     g_assert_cmphex(vector, !=, QVIRTIO_MSI_NO_VECTOR);
 322 }
 323
 324 void qvirtio_pci_set_msix_configuration_vector(QVirtioPCIDevice *d,
 325                                         QGuestAllocator *alloc, uint16_t entry)
 326 {
 327     uint16_t vector;
 328     uint32_t control;
 329     void *addr;
 330
 331     g_assert(d->pdev->msix_enabled);
 332     addr = d->pdev->msix_table + (entry * 16);
 333
 334     g_assert_cmpint(entry, >=, 0);
 335     g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev));
 336     d->config_msix_entry = entry;
 337
 338     d->config_msix_data = 0x12345678;
 339     d->config_msix_addr = guest_alloc(alloc, 4);
 340
 341     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_LOWER_ADDR,
 342                                                     d->config_msix_addr & ~0UL);
 343     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_UPPER_ADDR,
 344                                             (d->config_msix_addr >> 32) & ~0UL);
 345     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_DATA, d->config_msix_data);
 346
 347     control = qpci_io_readl(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
 348     qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL,
 349                                         control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT);
 350
 351     qpci_io_writew(d->pdev, d->addr + QVIRTIO_PCI_MSIX_CONF_VECTOR, entry);
 352     vector = qpci_io_readw(d->pdev, d->addr + QVIRTIO_PCI_MSIX_CONF_VECTOR);
 353     g_assert_cmphex(vector, !=, QVIRTIO_MSI_NO_VECTOR);
 354 }