hw/usb/tusb6010.c

   1 /*
   2  * Texas Instruments TUSB6010 emulation.
   3  * Based on reverse-engineering of a linux driver.
   4  *
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Written by Andrzej Zaborowski <andrew@openedhand.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 or
  11  * (at your option) version 3 of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21 #include "qemu/osdep.h"
  22 #include "qemu-common.h"
  23 #include "qemu/timer.h"
  24 #include "hw/usb.h"
  25 #include "hw/arm/omap.h"
  26 #include "hw/irq.h"
  27 #include "hw/devices.h"
  28 #include "hw/sysbus.h"
  29
  30 #define TYPE_TUSB6010 "tusb6010"
  31 #define TUSB(obj) OBJECT_CHECK(TUSBState, (obj), TYPE_TUSB6010)
  32
  33 typedef struct TUSBState {
  34     SysBusDevice parent_obj;
  35
  36     MemoryRegion iomem[2];
  37     qemu_irq irq;
  38     MUSBState *musb;
  39     QEMUTimer *otg_timer;
  40     QEMUTimer *pwr_timer;
  41
  42     int power;
  43     uint32_t scratch;
  44     uint16_t test_reset;
  45     uint32_t prcm_config;
  46     uint32_t prcm_mngmt;
  47     uint16_t otg_status;
  48     uint32_t dev_config;
  49     int host_mode;
  50     uint32_t intr;
  51     uint32_t intr_ok;
  52     uint32_t mask;
  53     uint32_t usbip_intr;
  54     uint32_t usbip_mask;
  55     uint32_t gpio_intr;
  56     uint32_t gpio_mask;
  57     uint32_t gpio_config;
  58     uint32_t dma_intr;
  59     uint32_t dma_mask;
  60     uint32_t dma_map;
  61     uint32_t dma_config;
  62     uint32_t ep0_config;
  63     uint32_t rx_config[15];
  64     uint32_t tx_config[15];
  65     uint32_t wkup_mask;
  66     uint32_t pullup[2];
  67     uint32_t control_config;
  68     uint32_t otg_timer_val;
  69 } TUSBState;
  70
  71 #define TUSB_DEVCLOCK                   60000000        /* 60 MHz */
  72
  73 #define TUSB_VLYNQ_CTRL                 0x004
  74
  75 /* Mentor Graphics OTG core registers.  */
  76 #define TUSB_BASE_OFFSET                0x400
  77
  78 /* FIFO registers, 32-bit.  */
  79 #define TUSB_FIFO_BASE                  0x600
  80
  81 /* Device System & Control registers, 32-bit.  */
  82 #define TUSB_SYS_REG_BASE               0x800
  83
  84 #define TUSB_DEV_CONF                   (TUSB_SYS_REG_BASE + 0x000)
  85 #define TUSB_DEV_CONF_USB_HOST_MODE     (1 << 16)
  86 #define TUSB_DEV_CONF_PROD_TEST_MODE    (1 << 15)
  87 #define TUSB_DEV_CONF_SOFT_ID           (1 << 1)
  88 #define TUSB_DEV_CONF_ID_SEL            (1 << 0)
  89
  90 #define TUSB_PHY_OTG_CTRL_ENABLE        (TUSB_SYS_REG_BASE + 0x004)
  91 #define TUSB_PHY_OTG_CTRL               (TUSB_SYS_REG_BASE + 0x008)
  92 #define TUSB_PHY_OTG_CTRL_WRPROTECT     (0xa5 << 24)
  93 #define TUSB_PHY_OTG_CTRL_O_ID_PULLUP   (1 << 23)
  94 #define TUSB_PHY_OTG_CTRL_O_VBUS_DET_EN (1 << 19)
  95 #define TUSB_PHY_OTG_CTRL_O_SESS_END_EN (1 << 18)
  96 #define TUSB_PHY_OTG_CTRL_TESTM2        (1 << 17)
  97 #define TUSB_PHY_OTG_CTRL_TESTM1        (1 << 16)
  98 #define TUSB_PHY_OTG_CTRL_TESTM0        (1 << 15)
  99 #define TUSB_PHY_OTG_CTRL_TX_DATA2      (1 << 14)
 100 #define TUSB_PHY_OTG_CTRL_TX_GZ2        (1 << 13)
 101 #define TUSB_PHY_OTG_CTRL_TX_ENABLE2    (1 << 12)
 102 #define TUSB_PHY_OTG_CTRL_DM_PULLDOWN   (1 << 11)
 103 #define TUSB_PHY_OTG_CTRL_DP_PULLDOWN   (1 << 10)
 104 #define TUSB_PHY_OTG_CTRL_OSC_EN        (1 << 9)
 105 #define TUSB_PHY_OTG_CTRL_PHYREF_CLK(v) (((v) & 3) << 7)
 106 #define TUSB_PHY_OTG_CTRL_PD            (1 << 6)
 107 #define TUSB_PHY_OTG_CTRL_PLL_ON        (1 << 5)
 108 #define TUSB_PHY_OTG_CTRL_EXT_RPU       (1 << 4)
 109 #define TUSB_PHY_OTG_CTRL_PWR_GOOD      (1 << 3)
 110 #define TUSB_PHY_OTG_CTRL_RESET         (1 << 2)
 111 #define TUSB_PHY_OTG_CTRL_SUSPENDM      (1 << 1)
 112 #define TUSB_PHY_OTG_CTRL_CLK_MODE      (1 << 0)
 113
 114 /* OTG status register */
 115 #define TUSB_DEV_OTG_STAT               (TUSB_SYS_REG_BASE + 0x00c)
 116 #define TUSB_DEV_OTG_STAT_PWR_CLK_GOOD  (1 << 8)
 117 #define TUSB_DEV_OTG_STAT_SESS_END      (1 << 7)
 118 #define TUSB_DEV_OTG_STAT_SESS_VALID    (1 << 6)
 119 #define TUSB_DEV_OTG_STAT_VBUS_VALID    (1 << 5)
 120 #define TUSB_DEV_OTG_STAT_VBUS_SENSE    (1 << 4)
 121 #define TUSB_DEV_OTG_STAT_ID_STATUS     (1 << 3)
 122 #define TUSB_DEV_OTG_STAT_HOST_DISCON   (1 << 2)
 123 #define TUSB_DEV_OTG_STAT_LINE_STATE    (3 << 0)
 124 #define TUSB_DEV_OTG_STAT_DP_ENABLE     (1 << 1)
 125 #define TUSB_DEV_OTG_STAT_DM_ENABLE     (1 << 0)
 126
 127 #define TUSB_DEV_OTG_TIMER              (TUSB_SYS_REG_BASE + 0x010)
 128 #define TUSB_DEV_OTG_TIMER_ENABLE       (1 << 31)
 129 #define TUSB_DEV_OTG_TIMER_VAL(v)       ((v) & 0x07ffffff)
 130 #define TUSB_PRCM_REV                   (TUSB_SYS_REG_BASE + 0x014)
 131
 132 /* PRCM configuration register */
 133 #define TUSB_PRCM_CONF                  (TUSB_SYS_REG_BASE + 0x018)
 134 #define TUSB_PRCM_CONF_SFW_CPEN         (1 << 24)
 135 #define TUSB_PRCM_CONF_SYS_CLKSEL(v)    (((v) & 3) << 16)
 136
 137 /* PRCM management register */
 138 #define TUSB_PRCM_MNGMT                 (TUSB_SYS_REG_BASE + 0x01c)
 139 #define TUSB_PRCM_MNGMT_SRP_FIX_TMR(v)  (((v) & 0xf) << 25)
 140 #define TUSB_PRCM_MNGMT_SRP_FIX_EN      (1 << 24)
 141 #define TUSB_PRCM_MNGMT_VBUS_VAL_TMR(v) (((v) & 0xf) << 20)
 142 #define TUSB_PRCM_MNGMT_VBUS_VAL_FLT_EN (1 << 19)
 143 #define TUSB_PRCM_MNGMT_DFT_CLK_DIS     (1 << 18)
 144 #define TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS   (1 << 17)
 145 #define TUSB_PRCM_MNGMT_OTG_SESS_END_EN (1 << 10)
 146 #define TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN (1 << 9)
 147 #define TUSB_PRCM_MNGMT_OTG_ID_PULLUP   (1 << 8)
 148 #define TUSB_PRCM_MNGMT_15_SW_EN        (1 << 4)
 149 #define TUSB_PRCM_MNGMT_33_SW_EN        (1 << 3)
 150 #define TUSB_PRCM_MNGMT_5V_CPEN         (1 << 2)
 151 #define TUSB_PRCM_MNGMT_PM_IDLE         (1 << 1)
 152 #define TUSB_PRCM_MNGMT_DEV_IDLE        (1 << 0)
 153
 154 /* Wake-up source clear and mask registers */
 155 #define TUSB_PRCM_WAKEUP_SOURCE         (TUSB_SYS_REG_BASE + 0x020)
 156 #define TUSB_PRCM_WAKEUP_CLEAR          (TUSB_SYS_REG_BASE + 0x028)
 157 #define TUSB_PRCM_WAKEUP_MASK           (TUSB_SYS_REG_BASE + 0x02c)
 158 #define TUSB_PRCM_WAKEUP_RESERVED_BITS  (0xffffe << 13)
 159 #define TUSB_PRCM_WGPIO_7               (1 << 12)
 160 #define TUSB_PRCM_WGPIO_6               (1 << 11)
 161 #define TUSB_PRCM_WGPIO_5               (1 << 10)
 162 #define TUSB_PRCM_WGPIO_4               (1 << 9)
 163 #define TUSB_PRCM_WGPIO_3               (1 << 8)
 164 #define TUSB_PRCM_WGPIO_2               (1 << 7)
 165 #define TUSB_PRCM_WGPIO_1               (1 << 6)
 166 #define TUSB_PRCM_WGPIO_0               (1 << 5)
 167 #define TUSB_PRCM_WHOSTDISCON           (1 << 4)        /* Host disconnect */
 168 #define TUSB_PRCM_WBUS                  (1 << 3)        /* USB bus resume */
 169 #define TUSB_PRCM_WNORCS                (1 << 2)        /* NOR chip select */
 170 #define TUSB_PRCM_WVBUS                 (1 << 1)        /* OTG PHY VBUS */
 171 #define TUSB_PRCM_WID                   (1 << 0)        /* OTG PHY ID detect */
 172
 173 #define TUSB_PULLUP_1_CTRL              (TUSB_SYS_REG_BASE + 0x030)
 174 #define TUSB_PULLUP_2_CTRL              (TUSB_SYS_REG_BASE + 0x034)
 175 #define TUSB_INT_CTRL_REV               (TUSB_SYS_REG_BASE + 0x038)
 176 #define TUSB_INT_CTRL_CONF              (TUSB_SYS_REG_BASE + 0x03c)
 177 #define TUSB_USBIP_INT_SRC              (TUSB_SYS_REG_BASE + 0x040)
 178 #define TUSB_USBIP_INT_SET              (TUSB_SYS_REG_BASE + 0x044)
 179 #define TUSB_USBIP_INT_CLEAR            (TUSB_SYS_REG_BASE + 0x048)
 180 #define TUSB_USBIP_INT_MASK             (TUSB_SYS_REG_BASE + 0x04c)
 181 #define TUSB_DMA_INT_SRC                (TUSB_SYS_REG_BASE + 0x050)
 182 #define TUSB_DMA_INT_SET                (TUSB_SYS_REG_BASE + 0x054)
 183 #define TUSB_DMA_INT_CLEAR              (TUSB_SYS_REG_BASE + 0x058)
 184 #define TUSB_DMA_INT_MASK               (TUSB_SYS_REG_BASE + 0x05c)
 185 #define TUSB_GPIO_INT_SRC               (TUSB_SYS_REG_BASE + 0x060)
 186 #define TUSB_GPIO_INT_SET               (TUSB_SYS_REG_BASE + 0x064)
 187 #define TUSB_GPIO_INT_CLEAR             (TUSB_SYS_REG_BASE + 0x068)
 188 #define TUSB_GPIO_INT_MASK              (TUSB_SYS_REG_BASE + 0x06c)
 189
 190 /* NOR flash interrupt source registers */
 191 #define TUSB_INT_SRC                    (TUSB_SYS_REG_BASE + 0x070)
 192 #define TUSB_INT_SRC_SET                (TUSB_SYS_REG_BASE + 0x074)
 193 #define TUSB_INT_SRC_CLEAR              (TUSB_SYS_REG_BASE + 0x078)
 194 #define TUSB_INT_MASK                   (TUSB_SYS_REG_BASE + 0x07c)
 195 #define TUSB_INT_SRC_TXRX_DMA_DONE      (1 << 24)
 196 #define TUSB_INT_SRC_USB_IP_CORE        (1 << 17)
 197 #define TUSB_INT_SRC_OTG_TIMEOUT        (1 << 16)
 198 #define TUSB_INT_SRC_VBUS_SENSE_CHNG    (1 << 15)
 199 #define TUSB_INT_SRC_ID_STATUS_CHNG     (1 << 14)
 200 #define TUSB_INT_SRC_DEV_WAKEUP         (1 << 13)
 201 #define TUSB_INT_SRC_DEV_READY          (1 << 12)
 202 #define TUSB_INT_SRC_USB_IP_TX          (1 << 9)
 203 #define TUSB_INT_SRC_USB_IP_RX          (1 << 8)
 204 #define TUSB_INT_SRC_USB_IP_VBUS_ERR    (1 << 7)
 205 #define TUSB_INT_SRC_USB_IP_VBUS_REQ    (1 << 6)
 206 #define TUSB_INT_SRC_USB_IP_DISCON      (1 << 5)
 207 #define TUSB_INT_SRC_USB_IP_CONN        (1 << 4)
 208 #define TUSB_INT_SRC_USB_IP_SOF         (1 << 3)
 209 #define TUSB_INT_SRC_USB_IP_RST_BABBLE  (1 << 2)
 210 #define TUSB_INT_SRC_USB_IP_RESUME      (1 << 1)
 211 #define TUSB_INT_SRC_USB_IP_SUSPEND     (1 << 0)
 212
 213 #define TUSB_GPIO_REV                   (TUSB_SYS_REG_BASE + 0x080)
 214 #define TUSB_GPIO_CONF                  (TUSB_SYS_REG_BASE + 0x084)
 215 #define TUSB_DMA_CTRL_REV               (TUSB_SYS_REG_BASE + 0x100)
 216 #define TUSB_DMA_REQ_CONF               (TUSB_SYS_REG_BASE + 0x104)
 217 #define TUSB_EP0_CONF                   (TUSB_SYS_REG_BASE + 0x108)
 218 #define TUSB_EP_IN_SIZE                 (TUSB_SYS_REG_BASE + 0x10c)
 219 #define TUSB_DMA_EP_MAP                 (TUSB_SYS_REG_BASE + 0x148)
 220 #define TUSB_EP_OUT_SIZE                (TUSB_SYS_REG_BASE + 0x14c)
 221 #define TUSB_EP_MAX_PACKET_SIZE_OFFSET  (TUSB_SYS_REG_BASE + 0x188)
 222 #define TUSB_SCRATCH_PAD                (TUSB_SYS_REG_BASE + 0x1c4)
 223 #define TUSB_WAIT_COUNT                 (TUSB_SYS_REG_BASE + 0x1c8)
 224 #define TUSB_PROD_TEST_RESET            (TUSB_SYS_REG_BASE + 0x1d8)
 225
 226 #define TUSB_DIDR1_LO                   (TUSB_SYS_REG_BASE + 0x1f8)
 227 #define TUSB_DIDR1_HI                   (TUSB_SYS_REG_BASE + 0x1fc)
 228
 229 /* Device System & Control register bitfields */
 230 #define TUSB_INT_CTRL_CONF_INT_RLCYC(v) (((v) & 0x7) << 18)
 231 #define TUSB_INT_CTRL_CONF_INT_POLARITY (1 << 17)
 232 #define TUSB_INT_CTRL_CONF_INT_MODE     (1 << 16)
 233 #define TUSB_GPIO_CONF_DMAREQ(v)        (((v) & 0x3f) << 24)
 234 #define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26)
 235 #define TUSB_DMA_REQ_CONF_DMA_RQ_EN(v)  (((v) & 0x3f) << 20)
 236 #define TUSB_DMA_REQ_CONF_DMA_RQ_ASR(v) (((v) & 0xf) << 16)
 237 #define TUSB_EP0_CONFIG_SW_EN           (1 << 8)
 238 #define TUSB_EP0_CONFIG_DIR_TX          (1 << 7)
 239 #define TUSB_EP0_CONFIG_XFR_SIZE(v)     ((v) & 0x7f)
 240 #define TUSB_EP_CONFIG_SW_EN            (1 << 31)
 241 #define TUSB_EP_CONFIG_XFR_SIZE(v)      ((v) & 0x7fffffff)
 242 #define TUSB_PROD_TEST_RESET_VAL        0xa596
 243
 244 static void tusb_intr_update(TUSBState *s)
 245 {
 246     if (s->control_config & TUSB_INT_CTRL_CONF_INT_POLARITY)
 247         qemu_set_irq(s->irq, s->intr & ~s->mask & s->intr_ok);
 248     else
 249         qemu_set_irq(s->irq, (!(s->intr & ~s->mask)) & s->intr_ok);
 250 }
 251
 252 static void tusb_usbip_intr_update(TUSBState *s)
 253 {
 254     /* TX interrupt in the MUSB */
 255     if (s->usbip_intr & 0x0000ffff & ~s->usbip_mask)
 256         s->intr |= TUSB_INT_SRC_USB_IP_TX;
 257     else
 258         s->intr &= ~TUSB_INT_SRC_USB_IP_TX;
 259
 260     /* RX interrupt in the MUSB */
 261     if (s->usbip_intr & 0xffff0000 & ~s->usbip_mask)
 262         s->intr |= TUSB_INT_SRC_USB_IP_RX;
 263     else
 264         s->intr &= ~TUSB_INT_SRC_USB_IP_RX;
 265
 266     /* XXX: What about TUSB_INT_SRC_USB_IP_CORE?  */
 267
 268     tusb_intr_update(s);
 269 }
 270
 271 static void tusb_dma_intr_update(TUSBState *s)
 272 {
 273     if (s->dma_intr & ~s->dma_mask)
 274         s->intr |= TUSB_INT_SRC_TXRX_DMA_DONE;
 275     else
 276         s->intr &= ~TUSB_INT_SRC_TXRX_DMA_DONE;
 277
 278     tusb_intr_update(s);
 279 }
 280
 281 static void tusb_gpio_intr_update(TUSBState *s)
 282 {
 283     /* TODO: How is this signalled?  */
 284 }
 285
 286 static uint32_t tusb_async_readb(void *opaque, hwaddr addr)
 287 {
 288     TUSBState *s = (TUSBState *) opaque;
 289
 290     switch (addr & 0xfff) {
 291     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
 292         return musb_read[0](s->musb, addr & 0x1ff);
 293
 294     case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
 295         return musb_read[0](s->musb, 0x20 + ((addr >> 3) & 0x3c));
 296     }
 297
 298     printf("%s: unknown register at %03x\n",
 299                     __FUNCTION__, (int) (addr & 0xfff));
 300     return 0;
 301 }
 302
 303 static uint32_t tusb_async_readh(void *opaque, hwaddr addr)
 304 {
 305     TUSBState *s = (TUSBState *) opaque;
 306
 307     switch (addr & 0xfff) {
 308     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
 309         return musb_read[1](s->musb, addr & 0x1ff);
 310
 311     case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
 312         return musb_read[1](s->musb, 0x20 + ((addr >> 3) & 0x3c));
 313     }
 314
 315     printf("%s: unknown register at %03x\n",
 316                     __FUNCTION__, (int) (addr & 0xfff));
 317     return 0;
 318 }
 319
 320 static uint32_t tusb_async_readw(void *opaque, hwaddr addr)
 321 {
 322     TUSBState *s = (TUSBState *) opaque;
 323     int offset = addr & 0xfff;
 324     int epnum;
 325     uint32_t ret;
 326
 327     switch (offset) {
 328     case TUSB_DEV_CONF:
 329         return s->dev_config;
 330
 331     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
 332         return musb_read[2](s->musb, offset & 0x1ff);
 333
 334     case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
 335         return musb_read[2](s->musb, 0x20 + ((addr >> 3) & 0x3c));
 336
 337     case TUSB_PHY_OTG_CTRL_ENABLE:
 338     case TUSB_PHY_OTG_CTRL:
 339         return 0x00;    /* TODO */
 340
 341     case TUSB_DEV_OTG_STAT:
 342         ret = s->otg_status;
 343 #if 0
 344         if (!(s->prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN))
 345             ret &= ~TUSB_DEV_OTG_STAT_VBUS_VALID;
 346 #endif
 347         return ret;
 348     case TUSB_DEV_OTG_TIMER:
 349         return s->otg_timer_val;
 350
 351     case TUSB_PRCM_REV:
 352         return 0x20;
 353     case TUSB_PRCM_CONF:
 354         return s->prcm_config;
 355     case TUSB_PRCM_MNGMT:
 356         return s->prcm_mngmt;
 357     case TUSB_PRCM_WAKEUP_SOURCE:
 358     case TUSB_PRCM_WAKEUP_CLEAR:        /* TODO: What does this one return?  */
 359         return 0x00000000;
 360     case TUSB_PRCM_WAKEUP_MASK:
 361         return s->wkup_mask;
 362
 363     case TUSB_PULLUP_1_CTRL:
 364         return s->pullup[0];
 365     case TUSB_PULLUP_2_CTRL:
 366         return s->pullup[1];
 367
 368     case TUSB_INT_CTRL_REV:
 369         return 0x20;
 370     case TUSB_INT_CTRL_CONF:
 371         return s->control_config;
 372
 373     case TUSB_USBIP_INT_SRC:
 374     case TUSB_USBIP_INT_SET:    /* TODO: What do these two return?  */
 375     case TUSB_USBIP_INT_CLEAR:
 376         return s->usbip_intr;
 377     case TUSB_USBIP_INT_MASK:
 378         return s->usbip_mask;
 379
 380     case TUSB_DMA_INT_SRC:
 381     case TUSB_DMA_INT_SET:      /* TODO: What do these two return?  */
 382     case TUSB_DMA_INT_CLEAR:
 383         return s->dma_intr;
 384     case TUSB_DMA_INT_MASK:
 385         return s->dma_mask;
 386
 387     case TUSB_GPIO_INT_SRC:     /* TODO: What do these two return?  */
 388     case TUSB_GPIO_INT_SET:
 389     case TUSB_GPIO_INT_CLEAR:
 390         return s->gpio_intr;
 391     case TUSB_GPIO_INT_MASK:
 392         return s->gpio_mask;
 393
 394     case TUSB_INT_SRC:
 395     case TUSB_INT_SRC_SET:      /* TODO: What do these two return?  */
 396     case TUSB_INT_SRC_CLEAR:
 397         return s->intr;
 398     case TUSB_INT_MASK:
 399         return s->mask;
 400
 401     case TUSB_GPIO_REV:
 402         return 0x30;
 403     case TUSB_GPIO_CONF:
 404         return s->gpio_config;
 405
 406     case TUSB_DMA_CTRL_REV:
 407         return 0x30;
 408     case TUSB_DMA_REQ_CONF:
 409         return s->dma_config;
 410     case TUSB_EP0_CONF:
 411         return s->ep0_config;
 412     case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b):
 413         epnum = (offset - TUSB_EP_IN_SIZE) >> 2;
 414         return s->tx_config[epnum];
 415     case TUSB_DMA_EP_MAP:
 416         return s->dma_map;
 417     case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b):
 418         epnum = (offset - TUSB_EP_OUT_SIZE) >> 2;
 419         return s->rx_config[epnum];
 420     case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
 421             (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
 422         return 0x00000000;      /* TODO */
 423     case TUSB_WAIT_COUNT:
 424         return 0x00;            /* TODO */
 425
 426     case TUSB_SCRATCH_PAD:
 427         return s->scratch;
 428
 429     case TUSB_PROD_TEST_RESET:
 430         return s->test_reset;
 431
 432     /* DIE IDs */
 433     case TUSB_DIDR1_LO:
 434         return 0xa9453c59;
 435     case TUSB_DIDR1_HI:
 436         return 0x54059adf;
 437     }
 438
 439     printf("%s: unknown register at %03x\n", __FUNCTION__, offset);
 440     return 0;
 441 }
 442
 443 static void tusb_async_writeb(void *opaque, hwaddr addr,
 444                 uint32_t value)
 445 {
 446     TUSBState *s = (TUSBState *) opaque;
 447
 448     switch (addr & 0xfff) {
 449     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
 450         musb_write[0](s->musb, addr & 0x1ff, value);
 451         break;
 452
 453     case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
 454         musb_write[0](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
 455         break;
 456
 457     default:
 458         printf("%s: unknown register at %03x\n",
 459                         __FUNCTION__, (int) (addr & 0xfff));
 460         return;
 461     }
 462 }
 463
 464 static void tusb_async_writeh(void *opaque, hwaddr addr,
 465                 uint32_t value)
 466 {
 467     TUSBState *s = (TUSBState *) opaque;
 468
 469     switch (addr & 0xfff) {
 470     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
 471         musb_write[1](s->musb, addr & 0x1ff, value);
 472         break;
 473
 474     case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
 475         musb_write[1](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
 476         break;
 477
 478     default:
 479         printf("%s: unknown register at %03x\n",
 480                         __FUNCTION__, (int) (addr & 0xfff));
 481         return;
 482     }
 483 }
 484
 485 static void tusb_async_writew(void *opaque, hwaddr addr,
 486                 uint32_t value)
 487 {
 488     TUSBState *s = (TUSBState *) opaque;
 489     int offset = addr & 0xfff;
 490     int epnum;
 491
 492     switch (offset) {
 493     case TUSB_VLYNQ_CTRL:
 494         break;
 495
 496     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
 497         musb_write[2](s->musb, offset & 0x1ff, value);
 498         break;
 499
 500     case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff):
 501         musb_write[2](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
 502         break;
 503
 504     case TUSB_DEV_CONF:
 505         s->dev_config = value;
 506         s->host_mode = (value & TUSB_DEV_CONF_USB_HOST_MODE);
 507         if (value & TUSB_DEV_CONF_PROD_TEST_MODE)
 508             hw_error("%s: Product Test mode not allowed\n", __FUNCTION__);
 509         break;
 510
 511     case TUSB_PHY_OTG_CTRL_ENABLE:
 512     case TUSB_PHY_OTG_CTRL:
 513         return;         /* TODO */
 514     case TUSB_DEV_OTG_TIMER:
 515         s->otg_timer_val = value;
 516         if (value & TUSB_DEV_OTG_TIMER_ENABLE)
 517             timer_mod(s->otg_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 518                             muldiv64(TUSB_DEV_OTG_TIMER_VAL(value),
 519                                      get_ticks_per_sec(), TUSB_DEVCLOCK));
 520         else
 521             timer_del(s->otg_timer);
 522         break;
 523
 524     case TUSB_PRCM_CONF:
 525         s->prcm_config = value;
 526         break;
 527     case TUSB_PRCM_MNGMT:
 528         s->prcm_mngmt = value;
 529         break;
 530     case TUSB_PRCM_WAKEUP_CLEAR:
 531         break;
 532     case TUSB_PRCM_WAKEUP_MASK:
 533         s->wkup_mask = value;
 534         break;
 535
 536     case TUSB_PULLUP_1_CTRL:
 537         s->pullup[0] = value;
 538         break;
 539     case TUSB_PULLUP_2_CTRL:
 540         s->pullup[1] = value;
 541         break;
 542     case TUSB_INT_CTRL_CONF:
 543         s->control_config = value;
 544         tusb_intr_update(s);
 545         break;
 546
 547     case TUSB_USBIP_INT_SET:
 548         s->usbip_intr |= value;
 549         tusb_usbip_intr_update(s);
 550         break;
 551     case TUSB_USBIP_INT_CLEAR:
 552         s->usbip_intr &= ~value;
 553         tusb_usbip_intr_update(s);
 554         musb_core_intr_clear(s->musb, ~value);
 555         break;
 556     case TUSB_USBIP_INT_MASK:
 557         s->usbip_mask = value;
 558         tusb_usbip_intr_update(s);
 559         break;
 560
 561     case TUSB_DMA_INT_SET:
 562         s->dma_intr |= value;
 563         tusb_dma_intr_update(s);
 564         break;
 565     case TUSB_DMA_INT_CLEAR:
 566         s->dma_intr &= ~value;
 567         tusb_dma_intr_update(s);
 568         break;
 569     case TUSB_DMA_INT_MASK:
 570         s->dma_mask = value;
 571         tusb_dma_intr_update(s);
 572         break;
 573
 574     case TUSB_GPIO_INT_SET:
 575         s->gpio_intr |= value;
 576         tusb_gpio_intr_update(s);
 577         break;
 578     case TUSB_GPIO_INT_CLEAR:
 579         s->gpio_intr &= ~value;
 580         tusb_gpio_intr_update(s);
 581         break;
 582     case TUSB_GPIO_INT_MASK:
 583         s->gpio_mask = value;
 584         tusb_gpio_intr_update(s);
 585         break;
 586
 587     case TUSB_INT_SRC_SET:
 588         s->intr |= value;
 589         tusb_intr_update(s);
 590         break;
 591     case TUSB_INT_SRC_CLEAR:
 592         s->intr &= ~value;
 593         tusb_intr_update(s);
 594         break;
 595     case TUSB_INT_MASK:
 596         s->mask = value;
 597         tusb_intr_update(s);
 598         break;
 599
 600     case TUSB_GPIO_CONF:
 601         s->gpio_config = value;
 602         break;
 603     case TUSB_DMA_REQ_CONF:
 604         s->dma_config = value;
 605         break;
 606     case TUSB_EP0_CONF:
 607         s->ep0_config = value & 0x1ff;
 608         musb_set_size(s->musb, 0, TUSB_EP0_CONFIG_XFR_SIZE(value),
 609                         value & TUSB_EP0_CONFIG_DIR_TX);
 610         break;
 611     case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b):
 612         epnum = (offset - TUSB_EP_IN_SIZE) >> 2;
 613         s->tx_config[epnum] = value;
 614         musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 1);
 615         break;
 616     case TUSB_DMA_EP_MAP:
 617         s->dma_map = value;
 618         break;
 619     case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b):
 620         epnum = (offset - TUSB_EP_OUT_SIZE) >> 2;
 621         s->rx_config[epnum] = value;
 622         musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 0);
 623         break;
 624     case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
 625             (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
 626         return;         /* TODO */
 627     case TUSB_WAIT_COUNT:
 628         return;         /* TODO */
 629
 630     case TUSB_SCRATCH_PAD:
 631         s->scratch = value;
 632         break;
 633
 634     case TUSB_PROD_TEST_RESET:
 635         s->test_reset = value;
 636         break;
 637
 638     default:
 639         printf("%s: unknown register at %03x\n", __FUNCTION__, offset);
 640         return;
 641     }
 642 }
 643
 644 static const MemoryRegionOps tusb_async_ops = {
 645     .old_mmio = {
 646         .read = { tusb_async_readb, tusb_async_readh, tusb_async_readw, },
 647         .write =  { tusb_async_writeb, tusb_async_writeh, tusb_async_writew, },
 648     },
 649     .endianness = DEVICE_NATIVE_ENDIAN,
 650 };
 651
 652 static void tusb_otg_tick(void *opaque)
 653 {
 654     TUSBState *s = (TUSBState *) opaque;
 655
 656     s->otg_timer_val = 0;
 657     s->intr |= TUSB_INT_SRC_OTG_TIMEOUT;
 658     tusb_intr_update(s);
 659 }
 660
 661 static void tusb_power_tick(void *opaque)
 662 {
 663     TUSBState *s = (TUSBState *) opaque;
 664
 665     if (s->power) {
 666         s->intr_ok = ~0;
 667         tusb_intr_update(s);
 668     }
 669 }
 670
 671 static void tusb_musb_core_intr(void *opaque, int source, int level)
 672 {
 673     TUSBState *s = (TUSBState *) opaque;
 674     uint16_t otg_status = s->otg_status;
 675
 676     switch (source) {
 677     case musb_set_vbus:
 678         if (level)
 679             otg_status |= TUSB_DEV_OTG_STAT_VBUS_VALID;
 680         else
 681             otg_status &= ~TUSB_DEV_OTG_STAT_VBUS_VALID;
 682
 683         /* XXX: only if TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN set?  */
 684         /* XXX: only if TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN set?  */
 685         if (s->otg_status != otg_status) {
 686             s->otg_status = otg_status;
 687             s->intr |= TUSB_INT_SRC_VBUS_SENSE_CHNG;
 688             tusb_intr_update(s);
 689         }
 690         break;
 691
 692     case musb_set_session:
 693         /* XXX: only if TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN set?  */
 694         /* XXX: only if TUSB_PRCM_MNGMT_OTG_SESS_END_EN set?  */
 695         if (level) {
 696             s->otg_status |= TUSB_DEV_OTG_STAT_SESS_VALID;
 697             s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_END;
 698         } else {
 699             s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_VALID;
 700             s->otg_status |= TUSB_DEV_OTG_STAT_SESS_END;
 701         }
 702
 703         /* XXX: some IRQ or anything?  */
 704         break;
 705
 706     case musb_irq_tx:
 707     case musb_irq_rx:
 708         s->usbip_intr = musb_core_intr_get(s->musb);
 709         /* Fall through.  */
 710     default:
 711         if (level)
 712             s->intr |= 1 << source;
 713         else
 714             s->intr &= ~(1 << source);
 715         tusb_intr_update(s);
 716         break;
 717     }
 718 }
 719
 720 static void tusb6010_power(TUSBState *s, int on)
 721 {
 722     if (!on) {
 723         s->power = 0;
 724     } else if (!s->power && on) {
 725         s->power = 1;
 726         /* Pull the interrupt down after TUSB6010 comes up.  */
 727         s->intr_ok = 0;
 728         tusb_intr_update(s);
 729         timer_mod(s->pwr_timer,
 730                        qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + get_ticks_per_sec() / 2);
 731     }
 732 }
 733
 734 static void tusb6010_irq(void *opaque, int source, int level)
 735 {
 736     if (source) {
 737         tusb_musb_core_intr(opaque, source - 1, level);
 738     } else {
 739         tusb6010_power(opaque, level);
 740     }
 741 }
 742
 743 static void tusb6010_reset(DeviceState *dev)
 744 {
 745     TUSBState *s = TUSB(dev);
 746     int i;
 747
 748     s->test_reset = TUSB_PROD_TEST_RESET_VAL;
 749     s->host_mode = 0;
 750     s->dev_config = 0;
 751     s->otg_status = 0;  /* !TUSB_DEV_OTG_STAT_ID_STATUS means host mode */
 752     s->power = 0;
 753     s->mask = 0xffffffff;
 754     s->intr = 0x00000000;
 755     s->otg_timer_val = 0;
 756     s->scratch = 0;
 757     s->prcm_config = 0;
 758     s->prcm_mngmt = 0;
 759     s->intr_ok = 0;
 760     s->usbip_intr = 0;
 761     s->usbip_mask = 0;
 762     s->gpio_intr = 0;
 763     s->gpio_mask = 0;
 764     s->gpio_config = 0;
 765     s->dma_intr = 0;
 766     s->dma_mask = 0;
 767     s->dma_map = 0;
 768     s->dma_config = 0;
 769     s->ep0_config = 0;
 770     s->wkup_mask = 0;
 771     s->pullup[0] = s->pullup[1] = 0;
 772     s->control_config = 0;
 773     for (i = 0; i < 15; i++) {
 774         s->rx_config[i] = s->tx_config[i] = 0;
 775     }
 776     musb_reset(s->musb);
 777 }
 778
 779 static int tusb6010_init(SysBusDevice *sbd)
 780 {
 781     DeviceState *dev = DEVICE(sbd);
 782     TUSBState *s = TUSB(dev);
 783
 784     s->otg_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_otg_tick, s);
 785     s->pwr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_power_tick, s);
 786     memory_region_init_io(&s->iomem[1], OBJECT(s), &tusb_async_ops, s,
 787                           "tusb-async", UINT32_MAX);
 788     sysbus_init_mmio(sbd, &s->iomem[0]);
 789     sysbus_init_mmio(sbd, &s->iomem[1]);
 790     sysbus_init_irq(sbd, &s->irq);
 791     qdev_init_gpio_in(dev, tusb6010_irq, musb_irq_max + 1);
 792     s->musb = musb_init(dev, 1);
 793     return 0;
 794 }
 795
 796 static void tusb6010_class_init(ObjectClass *klass, void *data)
 797 {
 798     DeviceClass *dc = DEVICE_CLASS(klass);
 799     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 800
 801     k->init = tusb6010_init;
 802     dc->reset = tusb6010_reset;
 803 }
 804
 805 static const TypeInfo tusb6010_info = {
 806     .name          = TYPE_TUSB6010,
 807     .parent        = TYPE_SYS_BUS_DEVICE,
 808     .instance_size = sizeof(TUSBState),
 809     .class_init    = tusb6010_class_init,
 810 };
 811
 812 static void tusb6010_register_types(void)
 813 {
 814     type_register_static(&tusb6010_info);
 815 }
 816
 817 type_init(tusb6010_register_types)