target-i386/cpu-qom.h

   1 /*
   2  * QEMU x86 CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20 #ifndef QEMU_I386_CPU_QOM_H
  21 #define QEMU_I386_CPU_QOM_H
  22
  23 #include "qom/cpu.h"
  24 #include "cpu.h"
  25 #include "qapi/error.h"
  26 #include "qemu/notify.h"
  27
  28 #ifdef TARGET_X86_64
  29 #define TYPE_X86_CPU "x86_64-cpu"
  30 #else
  31 #define TYPE_X86_CPU "i386-cpu"
  32 #endif
  33
  34 #define X86_CPU_CLASS(klass) \
  35     OBJECT_CLASS_CHECK(X86CPUClass, (klass), TYPE_X86_CPU)
  36 #define X86_CPU(obj) \
  37     OBJECT_CHECK(X86CPU, (obj), TYPE_X86_CPU)
  38 #define X86_CPU_GET_CLASS(obj) \
  39     OBJECT_GET_CLASS(X86CPUClass, (obj), TYPE_X86_CPU)
  40
  41 /**
  42  * X86CPUDefinition:
  43  *
  44  * CPU model definition data that was not converted to QOM per-subclass
  45  * property defaults yet.
  46  */
  47 typedef struct X86CPUDefinition X86CPUDefinition;
  48
  49 /**
  50  * X86CPUClass:
  51  * @cpu_def: CPU model definition
  52  * @kvm_required: Whether CPU model requires KVM to be enabled.
  53  * @parent_realize: The parent class' realize handler.
  54  * @parent_reset: The parent class' reset handler.
  55  *
  56  * An x86 CPU model or family.
  57  */
  58 typedef struct X86CPUClass {
  59     /*< private >*/
  60     CPUClass parent_class;
  61     /*< public >*/
  62
  63     /* Should be eventually replaced by subclass-specific property defaults. */
  64     X86CPUDefinition *cpu_def;
  65
  66     bool kvm_required;
  67
  68     DeviceRealize parent_realize;
  69     void (*parent_reset)(CPUState *cpu);
  70 } X86CPUClass;
  71
  72 /**
  73  * X86CPU:
  74  * @env: #CPUX86State
  75  * @migratable: If set, only migratable flags will be accepted when "enforce"
  76  * mode is used, and only migratable flags will be included in the "host"
  77  * CPU model.
  78  *
  79  * An x86 CPU.
  80  */
  81 typedef struct X86CPU {
  82     /*< private >*/
  83     CPUState parent_obj;
  84     /*< public >*/
  85
  86     CPUX86State env;
  87
  88     bool hyperv_vapic;
  89     bool hyperv_relaxed_timing;
  90     int hyperv_spinlock_attempts;
  91     char *hyperv_vendor_id;
  92     bool hyperv_time;
  93     bool hyperv_crash;
  94     bool hyperv_reset;
  95     bool hyperv_vpindex;
  96     bool hyperv_runtime;
  97     bool check_cpuid;
  98     bool enforce_cpuid;
  99     bool expose_kvm;
 100     bool migratable;
 101     bool host_features;
 102     int64_t apic_id;
 103
 104     /* if true the CPUID code directly forward host cache leaves to the guest */
 105     bool cache_info_passthrough;
 106
 107     /* Features that were filtered out because of missing host capabilities */
 108     uint32_t filtered_features[FEATURE_WORDS];
 109
 110     /* Enable PMU CPUID bits. This can't be enabled by default yet because
 111      * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
 112      * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
 113      * capabilities) directly to the guest.
 114      */
 115     bool enable_pmu;
 116
 117     /* in order to simplify APIC support, we leave this pointer to the
 118        user */
 119     struct DeviceState *apic_state;
 120     struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
 121     Notifier machine_done;
 122 } X86CPU;
 123
 124 static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
 125 {
 126     return container_of(env, X86CPU, env);
 127 }
 128
 129 #define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
 130
 131 #define ENV_OFFSET offsetof(X86CPU, env)
 132
 133 #ifndef CONFIG_USER_ONLY
 134 extern struct VMStateDescription vmstate_x86_cpu;
 135 #endif
 136
 137 /**
 138  * x86_cpu_do_interrupt:
 139  * @cpu: vCPU the interrupt is to be handled by.
 140  */
 141 void x86_cpu_do_interrupt(CPUState *cpu);
 142 bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
 143
 144 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
 145                              int cpuid, void *opaque);
 146 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
 147                              int cpuid, void *opaque);
 148 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
 149                                  void *opaque);
 150 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
 151                                  void *opaque);
 152
 153 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
 154                                 Error **errp);
 155
 156 void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
 157                         int flags);
 158
 159 hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 160
 161 int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 162 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 163
 164 void x86_cpu_exec_enter(CPUState *cpu);
 165 void x86_cpu_exec_exit(CPUState *cpu);
 166
 167 #endif