?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
target/riscv: Set the opcode in DisasContext
[qemu/kevin.git] / target / riscv / translate.c
blob9e4f9c334207847961b0a7002f584ea7b2792b2b
1 /*
2 * RISC-V emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include "qemu/osdep.h"
20 #include "qemu/log.h"
21 #include "cpu.h"
22 #include "tcg/tcg-op.h"
23 #include "disas/disas.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/exec-all.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
28
29 #include "exec/translator.h"
30 #include "exec/log.h"
31
32 #include "instmap.h"
33 #include "internals.h"
34
35 /* global register indices */
36 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
37 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
38 static TCGv load_res;
39 static TCGv load_val;
40 /* globals for PM CSRs */
41 static TCGv pm_mask[4];
42 static TCGv pm_base[4];
43
44 #include "exec/gen-icount.h"
45
46 /*
47 * If an operation is being performed on less than TARGET_LONG_BITS,
48 * it may require the inputs to be sign- or zero-extended; which will
49 * depend on the exact operation being performed.
50 */
51 typedef enum {
52 EXT_NONE,
53 EXT_SIGN,
54 EXT_ZERO,
55 } DisasExtend;
56
57 typedef struct DisasContext {
58 DisasContextBase base;
59 /* pc_succ_insn points to the instruction following base.pc_next */
60 target_ulong pc_succ_insn;
61 target_ulong priv_ver;
62 RISCVMXL misa_mxl_max;
63 RISCVMXL xl;
64 uint32_t misa_ext;
65 uint32_t opcode;
66 uint32_t mstatus_fs;
67 uint32_t mstatus_vs;
68 uint32_t mstatus_hs_fs;
69 uint32_t mstatus_hs_vs;
70 uint32_t mem_idx;
71 /* Remember the rounding mode encoded in the previous fp instruction,
72 which we have already installed into env->fp_status. Or -1 for
73 no previous fp instruction. Note that we exit the TB when writing
74 to any system register, which includes CSR_FRM, so we do not have
75 to reset this known value. */
76 int frm;
77 RISCVMXL ol;
78 bool virt_enabled;
79 bool ext_ifencei;
80 bool ext_zfh;
81 bool ext_zfhmin;
82 bool hlsx;
83 /* vector extension */
84 bool vill;
85 /*
86 * Encode LMUL to lmul as follows:
87 * LMUL vlmul lmul
88 * 1 000 0
89 * 2 001 1
90 * 4 010 2
91 * 8 011 3
92 * - 100 -
93 * 1/8 101 -3
94 * 1/4 110 -2
95 * 1/2 111 -1
96 */
97 int8_t lmul;
98 uint8_t sew;
99 uint16_t vlen;
100 uint16_t elen;
101 target_ulong vstart;
102 bool vl_eq_vlmax;
103 uint8_t ntemp;
104 CPUState *cs;
105 TCGv zero;
106 /* Space for 3 operands plus 1 extra for address computation. */
107 TCGv temp[4];
108 /* PointerMasking extension */
109 bool pm_enabled;
110 TCGv pm_mask;
111 TCGv pm_base;
112 } DisasContext;
113
114 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
115 {
116 return ctx->misa_ext & ext;
117 }
118
119 #ifdef TARGET_RISCV32
120 #define get_xl(ctx) MXL_RV32
121 #elif defined(CONFIG_USER_ONLY)
122 #define get_xl(ctx) MXL_RV64
123 #else
124 #define get_xl(ctx) ((ctx)->xl)
125 #endif
126
127 /* The word size for this machine mode. */
128 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx)
129 {
130 return 16 << get_xl(ctx);
131 }
132
133 /* The operation length, as opposed to the xlen. */
134 #ifdef TARGET_RISCV32
135 #define get_ol(ctx) MXL_RV32
136 #else
137 #define get_ol(ctx) ((ctx)->ol)
138 #endif
139
140 static inline int get_olen(DisasContext *ctx)
141 {
142 return 16 << get_ol(ctx);
143 }
144
145 /* The maximum register length */
146 #ifdef TARGET_RISCV32
147 #define get_xl_max(ctx) MXL_RV32
148 #else
149 #define get_xl_max(ctx) ((ctx)->misa_mxl_max)
150 #endif
151
152 /*
153 * RISC-V requires NaN-boxing of narrower width floating point values.
154 * This applies when a 32-bit value is assigned to a 64-bit FP register.
155 * For consistency and simplicity, we nanbox results even when the RVD
156 * extension is not present.
157 */
158 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
159 {
160 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
161 }
162
163 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in)
164 {
165 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48));
166 }
167
168 /*
169 * A narrow n-bit operation, where n < FLEN, checks that input operands
170 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
171 * If so, the least-significant bits of the input are used, otherwise the
172 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2).
173 *
174 * Here, the result is always nan-boxed, even the canonical nan.
175 */
176 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in)
177 {
178 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull);
179 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull);
180
181 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
182 tcg_temp_free_i64(t_max);
183 tcg_temp_free_i64(t_nan);
184 }
185
186 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
187 {
188 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull);
189 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull);
190
191 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
192 }
193
194 static void generate_exception(DisasContext *ctx, int excp)
195 {
196 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
197 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
198 ctx->base.is_jmp = DISAS_NORETURN;
199 }
200
201 static void generate_exception_mtval(DisasContext *ctx, int excp)
202 {
203 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
204 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
205 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
206 ctx->base.is_jmp = DISAS_NORETURN;
207 }
208
209 static void gen_exception_illegal(DisasContext *ctx)
210 {
211 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
212 }
213
214 static void gen_exception_inst_addr_mis(DisasContext *ctx)
215 {
216 generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS);
217 }
218
219 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
220 {
221 if (translator_use_goto_tb(&ctx->base, dest)) {
222 tcg_gen_goto_tb(n);
223 tcg_gen_movi_tl(cpu_pc, dest);
224 tcg_gen_exit_tb(ctx->base.tb, n);
225 } else {
226 tcg_gen_movi_tl(cpu_pc, dest);
227 tcg_gen_lookup_and_goto_ptr();
228 }
229 }
230
231 /*
232 * Wrappers for getting reg values.
233 *
234 * The $zero register does not have cpu_gpr[0] allocated -- we supply the
235 * constant zero as a source, and an uninitialized sink as destination.
236 *
237 * Further, we may provide an extension for word operations.
238 */
239 static TCGv temp_new(DisasContext *ctx)
240 {
241 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
242 return ctx->temp[ctx->ntemp++] = tcg_temp_new();
243 }
244
245 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
246 {
247 TCGv t;
248
249 if (reg_num == 0) {
250 return ctx->zero;
251 }
252
253 switch (get_ol(ctx)) {
254 case MXL_RV32:
255 switch (ext) {
256 case EXT_NONE:
257 break;
258 case EXT_SIGN:
259 t = temp_new(ctx);
260 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
261 return t;
262 case EXT_ZERO:
263 t = temp_new(ctx);
264 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
265 return t;
266 default:
267 g_assert_not_reached();
268 }
269 break;
270 case MXL_RV64:
271 case MXL_RV128:
272 break;
273 default:
274 g_assert_not_reached();
275 }
276 return cpu_gpr[reg_num];
277 }
278
279 static TCGv get_gprh(DisasContext *ctx, int reg_num)
280 {
281 assert(get_xl(ctx) == MXL_RV128);
282 if (reg_num == 0) {
283 return ctx->zero;
284 }
285 return cpu_gprh[reg_num];
286 }
287
288 static TCGv dest_gpr(DisasContext *ctx, int reg_num)
289 {
290 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) {
291 return temp_new(ctx);
292 }
293 return cpu_gpr[reg_num];
294 }
295
296 static TCGv dest_gprh(DisasContext *ctx, int reg_num)
297 {
298 if (reg_num == 0) {
299 return temp_new(ctx);
300 }
301 return cpu_gprh[reg_num];
302 }
303
304 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
305 {
306 if (reg_num != 0) {
307 switch (get_ol(ctx)) {
308 case MXL_RV32:
309 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
310 break;
311 case MXL_RV64:
312 case MXL_RV128:
313 tcg_gen_mov_tl(cpu_gpr[reg_num], t);
314 break;
315 default:
316 g_assert_not_reached();
317 }
318
319 if (get_xl_max(ctx) == MXL_RV128) {
320 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63);
321 }
322 }
323 }
324
325 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm)
326 {
327 if (reg_num != 0) {
328 switch (get_ol(ctx)) {
329 case MXL_RV32:
330 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm);
331 break;
332 case MXL_RV64:
333 case MXL_RV128:
334 tcg_gen_movi_tl(cpu_gpr[reg_num], imm);
335 break;
336 default:
337 g_assert_not_reached();
338 }
339
340 if (get_xl_max(ctx) == MXL_RV128) {
341 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0));
342 }
343 }
344 }
345
346 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh)
347 {
348 assert(get_ol(ctx) == MXL_RV128);
349 if (reg_num != 0) {
350 tcg_gen_mov_tl(cpu_gpr[reg_num], rl);
351 tcg_gen_mov_tl(cpu_gprh[reg_num], rh);
352 }
353 }
354
355 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
356 {
357 target_ulong next_pc;
358
359 /* check misaligned: */
360 next_pc = ctx->base.pc_next + imm;
361 if (!has_ext(ctx, RVC)) {
362 if ((next_pc & 0x3) != 0) {
363 gen_exception_inst_addr_mis(ctx);
364 return;
365 }
366 }
367 if (rd != 0) {
368 tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
369 }
370
371 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */
372 ctx->base.is_jmp = DISAS_NORETURN;
373 }
374
375 /*
376 * Generates address adjustment for PointerMasking
377 */
378 static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
379 {
380 TCGv temp;
381 if (!s->pm_enabled) {
382 /* Load unmodified address */
383 return src;
384 } else {
385 temp = temp_new(s);
386 tcg_gen_andc_tl(temp, src, s->pm_mask);
387 tcg_gen_or_tl(temp, temp, s->pm_base);
388 return temp;
389 }
390 }
391
392 #ifndef CONFIG_USER_ONLY
393 /* The states of mstatus_fs are:
394 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
395 * We will have already diagnosed disabled state,
396 * and need to turn initial/clean into dirty.
397 */
398 static void mark_fs_dirty(DisasContext *ctx)
399 {
400 TCGv tmp;
401
402 if (ctx->mstatus_fs != MSTATUS_FS) {
403 /* Remember the state change for the rest of the TB. */
404 ctx->mstatus_fs = MSTATUS_FS;
405
406 tmp = tcg_temp_new();
407 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
408 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
409 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
410 tcg_temp_free(tmp);
411 }
412
413 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) {
414 /* Remember the stage change for the rest of the TB. */
415 ctx->mstatus_hs_fs = MSTATUS_FS;
416
417 tmp = tcg_temp_new();
418 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
419 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
420 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
421 tcg_temp_free(tmp);
422 }
423 }
424 #else
425 static inline void mark_fs_dirty(DisasContext *ctx) { }
426 #endif
427
428 #ifndef CONFIG_USER_ONLY
429 /* The states of mstatus_vs are:
430 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
431 * We will have already diagnosed disabled state,
432 * and need to turn initial/clean into dirty.
433 */
434 static void mark_vs_dirty(DisasContext *ctx)
435 {
436 TCGv tmp;
437
438 if (ctx->mstatus_vs != MSTATUS_VS) {
439 /* Remember the state change for the rest of the TB. */
440 ctx->mstatus_vs = MSTATUS_VS;
441
442 tmp = tcg_temp_new();
443 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
444 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
445 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
446 tcg_temp_free(tmp);
447 }
448
449 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) {
450 /* Remember the stage change for the rest of the TB. */
451 ctx->mstatus_hs_vs = MSTATUS_VS;
452
453 tmp = tcg_temp_new();
454 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
455 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
456 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
457 tcg_temp_free(tmp);
458 }
459 }
460 #else
461 static inline void mark_vs_dirty(DisasContext *ctx) { }
462 #endif
463
464 static void gen_set_rm(DisasContext *ctx, int rm)
465 {
466 if (ctx->frm == rm) {
467 return;
468 }
469 ctx->frm = rm;
470
471 if (rm == RISCV_FRM_ROD) {
472 gen_helper_set_rod_rounding_mode(cpu_env);
473 return;
474 }
475
476 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm));
477 }
478
479 static int ex_plus_1(DisasContext *ctx, int nf)
480 {
481 return nf + 1;
482 }
483
484 #define EX_SH(amount) \
485 static int ex_shift_##amount(DisasContext *ctx, int imm) \
486 { \
487 return imm << amount; \
488 }
489 EX_SH(1)
490 EX_SH(2)
491 EX_SH(3)
492 EX_SH(4)
493 EX_SH(12)
494
495 #define REQUIRE_EXT(ctx, ext) do { \
496 if (!has_ext(ctx, ext)) { \
497 return false; \
498 } \
499 } while (0)
500
501 #define REQUIRE_32BIT(ctx) do { \
502 if (get_xl(ctx) != MXL_RV32) { \
503 return false; \
504 } \
505 } while (0)
506
507 #define REQUIRE_64BIT(ctx) do { \
508 if (get_xl(ctx) != MXL_RV64) { \
509 return false; \
510 } \
511 } while (0)
512
513 #define REQUIRE_128BIT(ctx) do { \
514 if (get_xl(ctx) != MXL_RV128) { \
515 return false; \
516 } \
517 } while (0)
518
519 #define REQUIRE_64_OR_128BIT(ctx) do { \
520 if (get_xl(ctx) == MXL_RV32) { \
521 return false; \
522 } \
523 } while (0)
524
525 static int ex_rvc_register(DisasContext *ctx, int reg)
526 {
527 return 8 + reg;
528 }
529
530 static int ex_rvc_shifti(DisasContext *ctx, int imm)
531 {
532 /* For RV128 a shamt of 0 means a shift by 64. */
533 return imm ? imm : 64;
534 }
535
536 /* Include the auto-generated decoder for 32 bit insn */
537 #include "decode-insn32.c.inc"
538
539 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a,
540 void (*func)(TCGv, TCGv, target_long))
541 {
542 TCGv dest = dest_gpr(ctx, a->rd);
543 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
544
545 func(dest, src1, a->imm);
546
547 if (get_xl(ctx) == MXL_RV128) {
548 TCGv src1h = get_gprh(ctx, a->rs1);
549 TCGv desth = dest_gprh(ctx, a->rd);
550
551 func(desth, src1h, -(a->imm < 0));
552 gen_set_gpr128(ctx, a->rd, dest, desth);
553 } else {
554 gen_set_gpr(ctx, a->rd, dest);
555 }
556
557 return true;
558 }
559
560 static bool gen_logic(DisasContext *ctx, arg_r *a,
561 void (*func)(TCGv, TCGv, TCGv))
562 {
563 TCGv dest = dest_gpr(ctx, a->rd);
564 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
565 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
566
567 func(dest, src1, src2);
568
569 if (get_xl(ctx) == MXL_RV128) {
570 TCGv src1h = get_gprh(ctx, a->rs1);
571 TCGv src2h = get_gprh(ctx, a->rs2);
572 TCGv desth = dest_gprh(ctx, a->rd);
573
574 func(desth, src1h, src2h);
575 gen_set_gpr128(ctx, a->rd, dest, desth);
576 } else {
577 gen_set_gpr(ctx, a->rd, dest);
578 }
579
580 return true;
581 }
582
583 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
584 void (*func)(TCGv, TCGv, target_long),
585 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long))
586 {
587 TCGv dest = dest_gpr(ctx, a->rd);
588 TCGv src1 = get_gpr(ctx, a->rs1, ext);
589
590 if (get_ol(ctx) < MXL_RV128) {
591 func(dest, src1, a->imm);
592 gen_set_gpr(ctx, a->rd, dest);
593 } else {
594 if (f128 == NULL) {
595 return false;
596 }
597
598 TCGv src1h = get_gprh(ctx, a->rs1);
599 TCGv desth = dest_gprh(ctx, a->rd);
600
601 f128(dest, desth, src1, src1h, a->imm);
602 gen_set_gpr128(ctx, a->rd, dest, desth);
603 }
604 return true;
605 }
606
607 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext,
608 void (*func)(TCGv, TCGv, TCGv),
609 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv))
610 {
611 TCGv dest = dest_gpr(ctx, a->rd);
612 TCGv src1 = get_gpr(ctx, a->rs1, ext);
613 TCGv src2 = tcg_constant_tl(a->imm);
614
615 if (get_ol(ctx) < MXL_RV128) {
616 func(dest, src1, src2);
617 gen_set_gpr(ctx, a->rd, dest);
618 } else {
619 if (f128 == NULL) {
620 return false;
621 }
622
623 TCGv src1h = get_gprh(ctx, a->rs1);
624 TCGv src2h = tcg_constant_tl(-(a->imm < 0));
625 TCGv desth = dest_gprh(ctx, a->rd);
626
627 f128(dest, desth, src1, src1h, src2, src2h);
628 gen_set_gpr128(ctx, a->rd, dest, desth);
629 }
630 return true;
631 }
632
633 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
634 void (*func)(TCGv, TCGv, TCGv),
635 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv))
636 {
637 TCGv dest = dest_gpr(ctx, a->rd);
638 TCGv src1 = get_gpr(ctx, a->rs1, ext);
639 TCGv src2 = get_gpr(ctx, a->rs2, ext);
640
641 if (get_ol(ctx) < MXL_RV128) {
642 func(dest, src1, src2);
643 gen_set_gpr(ctx, a->rd, dest);
644 } else {
645 if (f128 == NULL) {
646 return false;
647 }
648
649 TCGv src1h = get_gprh(ctx, a->rs1);
650 TCGv src2h = get_gprh(ctx, a->rs2);
651 TCGv desth = dest_gprh(ctx, a->rd);
652
653 f128(dest, desth, src1, src1h, src2, src2h);
654 gen_set_gpr128(ctx, a->rd, dest, desth);
655 }
656 return true;
657 }
658
659 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext,
660 void (*f_tl)(TCGv, TCGv, TCGv),
661 void (*f_32)(TCGv, TCGv, TCGv),
662 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv))
663 {
664 int olen = get_olen(ctx);
665
666 if (olen != TARGET_LONG_BITS) {
667 if (olen == 32) {
668 f_tl = f_32;
669 } else if (olen != 128) {
670 g_assert_not_reached();
671 }
672 }
673 return gen_arith(ctx, a, ext, f_tl, f_128);
674 }
675
676 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
677 void (*func)(TCGv, TCGv, target_long),
678 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long))
679 {
680 TCGv dest, src1;
681 int max_len = get_olen(ctx);
682
683 if (a->shamt >= max_len) {
684 return false;
685 }
686
687 dest = dest_gpr(ctx, a->rd);
688 src1 = get_gpr(ctx, a->rs1, ext);
689
690 if (max_len < 128) {
691 func(dest, src1, a->shamt);
692 gen_set_gpr(ctx, a->rd, dest);
693 } else {
694 TCGv src1h = get_gprh(ctx, a->rs1);
695 TCGv desth = dest_gprh(ctx, a->rd);
696
697 if (f128 == NULL) {
698 return false;
699 }
700 f128(dest, desth, src1, src1h, a->shamt);
701 gen_set_gpr128(ctx, a->rd, dest, desth);
702 }
703 return true;
704 }
705
706 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a,
707 DisasExtend ext,
708 void (*f_tl)(TCGv, TCGv, target_long),
709 void (*f_32)(TCGv, TCGv, target_long),
710 void (*f_128)(TCGv, TCGv, TCGv, TCGv,
711 target_long))
712 {
713 int olen = get_olen(ctx);
714 if (olen != TARGET_LONG_BITS) {
715 if (olen == 32) {
716 f_tl = f_32;
717 } else if (olen != 128) {
718 g_assert_not_reached();
719 }
720 }
721 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128);
722 }
723
724 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext,
725 void (*func)(TCGv, TCGv, TCGv))
726 {
727 TCGv dest, src1, src2;
728 int max_len = get_olen(ctx);
729
730 if (a->shamt >= max_len) {
731 return false;
732 }
733
734 dest = dest_gpr(ctx, a->rd);
735 src1 = get_gpr(ctx, a->rs1, ext);
736 src2 = tcg_constant_tl(a->shamt);
737
738 func(dest, src1, src2);
739
740 gen_set_gpr(ctx, a->rd, dest);
741 return true;
742 }
743
744 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
745 void (*func)(TCGv, TCGv, TCGv),
746 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv))
747 {
748 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
749 TCGv ext2 = tcg_temp_new();
750 int max_len = get_olen(ctx);
751
752 tcg_gen_andi_tl(ext2, src2, max_len - 1);
753
754 TCGv dest = dest_gpr(ctx, a->rd);
755 TCGv src1 = get_gpr(ctx, a->rs1, ext);
756
757 if (max_len < 128) {
758 func(dest, src1, ext2);
759 gen_set_gpr(ctx, a->rd, dest);
760 } else {
761 TCGv src1h = get_gprh(ctx, a->rs1);
762 TCGv desth = dest_gprh(ctx, a->rd);
763
764 if (f128 == NULL) {
765 return false;
766 }
767 f128(dest, desth, src1, src1h, ext2);
768 gen_set_gpr128(ctx, a->rd, dest, desth);
769 }
770 tcg_temp_free(ext2);
771 return true;
772 }
773
774 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext,
775 void (*f_tl)(TCGv, TCGv, TCGv),
776 void (*f_32)(TCGv, TCGv, TCGv),
777 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv))
778 {
779 int olen = get_olen(ctx);
780 if (olen != TARGET_LONG_BITS) {
781 if (olen == 32) {
782 f_tl = f_32;
783 } else if (olen != 128) {
784 g_assert_not_reached();
785 }
786 }
787 return gen_shift(ctx, a, ext, f_tl, f_128);
788 }
789
790 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
791 void (*func)(TCGv, TCGv))
792 {
793 TCGv dest = dest_gpr(ctx, a->rd);
794 TCGv src1 = get_gpr(ctx, a->rs1, ext);
795
796 func(dest, src1);
797
798 gen_set_gpr(ctx, a->rd, dest);
799 return true;
800 }
801
802 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
803 void (*f_tl)(TCGv, TCGv),
804 void (*f_32)(TCGv, TCGv))
805 {
806 int olen = get_olen(ctx);
807
808 if (olen != TARGET_LONG_BITS) {
809 if (olen == 32) {
810 f_tl = f_32;
811 } else {
812 g_assert_not_reached();
813 }
814 }
815 return gen_unary(ctx, a, ext, f_tl);
816 }
817
818 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
819 {
820 DisasContext *ctx = container_of(dcbase, DisasContext, base);
821 CPUState *cpu = ctx->cs;
822 CPURISCVState *env = cpu->env_ptr;
823
824 return cpu_ldl_code(env, pc);
825 }
826
827 /* Include insn module translation function */
828 #include "insn_trans/trans_rvi.c.inc"
829 #include "insn_trans/trans_rvm.c.inc"
830 #include "insn_trans/trans_rva.c.inc"
831 #include "insn_trans/trans_rvf.c.inc"
832 #include "insn_trans/trans_rvd.c.inc"
833 #include "insn_trans/trans_rvh.c.inc"
834 #include "insn_trans/trans_rvv.c.inc"
835 #include "insn_trans/trans_rvb.c.inc"
836 #include "insn_trans/trans_rvzfh.c.inc"
837 #include "insn_trans/trans_privileged.c.inc"
838
839 /* Include the auto-generated decoder for 16 bit insn */
840 #include "decode-insn16.c.inc"
841
842 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
843 {
844 /* check for compressed insn */
845 if (extract16(opcode, 0, 2) != 3) {
846 if (!has_ext(ctx, RVC)) {
847 gen_exception_illegal(ctx);
848 } else {
849 ctx->opcode = opcode;
850 ctx->pc_succ_insn = ctx->base.pc_next + 2;
851 if (!decode_insn16(ctx, opcode)) {
852 gen_exception_illegal(ctx);
853 }
854 }
855 } else {
856 uint32_t opcode32 = opcode;
857 opcode32 = deposit32(opcode32, 16, 16,
858 translator_lduw(env, &ctx->base,
859 ctx->base.pc_next + 2));
860 ctx->opcode = opcode32;
861 ctx->pc_succ_insn = ctx->base.pc_next + 4;
862 if (!decode_insn32(ctx, opcode32)) {
863 gen_exception_illegal(ctx);
864 }
865 }
866 }
867
868 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
869 {
870 DisasContext *ctx = container_of(dcbase, DisasContext, base);
871 CPURISCVState *env = cs->env_ptr;
872 RISCVCPU *cpu = RISCV_CPU(cs);
873 uint32_t tb_flags = ctx->base.tb->flags;
874
875 ctx->pc_succ_insn = ctx->base.pc_first;
876 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
877 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
878 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS;
879 ctx->priv_ver = env->priv_ver;
880 #if !defined(CONFIG_USER_ONLY)
881 if (riscv_has_ext(env, RVH)) {
882 ctx->virt_enabled = riscv_cpu_virt_enabled(env);
883 } else {
884 ctx->virt_enabled = false;
885 }
886 #else
887 ctx->virt_enabled = false;
888 #endif
889 ctx->misa_ext = env->misa_ext;
890 ctx->frm = -1; /* unknown rounding mode */
891 ctx->ext_ifencei = cpu->cfg.ext_ifencei;
892 ctx->ext_zfh = cpu->cfg.ext_zfh;
893 ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
894 ctx->vlen = cpu->cfg.vlen;
895 ctx->elen = cpu->cfg.elen;
896 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
897 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS);
898 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
899 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
900 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
901 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3);
902 ctx->vstart = env->vstart;
903 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
904 ctx->misa_mxl_max = env->misa_mxl_max;
905 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
906 ctx->cs = cs;
907 ctx->ntemp = 0;
908 memset(ctx->temp, 0, sizeof(ctx->temp));
909 ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
910 int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK;
911 ctx->pm_mask = pm_mask[priv];
912 ctx->pm_base = pm_base[priv];
913
914 ctx->zero = tcg_constant_tl(0);
915 }
916
917 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
918 {
919 }
920
921 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
922 {
923 DisasContext *ctx = container_of(dcbase, DisasContext, base);
924
925 tcg_gen_insn_start(ctx->base.pc_next);
926 }
927
928 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
929 {
930 DisasContext *ctx = container_of(dcbase, DisasContext, base);
931 CPURISCVState *env = cpu->env_ptr;
932 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
933
934 ctx->ol = ctx->xl;
935 decode_opc(env, ctx, opcode16);
936 ctx->base.pc_next = ctx->pc_succ_insn;
937
938 for (int i = ctx->ntemp - 1; i >= 0; --i) {
939 tcg_temp_free(ctx->temp[i]);
940 ctx->temp[i] = NULL;
941 }
942 ctx->ntemp = 0;
943
944 if (ctx->base.is_jmp == DISAS_NEXT) {
945 target_ulong page_start;
946
947 page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
948 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) {
949 ctx->base.is_jmp = DISAS_TOO_MANY;
950 }
951 }
952 }
953
954 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
955 {
956 DisasContext *ctx = container_of(dcbase, DisasContext, base);
957
958 switch (ctx->base.is_jmp) {
959 case DISAS_TOO_MANY:
960 gen_goto_tb(ctx, 0, ctx->base.pc_next);
961 break;
962 case DISAS_NORETURN:
963 break;
964 default:
965 g_assert_not_reached();
966 }
967 }
968
969 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
970 {
971 #ifndef CONFIG_USER_ONLY
972 RISCVCPU *rvcpu = RISCV_CPU(cpu);
973 CPURISCVState *env = &rvcpu->env;
974 #endif
975
976 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
977 #ifndef CONFIG_USER_ONLY
978 qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt);
979 #endif
980 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
981 }
982
983 static const TranslatorOps riscv_tr_ops = {
984 .init_disas_context = riscv_tr_init_disas_context,
985 .tb_start = riscv_tr_tb_start,
986 .insn_start = riscv_tr_insn_start,
987 .translate_insn = riscv_tr_translate_insn,
988 .tb_stop = riscv_tr_tb_stop,
989 .disas_log = riscv_tr_disas_log,
990 };
991
992 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
993 {
994 DisasContext ctx;
995
996 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns);
997 }
998
999 void riscv_translate_init(void)
1000 {
1001 int i;
1002
1003 /*
1004 * cpu_gpr[0] is a placeholder for the zero register. Do not use it.
1005 * Use the gen_set_gpr and get_gpr helper functions when accessing regs,
1006 * unless you specifically block reads/writes to reg 0.
1007 */
1008 cpu_gpr[0] = NULL;
1009 cpu_gprh[0] = NULL;
1010
1011 for (i = 1; i < 32; i++) {
1012 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
1013 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
1014 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
1015 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]);
1016 }
1017
1018 for (i = 0; i < 32; i++) {
1019 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
1020 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]);
1021 }
1022
1023 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc");
1024 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl");
1025 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart),
1026 "vstart");
1027 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res),
1028 "load_res");
1029 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
1030 "load_val");
1031 #ifndef CONFIG_USER_ONLY
1032 /* Assign PM CSRs to tcg globals */
1033 pm_mask[PRV_U] =
1034 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask");
1035 pm_base[PRV_U] =
1036 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase");
1037 pm_mask[PRV_S] =
1038 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask");
1039 pm_base[PRV_S] =
1040 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase");
1041 pm_mask[PRV_M] =
1042 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask");
1043 pm_base[PRV_M] =
1044 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase");
1045 #endif
1046 }
Random patches