3 * TI X3130 pci express upstream port switch
5 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
6 * VA Linux Systems Japan K.K.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
23 #include "hw/pci/pci_ids.h"
24 #include "hw/pci/msi.h"
25 #include "hw/pci/pcie.h"
26 #include "hw/pci/pcie_port.h"
27 #include "qemu/module.h"
29 #define PCI_DEVICE_ID_TI_XIO3130U 0x8232 /* upstream port */
30 #define XIO3130_REVISION 0x2
31 #define XIO3130_MSI_OFFSET 0x70
32 #define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT
33 #define XIO3130_MSI_NR_VECTOR 1
34 #define XIO3130_SSVID_OFFSET 0x80
35 #define XIO3130_SSVID_SVID 0
36 #define XIO3130_SSVID_SSID 0
37 #define XIO3130_EXP_OFFSET 0x90
38 #define XIO3130_AER_OFFSET 0x100
40 static void xio3130_upstream_write_config(PCIDevice
*d
, uint32_t address
,
41 uint32_t val
, int len
)
43 pci_bridge_write_config(d
, address
, val
, len
);
44 pcie_cap_flr_write_config(d
, address
, val
, len
);
45 pcie_aer_write_config(d
, address
, val
, len
);
48 static void xio3130_upstream_reset(DeviceState
*qdev
)
50 PCIDevice
*d
= PCI_DEVICE(qdev
);
52 pci_bridge_reset(qdev
);
53 pcie_cap_deverr_reset(d
);
56 static void xio3130_upstream_realize(PCIDevice
*d
, Error
**errp
)
58 PCIEPort
*p
= PCIE_PORT(d
);
61 pci_bridge_initfn(d
, TYPE_PCIE_BUS
);
62 pcie_port_init_reg(d
);
64 rc
= msi_init(d
, XIO3130_MSI_OFFSET
, XIO3130_MSI_NR_VECTOR
,
65 XIO3130_MSI_SUPPORTED_FLAGS
& PCI_MSI_FLAGS_64BIT
,
66 XIO3130_MSI_SUPPORTED_FLAGS
& PCI_MSI_FLAGS_MASKBIT
,
69 assert(rc
== -ENOTSUP
);
73 rc
= pci_bridge_ssvid_init(d
, XIO3130_SSVID_OFFSET
,
74 XIO3130_SSVID_SVID
, XIO3130_SSVID_SSID
,
80 rc
= pcie_cap_init(d
, XIO3130_EXP_OFFSET
, PCI_EXP_TYPE_UPSTREAM
,
86 pcie_cap_deverr_init(d
);
88 rc
= pcie_aer_init(d
, PCI_ERR_VER
, XIO3130_AER_OFFSET
,
89 PCI_ERR_SIZEOF
, errp
);
101 pci_bridge_exitfn(d
);
104 static void xio3130_upstream_exitfn(PCIDevice
*d
)
109 pci_bridge_exitfn(d
);
112 static const VMStateDescription vmstate_xio3130_upstream
= {
113 .name
= "xio3130-express-upstream-port",
114 .priority
= MIG_PRI_PCI_BUS
,
116 .minimum_version_id
= 1,
117 .fields
= (VMStateField
[]) {
118 VMSTATE_PCI_DEVICE(parent_obj
.parent_obj
, PCIEPort
),
119 VMSTATE_STRUCT(parent_obj
.parent_obj
.exp
.aer_log
, PCIEPort
, 0,
120 vmstate_pcie_aer_log
, PCIEAERLog
),
121 VMSTATE_END_OF_LIST()
125 static void xio3130_upstream_class_init(ObjectClass
*klass
, void *data
)
127 DeviceClass
*dc
= DEVICE_CLASS(klass
);
128 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
131 k
->config_write
= xio3130_upstream_write_config
;
132 k
->realize
= xio3130_upstream_realize
;
133 k
->exit
= xio3130_upstream_exitfn
;
134 k
->vendor_id
= PCI_VENDOR_ID_TI
;
135 k
->device_id
= PCI_DEVICE_ID_TI_XIO3130U
;
136 k
->revision
= XIO3130_REVISION
;
137 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
138 dc
->desc
= "TI X3130 Upstream Port of PCI Express Switch";
139 dc
->reset
= xio3130_upstream_reset
;
140 dc
->vmsd
= &vmstate_xio3130_upstream
;
143 static const TypeInfo xio3130_upstream_info
= {
144 .name
= "x3130-upstream",
145 .parent
= TYPE_PCIE_PORT
,
146 .class_init
= xio3130_upstream_class_init
,
147 .interfaces
= (InterfaceInfo
[]) {
148 { INTERFACE_PCIE_DEVICE
},
153 static void xio3130_upstream_register_types(void)
155 type_register_static(&xio3130_upstream_info
);
158 type_init(xio3130_upstream_register_types
)