2 * PXA270-based Intel Mainstone platforms.
5 * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
8 * This code is licensed under the GNU GPL v2.
10 * Contributions after 2012-01-13 are licensed under the terms of the
11 * GNU GPL, version 2 or (at your option) any later version.
14 #include "qemu/osdep.h"
16 #include "hw/sysbus.h"
17 #include "migration/vmstate.h"
18 #include "qemu/module.h"
19 #include "qom/object.h"
21 /* Mainstone FPGA for extern irqs */
22 #define FPGA_GPIO_PIN 0
23 #define MST_NUM_IRQS 16
24 #define MST_LEDDAT1 0x10
25 #define MST_LEDDAT2 0x14
26 #define MST_LEDCTRL 0x40
27 #define MST_GPSWR 0x60
28 #define MST_MSCWR1 0x80
29 #define MST_MSCWR2 0x84
30 #define MST_MSCWR3 0x88
31 #define MST_MSCRD 0x90
32 #define MST_INTMSKENA 0xc0
33 #define MST_INTSETCLR 0xd0
34 #define MST_PCMCIA0 0xe0
35 #define MST_PCMCIA1 0xe4
37 #define MST_PCMCIAx_READY (1 << 10)
38 #define MST_PCMCIAx_nCD (1 << 5)
40 #define MST_PCMCIA_CD0_IRQ 9
41 #define MST_PCMCIA_CD1_IRQ 13
43 #define TYPE_MAINSTONE_FPGA "mainstone-fpga"
44 OBJECT_DECLARE_SIMPLE_TYPE(mst_irq_state
, MAINSTONE_FPGA
)
46 struct mst_irq_state
{
47 SysBusDevice parent_obj
;
69 mst_fpga_set_irq(void *opaque
, int irq
, int level
)
71 mst_irq_state
*s
= (mst_irq_state
*)opaque
;
72 uint32_t oldint
= s
->intsetclr
& s
->intmskena
;
75 s
->prev_level
|= 1u << irq
;
77 s
->prev_level
&= ~(1u << irq
);
80 case MST_PCMCIA_CD0_IRQ
:
82 s
->pcmcia0
&= ~MST_PCMCIAx_nCD
;
84 s
->pcmcia0
|= MST_PCMCIAx_nCD
;
86 case MST_PCMCIA_CD1_IRQ
:
88 s
->pcmcia1
&= ~MST_PCMCIAx_nCD
;
90 s
->pcmcia1
|= MST_PCMCIAx_nCD
;
94 if ((s
->intmskena
& (1u << irq
)) && level
)
95 s
->intsetclr
|= 1u << irq
;
97 if (oldint
!= (s
->intsetclr
& s
->intmskena
))
98 qemu_set_irq(s
->parent
, s
->intsetclr
& s
->intmskena
);
103 mst_fpga_readb(void *opaque
, hwaddr addr
, unsigned size
)
105 mst_irq_state
*s
= (mst_irq_state
*) opaque
;
133 printf("Mainstone - mst_fpga_readb: Bad register offset "
134 "0x" HWADDR_FMT_plx
"\n", addr
);
140 mst_fpga_writeb(void *opaque
, hwaddr addr
, uint64_t value
,
143 mst_irq_state
*s
= (mst_irq_state
*) opaque
;
171 case MST_INTMSKENA
: /* Mask interrupt */
172 s
->intmskena
= (value
& 0xFEEFF);
173 qemu_set_irq(s
->parent
, s
->intsetclr
& s
->intmskena
);
175 case MST_INTSETCLR
: /* clear or set interrupt */
176 s
->intsetclr
= (value
& 0xFEEFF);
177 qemu_set_irq(s
->parent
, s
->intsetclr
& s
->intmskena
);
179 /* For PCMCIAx allow the to change only power and reset */
181 s
->pcmcia0
= (value
& 0x1f) | (s
->pcmcia0
& ~0x1f);
184 s
->pcmcia1
= (value
& 0x1f) | (s
->pcmcia1
& ~0x1f);
187 printf("Mainstone - mst_fpga_writeb: Bad register offset "
188 "0x" HWADDR_FMT_plx
"\n", addr
);
192 static const MemoryRegionOps mst_fpga_ops
= {
193 .read
= mst_fpga_readb
,
194 .write
= mst_fpga_writeb
,
195 .endianness
= DEVICE_NATIVE_ENDIAN
,
198 static int mst_fpga_post_load(void *opaque
, int version_id
)
200 mst_irq_state
*s
= (mst_irq_state
*) opaque
;
202 qemu_set_irq(s
->parent
, s
->intsetclr
& s
->intmskena
);
206 static void mst_fpga_init(Object
*obj
)
208 DeviceState
*dev
= DEVICE(obj
);
209 mst_irq_state
*s
= MAINSTONE_FPGA(obj
);
210 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
212 s
->pcmcia0
= MST_PCMCIAx_READY
| MST_PCMCIAx_nCD
;
213 s
->pcmcia1
= MST_PCMCIAx_READY
| MST_PCMCIAx_nCD
;
215 sysbus_init_irq(sbd
, &s
->parent
);
217 /* alloc the external 16 irqs */
218 qdev_init_gpio_in(dev
, mst_fpga_set_irq
, MST_NUM_IRQS
);
220 memory_region_init_io(&s
->iomem
, obj
, &mst_fpga_ops
, s
,
222 sysbus_init_mmio(sbd
, &s
->iomem
);
225 static const VMStateDescription vmstate_mst_fpga_regs
= {
226 .name
= "mainstone_fpga",
228 .minimum_version_id
= 0,
229 .post_load
= mst_fpga_post_load
,
230 .fields
= (const VMStateField
[]) {
231 VMSTATE_UINT32(prev_level
, mst_irq_state
),
232 VMSTATE_UINT32(leddat1
, mst_irq_state
),
233 VMSTATE_UINT32(leddat2
, mst_irq_state
),
234 VMSTATE_UINT32(ledctrl
, mst_irq_state
),
235 VMSTATE_UINT32(gpswr
, mst_irq_state
),
236 VMSTATE_UINT32(mscwr1
, mst_irq_state
),
237 VMSTATE_UINT32(mscwr2
, mst_irq_state
),
238 VMSTATE_UINT32(mscwr3
, mst_irq_state
),
239 VMSTATE_UINT32(mscrd
, mst_irq_state
),
240 VMSTATE_UINT32(intmskena
, mst_irq_state
),
241 VMSTATE_UINT32(intsetclr
, mst_irq_state
),
242 VMSTATE_UINT32(pcmcia0
, mst_irq_state
),
243 VMSTATE_UINT32(pcmcia1
, mst_irq_state
),
244 VMSTATE_END_OF_LIST(),
248 static void mst_fpga_class_init(ObjectClass
*klass
, void *data
)
250 DeviceClass
*dc
= DEVICE_CLASS(klass
);
252 dc
->desc
= "Mainstone II FPGA";
253 dc
->vmsd
= &vmstate_mst_fpga_regs
;
256 static const TypeInfo mst_fpga_info
= {
257 .name
= TYPE_MAINSTONE_FPGA
,
258 .parent
= TYPE_SYS_BUS_DEVICE
,
259 .instance_size
= sizeof(mst_irq_state
),
260 .instance_init
= mst_fpga_init
,
261 .class_init
= mst_fpga_class_init
,
264 static void mst_fpga_register_types(void)
266 type_register_static(&mst_fpga_info
);
269 type_init(mst_fpga_register_types
)