2 * ARM IoTKit system control element
4 * Copyright (c) 2018 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
13 * This is a model of the "system control element" which is part of the
14 * Arm IoTKit and documented in
15 * https://developer.arm.com/documentation/ecm0601256/latest
16 * Specifically, it implements the "system control register" blocks.
19 #include "qemu/osdep.h"
20 #include "qemu/bitops.h"
22 #include "qemu/module.h"
23 #include "sysemu/runstate.h"
25 #include "qapi/error.h"
26 #include "hw/sysbus.h"
27 #include "migration/vmstate.h"
28 #include "hw/registerfields.h"
29 #include "hw/misc/iotkit-sysctl.h"
30 #include "hw/qdev-properties.h"
31 #include "hw/arm/armsse-version.h"
32 #include "target/arm/arm-powerctl.h"
34 REG32(SECDBGSTAT
, 0x0)
39 REG32(SYSCLK_DIV
, 0x14)
40 REG32(CLOCK_FORCE
, 0x18)
41 REG32(RESET_SYNDROME
, 0x100)
42 REG32(RESET_MASK
, 0x104)
44 FIELD(SWRESET
, SWRESETREQ
, 9, 1)
46 REG32(INITSVTOR0
, 0x110)
47 FIELD(INITSVTOR0
, LOCK
, 0, 1)
48 FIELD(INITSVTOR0
, VTOR
, 7, 25)
49 REG32(INITSVTOR1
, 0x114)
51 REG32(NMI_ENABLE
, 0x11c) /* BUSWAIT in IoTKit */
55 FIELD(PWRCTRL
, PPU_ACCESS_UNLOCK
, 0, 1)
56 FIELD(PWRCTRL
, PPU_ACCESS_FILTER
, 1, 1)
57 REG32(PDCM_PD_SYS_SENSE
, 0x200)
58 REG32(PDCM_PD_CPU0_SENSE
, 0x204)
59 REG32(PDCM_PD_SRAM0_SENSE
, 0x20c)
60 REG32(PDCM_PD_SRAM1_SENSE
, 0x210)
61 REG32(PDCM_PD_SRAM2_SENSE
, 0x214) /* PDCM_PD_VMR0_SENSE on SSE300 */
62 REG32(PDCM_PD_SRAM3_SENSE
, 0x218) /* PDCM_PD_VMR1_SENSE on SSE300 */
77 static const int iotkit_sysctl_id
[] = {
78 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
79 0x54, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
80 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
83 /* Also used by the SSE300 */
84 static const int sse200_sysctl_id
[] = {
85 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
86 0x54, 0xb8, 0x1b, 0x00, /* PID0..PID3 */
87 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
91 * Set the initial secure vector table offset address for the core.
92 * This will take effect when the CPU next resets.
94 static void set_init_vtor(uint64_t cpuid
, uint32_t vtor
)
96 Object
*cpuobj
= OBJECT(arm_get_cpu_by_id(cpuid
));
99 if (object_property_find(cpuobj
, "init-svtor")) {
100 object_property_set_uint(cpuobj
, "init-svtor", vtor
, &error_abort
);
105 static uint64_t iotkit_sysctl_read(void *opaque
, hwaddr offset
,
108 IoTKitSysCtl
*s
= IOTKIT_SYSCTL(opaque
);
116 switch (s
->sse_version
) {
124 g_assert_not_reached();
128 switch (s
->sse_version
) {
136 g_assert_not_reached();
140 switch (s
->sse_version
) {
148 g_assert_not_reached();
152 switch (s
->sse_version
) {
160 g_assert_not_reached();
163 case A_RESET_SYNDROME
:
164 r
= s
->reset_syndrome
;
176 switch (s
->sse_version
) {
185 g_assert_not_reached();
189 switch (s
->sse_version
) {
195 /* In SSE300 this is reserved (for INITSVTOR2) */
198 g_assert_not_reached();
202 switch (s
->sse_version
) {
204 /* In IoTKit this is named BUSWAIT but marked reserved, R/O, zero */
211 /* In SSE300 this is reserved (for INITSVTOR3) */
214 g_assert_not_reached();
218 switch (s
->sse_version
) {
224 /* In SSE300 this offset is CPUWAIT */
228 g_assert_not_reached();
232 switch (s
->sse_version
) {
239 /* In SSE300 this offset is NMI_ENABLE */
243 g_assert_not_reached();
247 switch (s
->sse_version
) {
255 g_assert_not_reached();
258 case A_PDCM_PD_SYS_SENSE
:
259 switch (s
->sse_version
) {
264 r
= s
->pdcm_pd_sys_sense
;
267 g_assert_not_reached();
270 case A_PDCM_PD_CPU0_SENSE
:
271 switch (s
->sse_version
) {
276 r
= s
->pdcm_pd_cpu0_sense
;
279 g_assert_not_reached();
282 case A_PDCM_PD_SRAM0_SENSE
:
283 switch (s
->sse_version
) {
287 r
= s
->pdcm_pd_sram0_sense
;
292 g_assert_not_reached();
295 case A_PDCM_PD_SRAM1_SENSE
:
296 switch (s
->sse_version
) {
300 r
= s
->pdcm_pd_sram1_sense
;
305 g_assert_not_reached();
308 case A_PDCM_PD_SRAM2_SENSE
:
309 switch (s
->sse_version
) {
313 r
= s
->pdcm_pd_sram2_sense
;
316 r
= s
->pdcm_pd_vmr0_sense
;
319 g_assert_not_reached();
322 case A_PDCM_PD_SRAM3_SENSE
:
323 switch (s
->sse_version
) {
327 r
= s
->pdcm_pd_sram3_sense
;
330 r
= s
->pdcm_pd_vmr1_sense
;
333 g_assert_not_reached();
336 case A_PID4
... A_CID3
:
337 switch (s
->sse_version
) {
339 r
= iotkit_sysctl_id
[(offset
- A_PID4
) / 4];
343 r
= sse200_sysctl_id
[(offset
- A_PID4
) / 4];
346 g_assert_not_reached();
352 qemu_log_mask(LOG_GUEST_ERROR
,
353 "IoTKit SysCtl read: read of WO offset %x\n",
359 qemu_log_mask(LOG_GUEST_ERROR
,
360 "IoTKit SysCtl read: bad offset %x\n", (int)offset
);
364 trace_iotkit_sysctl_read(offset
, r
, size
);
368 static void cpuwait_write(IoTKitSysCtl
*s
, uint32_t value
)
370 int num_cpus
= (s
->sse_version
== ARMSSE_SSE300
) ? 1 : 2;
373 for (i
= 0; i
< num_cpus
; i
++) {
374 uint32_t mask
= 1 << i
;
375 if ((s
->cpuwait
& mask
) && !(value
& mask
)) {
376 /* Powering up CPU 0 */
377 arm_set_cpu_on_and_reset(i
);
383 static void iotkit_sysctl_write(void *opaque
, hwaddr offset
,
384 uint64_t value
, unsigned size
)
386 IoTKitSysCtl
*s
= IOTKIT_SYSCTL(opaque
);
388 trace_iotkit_sysctl_write(offset
, value
, size
);
391 * Most of the state here has to do with control of reset and
392 * similar kinds of power up -- for instance the guest can ask
393 * what the reason for the last reset was, or forbid reset for
394 * some causes (like the non-secure watchdog). Most of this is
395 * not relevant to QEMU, which doesn't really model anything other
396 * than a full power-on reset.
397 * We just model the registers as reads-as-written.
401 case A_RESET_SYNDROME
:
402 qemu_log_mask(LOG_UNIMP
,
403 "IoTKit SysCtl RESET_SYNDROME unimplemented\n");
404 s
->reset_syndrome
= value
;
407 qemu_log_mask(LOG_UNIMP
, "IoTKit SysCtl RESET_MASK unimplemented\n");
408 s
->reset_mask
= value
;
412 * General retention register, which is only reset by a power-on
413 * reset. Technically this implementation is complete, since
414 * QEMU only supports power-on resets...
419 switch (s
->sse_version
) {
421 /* SSE300 has a LOCK bit which prevents further writes when set */
422 if (s
->initsvtor0
& R_INITSVTOR0_LOCK_MASK
) {
423 qemu_log_mask(LOG_GUEST_ERROR
,
424 "IoTKit INITSVTOR0 write when register locked\n");
427 s
->initsvtor0
= value
;
428 set_init_vtor(0, s
->initsvtor0
& R_INITSVTOR0_VTOR_MASK
);
432 s
->initsvtor0
= value
;
433 set_init_vtor(0, s
->initsvtor0
);
436 g_assert_not_reached();
440 switch (s
->sse_version
) {
443 cpuwait_write(s
, value
);
446 /* In SSE300 this is reserved (for INITSVTOR2) */
449 g_assert_not_reached();
453 switch (s
->sse_version
) {
456 qemu_log_mask(LOG_UNIMP
, "IoTKit SysCtl WICCTRL unimplemented\n");
460 /* In SSE300 this offset is CPUWAIT */
461 cpuwait_write(s
, value
);
464 g_assert_not_reached();
469 qemu_log_mask(LOG_UNIMP
, "IoTKit SysCtl SECDBGSET unimplemented\n");
470 s
->secure_debug
|= value
;
473 /* write-1-to-clear */
474 s
->secure_debug
&= ~value
;
477 /* One w/o bit to request a reset; all other bits reserved */
478 if (value
& R_SWRESET_SWRESETREQ_MASK
) {
479 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
483 switch (s
->sse_version
) {
488 qemu_log_mask(LOG_UNIMP
, "IoTKit SysCtl SCSECCTRL unimplemented\n");
489 s
->scsecctrl
= value
;
492 g_assert_not_reached();
496 switch (s
->sse_version
) {
501 qemu_log_mask(LOG_UNIMP
, "IoTKit SysCtl FCLK_DIV unimplemented\n");
505 g_assert_not_reached();
509 switch (s
->sse_version
) {
514 qemu_log_mask(LOG_UNIMP
, "IoTKit SysCtl SYSCLK_DIV unimplemented\n");
515 s
->sysclk_div
= value
;
518 g_assert_not_reached();
522 switch (s
->sse_version
) {
527 qemu_log_mask(LOG_UNIMP
, "IoTKit SysCtl CLOCK_FORCE unimplemented\n");
528 s
->clock_force
= value
;
531 g_assert_not_reached();
535 switch (s
->sse_version
) {
539 s
->initsvtor1
= value
;
540 set_init_vtor(1, s
->initsvtor1
);
545 g_assert_not_reached();
549 switch (s
->sse_version
) {
553 qemu_log_mask(LOG_UNIMP
, "IoTKit SysCtl EWCTRL unimplemented\n");
557 /* In SSE300 this offset is NMI_ENABLE */
558 qemu_log_mask(LOG_UNIMP
, "IoTKit SysCtl NMI_ENABLE unimplemented\n");
559 s
->nmi_enable
= value
;
562 g_assert_not_reached();
566 switch (s
->sse_version
) {
571 if (!(s
->pwrctrl
& R_PWRCTRL_PPU_ACCESS_UNLOCK_MASK
)) {
572 qemu_log_mask(LOG_GUEST_ERROR
,
573 "IoTKit PWRCTRL write when register locked\n");
579 g_assert_not_reached();
582 case A_PDCM_PD_SYS_SENSE
:
583 switch (s
->sse_version
) {
588 qemu_log_mask(LOG_UNIMP
,
589 "IoTKit SysCtl PDCM_PD_SYS_SENSE unimplemented\n");
590 s
->pdcm_pd_sys_sense
= value
;
593 g_assert_not_reached();
596 case A_PDCM_PD_CPU0_SENSE
:
597 switch (s
->sse_version
) {
602 qemu_log_mask(LOG_UNIMP
,
603 "IoTKit SysCtl PDCM_PD_CPU0_SENSE unimplemented\n");
604 s
->pdcm_pd_cpu0_sense
= value
;
607 g_assert_not_reached();
610 case A_PDCM_PD_SRAM0_SENSE
:
611 switch (s
->sse_version
) {
615 qemu_log_mask(LOG_UNIMP
,
616 "IoTKit SysCtl PDCM_PD_SRAM0_SENSE unimplemented\n");
617 s
->pdcm_pd_sram0_sense
= value
;
622 g_assert_not_reached();
625 case A_PDCM_PD_SRAM1_SENSE
:
626 switch (s
->sse_version
) {
630 qemu_log_mask(LOG_UNIMP
,
631 "IoTKit SysCtl PDCM_PD_SRAM1_SENSE unimplemented\n");
632 s
->pdcm_pd_sram1_sense
= value
;
637 g_assert_not_reached();
640 case A_PDCM_PD_SRAM2_SENSE
:
641 switch (s
->sse_version
) {
645 qemu_log_mask(LOG_UNIMP
,
646 "IoTKit SysCtl PDCM_PD_SRAM2_SENSE unimplemented\n");
647 s
->pdcm_pd_sram2_sense
= value
;
650 qemu_log_mask(LOG_UNIMP
,
651 "IoTKit SysCtl PDCM_PD_VMR0_SENSE unimplemented\n");
652 s
->pdcm_pd_vmr0_sense
= value
;
655 g_assert_not_reached();
658 case A_PDCM_PD_SRAM3_SENSE
:
659 switch (s
->sse_version
) {
663 qemu_log_mask(LOG_UNIMP
,
664 "IoTKit SysCtl PDCM_PD_SRAM3_SENSE unimplemented\n");
665 s
->pdcm_pd_sram3_sense
= value
;
668 qemu_log_mask(LOG_UNIMP
,
669 "IoTKit SysCtl PDCM_PD_VMR1_SENSE unimplemented\n");
670 s
->pdcm_pd_vmr1_sense
= value
;
673 g_assert_not_reached();
677 /* In IoTKit this is BUSWAIT: reserved, R/O, zero */
678 switch (s
->sse_version
) {
682 qemu_log_mask(LOG_UNIMP
, "IoTKit SysCtl NMI_ENABLE unimplemented\n");
683 s
->nmi_enable
= value
;
686 /* In SSE300 this is reserved (for INITSVTOR3) */
689 g_assert_not_reached();
693 case A_PID4
... A_CID3
:
695 qemu_log_mask(LOG_GUEST_ERROR
,
696 "IoTKit SysCtl write: write of RO offset %x\n",
701 qemu_log_mask(LOG_GUEST_ERROR
,
702 "IoTKit SysCtl write: bad offset %x\n", (int)offset
);
707 static const MemoryRegionOps iotkit_sysctl_ops
= {
708 .read
= iotkit_sysctl_read
,
709 .write
= iotkit_sysctl_write
,
710 .endianness
= DEVICE_LITTLE_ENDIAN
,
711 /* byte/halfword accesses are just zero-padded on reads and writes */
712 .impl
.min_access_size
= 4,
713 .impl
.max_access_size
= 4,
714 .valid
.min_access_size
= 1,
715 .valid
.max_access_size
= 4,
718 static void iotkit_sysctl_reset(DeviceState
*dev
)
720 IoTKitSysCtl
*s
= IOTKIT_SYSCTL(dev
);
722 trace_iotkit_sysctl_reset();
724 s
->reset_syndrome
= 1;
727 s
->initsvtor0
= s
->initsvtor0_rst
;
728 s
->initsvtor1
= s
->initsvtor1_rst
;
729 s
->cpuwait
= s
->cpuwait_rst
;
738 s
->pdcm_pd_sys_sense
= 0x7f;
739 s
->pdcm_pd_sram0_sense
= 0;
740 s
->pdcm_pd_sram1_sense
= 0;
741 s
->pdcm_pd_sram2_sense
= 0;
742 s
->pdcm_pd_sram3_sense
= 0;
743 s
->pdcm_pd_cpu0_sense
= 0;
744 s
->pdcm_pd_vmr0_sense
= 0;
745 s
->pdcm_pd_vmr1_sense
= 0;
748 static void iotkit_sysctl_init(Object
*obj
)
750 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
751 IoTKitSysCtl
*s
= IOTKIT_SYSCTL(obj
);
753 memory_region_init_io(&s
->iomem
, obj
, &iotkit_sysctl_ops
,
754 s
, "iotkit-sysctl", 0x1000);
755 sysbus_init_mmio(sbd
, &s
->iomem
);
758 static void iotkit_sysctl_realize(DeviceState
*dev
, Error
**errp
)
760 IoTKitSysCtl
*s
= IOTKIT_SYSCTL(dev
);
762 if (!armsse_version_valid(s
->sse_version
)) {
763 error_setg(errp
, "invalid sse-version value %d", s
->sse_version
);
768 static bool sse300_needed(void *opaque
)
770 IoTKitSysCtl
*s
= IOTKIT_SYSCTL(opaque
);
772 return s
->sse_version
== ARMSSE_SSE300
;
775 static const VMStateDescription iotkit_sysctl_sse300_vmstate
= {
776 .name
= "iotkit-sysctl/sse-300",
778 .minimum_version_id
= 1,
779 .needed
= sse300_needed
,
780 .fields
= (const VMStateField
[]) {
781 VMSTATE_UINT32(pwrctrl
, IoTKitSysCtl
),
782 VMSTATE_UINT32(pdcm_pd_cpu0_sense
, IoTKitSysCtl
),
783 VMSTATE_UINT32(pdcm_pd_vmr0_sense
, IoTKitSysCtl
),
784 VMSTATE_UINT32(pdcm_pd_vmr1_sense
, IoTKitSysCtl
),
785 VMSTATE_END_OF_LIST()
789 static bool sse200_needed(void *opaque
)
791 IoTKitSysCtl
*s
= IOTKIT_SYSCTL(opaque
);
793 return s
->sse_version
!= ARMSSE_IOTKIT
;
796 static const VMStateDescription iotkit_sysctl_sse200_vmstate
= {
797 .name
= "iotkit-sysctl/sse-200",
799 .minimum_version_id
= 1,
800 .needed
= sse200_needed
,
801 .fields
= (const VMStateField
[]) {
802 VMSTATE_UINT32(scsecctrl
, IoTKitSysCtl
),
803 VMSTATE_UINT32(fclk_div
, IoTKitSysCtl
),
804 VMSTATE_UINT32(sysclk_div
, IoTKitSysCtl
),
805 VMSTATE_UINT32(clock_force
, IoTKitSysCtl
),
806 VMSTATE_UINT32(initsvtor1
, IoTKitSysCtl
),
807 VMSTATE_UINT32(nmi_enable
, IoTKitSysCtl
),
808 VMSTATE_UINT32(pdcm_pd_sys_sense
, IoTKitSysCtl
),
809 VMSTATE_UINT32(pdcm_pd_sram0_sense
, IoTKitSysCtl
),
810 VMSTATE_UINT32(pdcm_pd_sram1_sense
, IoTKitSysCtl
),
811 VMSTATE_UINT32(pdcm_pd_sram2_sense
, IoTKitSysCtl
),
812 VMSTATE_UINT32(pdcm_pd_sram3_sense
, IoTKitSysCtl
),
813 VMSTATE_END_OF_LIST()
817 static const VMStateDescription iotkit_sysctl_vmstate
= {
818 .name
= "iotkit-sysctl",
820 .minimum_version_id
= 1,
821 .fields
= (const VMStateField
[]) {
822 VMSTATE_UINT32(secure_debug
, IoTKitSysCtl
),
823 VMSTATE_UINT32(reset_syndrome
, IoTKitSysCtl
),
824 VMSTATE_UINT32(reset_mask
, IoTKitSysCtl
),
825 VMSTATE_UINT32(gretreg
, IoTKitSysCtl
),
826 VMSTATE_UINT32(initsvtor0
, IoTKitSysCtl
),
827 VMSTATE_UINT32(cpuwait
, IoTKitSysCtl
),
828 VMSTATE_UINT32(wicctrl
, IoTKitSysCtl
),
829 VMSTATE_END_OF_LIST()
831 .subsections
= (const VMStateDescription
* const []) {
832 &iotkit_sysctl_sse200_vmstate
,
833 &iotkit_sysctl_sse300_vmstate
,
838 static Property iotkit_sysctl_props
[] = {
839 DEFINE_PROP_UINT32("sse-version", IoTKitSysCtl
, sse_version
, 0),
840 DEFINE_PROP_UINT32("CPUWAIT_RST", IoTKitSysCtl
, cpuwait_rst
, 0),
841 DEFINE_PROP_UINT32("INITSVTOR0_RST", IoTKitSysCtl
, initsvtor0_rst
,
843 DEFINE_PROP_UINT32("INITSVTOR1_RST", IoTKitSysCtl
, initsvtor1_rst
,
845 DEFINE_PROP_END_OF_LIST()
848 static void iotkit_sysctl_class_init(ObjectClass
*klass
, void *data
)
850 DeviceClass
*dc
= DEVICE_CLASS(klass
);
852 dc
->vmsd
= &iotkit_sysctl_vmstate
;
853 dc
->reset
= iotkit_sysctl_reset
;
854 device_class_set_props(dc
, iotkit_sysctl_props
);
855 dc
->realize
= iotkit_sysctl_realize
;
858 static const TypeInfo iotkit_sysctl_info
= {
859 .name
= TYPE_IOTKIT_SYSCTL
,
860 .parent
= TYPE_SYS_BUS_DEVICE
,
861 .instance_size
= sizeof(IoTKitSysCtl
),
862 .instance_init
= iotkit_sysctl_init
,
863 .class_init
= iotkit_sysctl_class_init
,
866 static void iotkit_sysctl_register_types(void)
868 type_register_static(&iotkit_sysctl_info
);
871 type_init(iotkit_sysctl_register_types
);