tcg/tcg.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef TCG_H
  26 #define TCG_H
  27
  28 #include "qemu-common.h"
  29 #include "cpu.h"
  30 #include "exec/tb-context.h"
  31 #include "qemu/bitops.h"
  32 #include "qemu/queue.h"
  33 #include "tcg-mo.h"
  34 #include "tcg-target.h"
  35 #include "qemu/int128.h"
  36
  37 /* XXX: make safe guess about sizes */
  38 #define MAX_OP_PER_INSTR 266
  39
  40 #if HOST_LONG_BITS == 32
  41 #define MAX_OPC_PARAM_PER_ARG 2
  42 #else
  43 #define MAX_OPC_PARAM_PER_ARG 1
  44 #endif
  45 #define MAX_OPC_PARAM_IARGS 6
  46 #define MAX_OPC_PARAM_OARGS 1
  47 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  48
  49 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  50  * and up to 4 + N parameters on 64-bit archs
  51  * (N = number of input arguments + output arguments).  */
  52 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  53
  54 #define CPU_TEMP_BUF_NLONGS 128
  55
  56 /* Default target word size to pointer size.  */
  57 #ifndef TCG_TARGET_REG_BITS
  58 # if UINTPTR_MAX == UINT32_MAX
  59 #  define TCG_TARGET_REG_BITS 32
  60 # elif UINTPTR_MAX == UINT64_MAX
  61 #  define TCG_TARGET_REG_BITS 64
  62 # else
  63 #  error Unknown pointer size for tcg target
  64 # endif
  65 #endif
  66
  67 #if TCG_TARGET_REG_BITS == 32
  68 typedef int32_t tcg_target_long;
  69 typedef uint32_t tcg_target_ulong;
  70 #define TCG_PRIlx PRIx32
  71 #define TCG_PRIld PRId32
  72 #elif TCG_TARGET_REG_BITS == 64
  73 typedef int64_t tcg_target_long;
  74 typedef uint64_t tcg_target_ulong;
  75 #define TCG_PRIlx PRIx64
  76 #define TCG_PRIld PRId64
  77 #else
  78 #error unsupported
  79 #endif
  80
  81 /* Oversized TCG guests make things like MTTCG hard
  82  * as we can't use atomics for cputlb updates.
  83  */
  84 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
  85 #define TCG_OVERSIZED_GUEST 1
  86 #else
  87 #define TCG_OVERSIZED_GUEST 0
  88 #endif
  89
  90 #if TCG_TARGET_NB_REGS <= 32
  91 typedef uint32_t TCGRegSet;
  92 #elif TCG_TARGET_NB_REGS <= 64
  93 typedef uint64_t TCGRegSet;
  94 #else
  95 #error unsupported
  96 #endif
  97
  98 #if TCG_TARGET_REG_BITS == 32
  99 /* Turn some undef macros into false macros.  */
 100 #define TCG_TARGET_HAS_extrl_i64_i32    0
 101 #define TCG_TARGET_HAS_extrh_i64_i32    0
 102 #define TCG_TARGET_HAS_div_i64          0
 103 #define TCG_TARGET_HAS_rem_i64          0
 104 #define TCG_TARGET_HAS_div2_i64         0
 105 #define TCG_TARGET_HAS_rot_i64          0
 106 #define TCG_TARGET_HAS_ext8s_i64        0
 107 #define TCG_TARGET_HAS_ext16s_i64       0
 108 #define TCG_TARGET_HAS_ext32s_i64       0
 109 #define TCG_TARGET_HAS_ext8u_i64        0
 110 #define TCG_TARGET_HAS_ext16u_i64       0
 111 #define TCG_TARGET_HAS_ext32u_i64       0
 112 #define TCG_TARGET_HAS_bswap16_i64      0
 113 #define TCG_TARGET_HAS_bswap32_i64      0
 114 #define TCG_TARGET_HAS_bswap64_i64      0
 115 #define TCG_TARGET_HAS_neg_i64          0
 116 #define TCG_TARGET_HAS_not_i64          0
 117 #define TCG_TARGET_HAS_andc_i64         0
 118 #define TCG_TARGET_HAS_orc_i64          0
 119 #define TCG_TARGET_HAS_eqv_i64          0
 120 #define TCG_TARGET_HAS_nand_i64         0
 121 #define TCG_TARGET_HAS_nor_i64          0
 122 #define TCG_TARGET_HAS_clz_i64          0
 123 #define TCG_TARGET_HAS_ctz_i64          0
 124 #define TCG_TARGET_HAS_ctpop_i64        0
 125 #define TCG_TARGET_HAS_deposit_i64      0
 126 #define TCG_TARGET_HAS_extract_i64      0
 127 #define TCG_TARGET_HAS_sextract_i64     0
 128 #define TCG_TARGET_HAS_movcond_i64      0
 129 #define TCG_TARGET_HAS_add2_i64         0
 130 #define TCG_TARGET_HAS_sub2_i64         0
 131 #define TCG_TARGET_HAS_mulu2_i64        0
 132 #define TCG_TARGET_HAS_muls2_i64        0
 133 #define TCG_TARGET_HAS_muluh_i64        0
 134 #define TCG_TARGET_HAS_mulsh_i64        0
 135 /* Turn some undef macros into true macros.  */
 136 #define TCG_TARGET_HAS_add2_i32         1
 137 #define TCG_TARGET_HAS_sub2_i32         1
 138 #endif
 139
 140 #ifndef TCG_TARGET_deposit_i32_valid
 141 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1
 142 #endif
 143 #ifndef TCG_TARGET_deposit_i64_valid
 144 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1
 145 #endif
 146 #ifndef TCG_TARGET_extract_i32_valid
 147 #define TCG_TARGET_extract_i32_valid(ofs, len) 1
 148 #endif
 149 #ifndef TCG_TARGET_extract_i64_valid
 150 #define TCG_TARGET_extract_i64_valid(ofs, len) 1
 151 #endif
 152
 153 /* Only one of DIV or DIV2 should be defined.  */
 154 #if defined(TCG_TARGET_HAS_div_i32)
 155 #define TCG_TARGET_HAS_div2_i32         0
 156 #elif defined(TCG_TARGET_HAS_div2_i32)
 157 #define TCG_TARGET_HAS_div_i32          0
 158 #define TCG_TARGET_HAS_rem_i32          0
 159 #endif
 160 #if defined(TCG_TARGET_HAS_div_i64)
 161 #define TCG_TARGET_HAS_div2_i64         0
 162 #elif defined(TCG_TARGET_HAS_div2_i64)
 163 #define TCG_TARGET_HAS_div_i64          0
 164 #define TCG_TARGET_HAS_rem_i64          0
 165 #endif
 166
 167 /* For 32-bit targets, some sort of unsigned widening multiply is required.  */
 168 #if TCG_TARGET_REG_BITS == 32 \
 169     && !(defined(TCG_TARGET_HAS_mulu2_i32) \
 170          || defined(TCG_TARGET_HAS_muluh_i32))
 171 # error "Missing unsigned widening multiply"
 172 #endif
 173
 174 #if !defined(TCG_TARGET_HAS_v64) \
 175     && !defined(TCG_TARGET_HAS_v128) \
 176     && !defined(TCG_TARGET_HAS_v256)
 177 #define TCG_TARGET_MAYBE_vec            0
 178 #define TCG_TARGET_HAS_neg_vec          0
 179 #define TCG_TARGET_HAS_not_vec          0
 180 #define TCG_TARGET_HAS_andc_vec         0
 181 #define TCG_TARGET_HAS_orc_vec          0
 182 #define TCG_TARGET_HAS_shi_vec          0
 183 #define TCG_TARGET_HAS_shs_vec          0
 184 #define TCG_TARGET_HAS_shv_vec          0
 185 #define TCG_TARGET_HAS_mul_vec          0
 186 #define TCG_TARGET_HAS_sat_vec          0
 187 #define TCG_TARGET_HAS_minmax_vec       0
 188 #else
 189 #define TCG_TARGET_MAYBE_vec            1
 190 #endif
 191 #ifndef TCG_TARGET_HAS_v64
 192 #define TCG_TARGET_HAS_v64              0
 193 #endif
 194 #ifndef TCG_TARGET_HAS_v128
 195 #define TCG_TARGET_HAS_v128             0
 196 #endif
 197 #ifndef TCG_TARGET_HAS_v256
 198 #define TCG_TARGET_HAS_v256             0
 199 #endif
 200
 201 #ifndef TARGET_INSN_START_EXTRA_WORDS
 202 # define TARGET_INSN_START_WORDS 1
 203 #else
 204 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
 205 #endif
 206
 207 typedef enum TCGOpcode {
 208 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
 209 #include "tcg-opc.h"
 210 #undef DEF
 211     NB_OPS,
 212 } TCGOpcode;
 213
 214 #define tcg_regset_set_reg(d, r)   ((d) |= (TCGRegSet)1 << (r))
 215 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r)))
 216 #define tcg_regset_test_reg(d, r)  (((d) >> (r)) & 1)
 217
 218 #ifndef TCG_TARGET_INSN_UNIT_SIZE
 219 # error "Missing TCG_TARGET_INSN_UNIT_SIZE"
 220 #elif TCG_TARGET_INSN_UNIT_SIZE == 1
 221 typedef uint8_t tcg_insn_unit;
 222 #elif TCG_TARGET_INSN_UNIT_SIZE == 2
 223 typedef uint16_t tcg_insn_unit;
 224 #elif TCG_TARGET_INSN_UNIT_SIZE == 4
 225 typedef uint32_t tcg_insn_unit;
 226 #elif TCG_TARGET_INSN_UNIT_SIZE == 8
 227 typedef uint64_t tcg_insn_unit;
 228 #else
 229 /* The port better have done this.  */
 230 #endif
 231
 232
 233 #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS
 234 # define tcg_debug_assert(X) do { assert(X); } while (0)
 235 #else
 236 # define tcg_debug_assert(X) \
 237     do { if (!(X)) { __builtin_unreachable(); } } while (0)
 238 #endif
 239
 240 typedef struct TCGRelocation {
 241     struct TCGRelocation *next;
 242     int type;
 243     tcg_insn_unit *ptr;
 244     intptr_t addend;
 245 } TCGRelocation;
 246
 247 typedef struct TCGLabel {
 248     unsigned has_value : 1;
 249     unsigned id : 15;
 250     unsigned refs : 16;
 251     union {
 252         uintptr_t value;
 253         tcg_insn_unit *value_ptr;
 254         TCGRelocation *first_reloc;
 255     } u;
 256 } TCGLabel;
 257
 258 typedef struct TCGPool {
 259     struct TCGPool *next;
 260     int size;
 261     uint8_t data[0] __attribute__ ((aligned));
 262 } TCGPool;
 263
 264 #define TCG_POOL_CHUNK_SIZE 32768
 265
 266 #define TCG_MAX_TEMPS 512
 267 #define TCG_MAX_INSNS 512
 268
 269 /* when the size of the arguments of a called function is smaller than
 270    this value, they are statically allocated in the TB stack frame */
 271 #define TCG_STATIC_CALL_ARGS_SIZE 128
 272
 273 typedef enum TCGType {
 274     TCG_TYPE_I32,
 275     TCG_TYPE_I64,
 276
 277     TCG_TYPE_V64,
 278     TCG_TYPE_V128,
 279     TCG_TYPE_V256,
 280
 281     TCG_TYPE_COUNT, /* number of different types */
 282
 283     /* An alias for the size of the host register.  */
 284 #if TCG_TARGET_REG_BITS == 32
 285     TCG_TYPE_REG = TCG_TYPE_I32,
 286 #else
 287     TCG_TYPE_REG = TCG_TYPE_I64,
 288 #endif
 289
 290     /* An alias for the size of the native pointer.  */
 291 #if UINTPTR_MAX == UINT32_MAX
 292     TCG_TYPE_PTR = TCG_TYPE_I32,
 293 #else
 294     TCG_TYPE_PTR = TCG_TYPE_I64,
 295 #endif
 296
 297     /* An alias for the size of the target "long", aka register.  */
 298 #if TARGET_LONG_BITS == 64
 299     TCG_TYPE_TL = TCG_TYPE_I64,
 300 #else
 301     TCG_TYPE_TL = TCG_TYPE_I32,
 302 #endif
 303 } TCGType;
 304
 305 /* Constants for qemu_ld and qemu_st for the Memory Operation field.  */
 306 typedef enum TCGMemOp {
 307     MO_8     = 0,
 308     MO_16    = 1,
 309     MO_32    = 2,
 310     MO_64    = 3,
 311     MO_SIZE  = 3,   /* Mask for the above.  */
 312
 313     MO_SIGN  = 4,   /* Sign-extended, otherwise zero-extended.  */
 314
 315     MO_BSWAP = 8,   /* Host reverse endian.  */
 316 #ifdef HOST_WORDS_BIGENDIAN
 317     MO_LE    = MO_BSWAP,
 318     MO_BE    = 0,
 319 #else
 320     MO_LE    = 0,
 321     MO_BE    = MO_BSWAP,
 322 #endif
 323 #ifdef TARGET_WORDS_BIGENDIAN
 324     MO_TE    = MO_BE,
 325 #else
 326     MO_TE    = MO_LE,
 327 #endif
 328
 329     /* MO_UNALN accesses are never checked for alignment.
 330      * MO_ALIGN accesses will result in a call to the CPU's
 331      * do_unaligned_access hook if the guest address is not aligned.
 332      * The default depends on whether the target CPU defines ALIGNED_ONLY.
 333      *
 334      * Some architectures (e.g. ARMv8) need the address which is aligned
 335      * to a size more than the size of the memory access.
 336      * Some architectures (e.g. SPARCv9) need an address which is aligned,
 337      * but less strictly than the natural alignment.
 338      *
 339      * MO_ALIGN supposes the alignment size is the size of a memory access.
 340      *
 341      * There are three options:
 342      * - unaligned access permitted (MO_UNALN).
 343      * - an alignment to the size of an access (MO_ALIGN);
 344      * - an alignment to a specified size, which may be more or less than
 345      *   the access size (MO_ALIGN_x where 'x' is a size in bytes);
 346      */
 347     MO_ASHIFT = 4,
 348     MO_AMASK = 7 << MO_ASHIFT,
 349 #ifdef ALIGNED_ONLY
 350     MO_ALIGN = 0,
 351     MO_UNALN = MO_AMASK,
 352 #else
 353     MO_ALIGN = MO_AMASK,
 354     MO_UNALN = 0,
 355 #endif
 356     MO_ALIGN_2  = 1 << MO_ASHIFT,
 357     MO_ALIGN_4  = 2 << MO_ASHIFT,
 358     MO_ALIGN_8  = 3 << MO_ASHIFT,
 359     MO_ALIGN_16 = 4 << MO_ASHIFT,
 360     MO_ALIGN_32 = 5 << MO_ASHIFT,
 361     MO_ALIGN_64 = 6 << MO_ASHIFT,
 362
 363     /* Combinations of the above, for ease of use.  */
 364     MO_UB    = MO_8,
 365     MO_UW    = MO_16,
 366     MO_UL    = MO_32,
 367     MO_SB    = MO_SIGN | MO_8,
 368     MO_SW    = MO_SIGN | MO_16,
 369     MO_SL    = MO_SIGN | MO_32,
 370     MO_Q     = MO_64,
 371
 372     MO_LEUW  = MO_LE | MO_UW,
 373     MO_LEUL  = MO_LE | MO_UL,
 374     MO_LESW  = MO_LE | MO_SW,
 375     MO_LESL  = MO_LE | MO_SL,
 376     MO_LEQ   = MO_LE | MO_Q,
 377
 378     MO_BEUW  = MO_BE | MO_UW,
 379     MO_BEUL  = MO_BE | MO_UL,
 380     MO_BESW  = MO_BE | MO_SW,
 381     MO_BESL  = MO_BE | MO_SL,
 382     MO_BEQ   = MO_BE | MO_Q,
 383
 384     MO_TEUW  = MO_TE | MO_UW,
 385     MO_TEUL  = MO_TE | MO_UL,
 386     MO_TESW  = MO_TE | MO_SW,
 387     MO_TESL  = MO_TE | MO_SL,
 388     MO_TEQ   = MO_TE | MO_Q,
 389
 390     MO_SSIZE = MO_SIZE | MO_SIGN,
 391 } TCGMemOp;
 392
 393 /**
 394  * get_alignment_bits
 395  * @memop: TCGMemOp value
 396  *
 397  * Extract the alignment size from the memop.
 398  */
 399 static inline unsigned get_alignment_bits(TCGMemOp memop)
 400 {
 401     unsigned a = memop & MO_AMASK;
 402
 403     if (a == MO_UNALN) {
 404         /* No alignment required.  */
 405         a = 0;
 406     } else if (a == MO_ALIGN) {
 407         /* A natural alignment requirement.  */
 408         a = memop & MO_SIZE;
 409     } else {
 410         /* A specific alignment requirement.  */
 411         a = a >> MO_ASHIFT;
 412     }
 413 #if defined(CONFIG_SOFTMMU)
 414     /* The requested alignment cannot overlap the TLB flags.  */
 415     tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0);
 416 #endif
 417     return a;
 418 }
 419
 420 typedef tcg_target_ulong TCGArg;
 421
 422 /* Define type and accessor macros for TCG variables.
 423
 424    TCG variables are the inputs and outputs of TCG ops, as described
 425    in tcg/README. Target CPU front-end code uses these types to deal
 426    with TCG variables as it emits TCG code via the tcg_gen_* functions.
 427    They come in several flavours:
 428     * TCGv_i32 : 32 bit integer type
 429     * TCGv_i64 : 64 bit integer type
 430     * TCGv_ptr : a host pointer type
 431     * TCGv_vec : a host vector type; the exact size is not exposed
 432                  to the CPU front-end code.
 433     * TCGv : an integer type the same size as target_ulong
 434              (an alias for either TCGv_i32 or TCGv_i64)
 435    The compiler's type checking will complain if you mix them
 436    up and pass the wrong sized TCGv to a function.
 437
 438    Users of tcg_gen_* don't need to know about any of the internal
 439    details of these, and should treat them as opaque types.
 440    You won't be able to look inside them in a debugger either.
 441
 442    Internal implementation details follow:
 443
 444    Note that there is no definition of the structs TCGv_i32_d etc anywhere.
 445    This is deliberate, because the values we store in variables of type
 446    TCGv_i32 are not really pointers-to-structures. They're just small
 447    integers, but keeping them in pointer types like this means that the
 448    compiler will complain if you accidentally pass a TCGv_i32 to a
 449    function which takes a TCGv_i64, and so on. Only the internals of
 450    TCG need to care about the actual contents of the types.  */
 451
 452 typedef struct TCGv_i32_d *TCGv_i32;
 453 typedef struct TCGv_i64_d *TCGv_i64;
 454 typedef struct TCGv_ptr_d *TCGv_ptr;
 455 typedef struct TCGv_vec_d *TCGv_vec;
 456 typedef TCGv_ptr TCGv_env;
 457 #if TARGET_LONG_BITS == 32
 458 #define TCGv TCGv_i32
 459 #elif TARGET_LONG_BITS == 64
 460 #define TCGv TCGv_i64
 461 #else
 462 #error Unhandled TARGET_LONG_BITS value
 463 #endif
 464
 465 /* call flags */
 466 /* Helper does not read globals (either directly or through an exception). It
 467    implies TCG_CALL_NO_WRITE_GLOBALS. */
 468 #define TCG_CALL_NO_READ_GLOBALS    0x0001
 469 /* Helper does not write globals */
 470 #define TCG_CALL_NO_WRITE_GLOBALS   0x0002
 471 /* Helper can be safely suppressed if the return value is not used. */
 472 #define TCG_CALL_NO_SIDE_EFFECTS    0x0004
 473 /* Helper is QEMU_NORETURN.  */
 474 #define TCG_CALL_NO_RETURN          0x0008
 475
 476 /* convenience version of most used call flags */
 477 #define TCG_CALL_NO_RWG         TCG_CALL_NO_READ_GLOBALS
 478 #define TCG_CALL_NO_WG          TCG_CALL_NO_WRITE_GLOBALS
 479 #define TCG_CALL_NO_SE          TCG_CALL_NO_SIDE_EFFECTS
 480 #define TCG_CALL_NO_RWG_SE      (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
 481 #define TCG_CALL_NO_WG_SE       (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
 482
 483 /* Used to align parameters.  See the comment before tcgv_i32_temp.  */
 484 #define TCG_CALL_DUMMY_ARG      ((TCGArg)0)
 485
 486 /* Conditions.  Note that these are laid out for easy manipulation by
 487    the functions below:
 488      bit 0 is used for inverting;
 489      bit 1 is signed,
 490      bit 2 is unsigned,
 491      bit 3 is used with bit 0 for swapping signed/unsigned.  */
 492 typedef enum {
 493     /* non-signed */
 494     TCG_COND_NEVER  = 0 | 0 | 0 | 0,
 495     TCG_COND_ALWAYS = 0 | 0 | 0 | 1,
 496     TCG_COND_EQ     = 8 | 0 | 0 | 0,
 497     TCG_COND_NE     = 8 | 0 | 0 | 1,
 498     /* signed */
 499     TCG_COND_LT     = 0 | 0 | 2 | 0,
 500     TCG_COND_GE     = 0 | 0 | 2 | 1,
 501     TCG_COND_LE     = 8 | 0 | 2 | 0,
 502     TCG_COND_GT     = 8 | 0 | 2 | 1,
 503     /* unsigned */
 504     TCG_COND_LTU    = 0 | 4 | 0 | 0,
 505     TCG_COND_GEU    = 0 | 4 | 0 | 1,
 506     TCG_COND_LEU    = 8 | 4 | 0 | 0,
 507     TCG_COND_GTU    = 8 | 4 | 0 | 1,
 508 } TCGCond;
 509
 510 /* Invert the sense of the comparison.  */
 511 static inline TCGCond tcg_invert_cond(TCGCond c)
 512 {
 513     return (TCGCond)(c ^ 1);
 514 }
 515
 516 /* Swap the operands in a comparison.  */
 517 static inline TCGCond tcg_swap_cond(TCGCond c)
 518 {
 519     return c & 6 ? (TCGCond)(c ^ 9) : c;
 520 }
 521
 522 /* Create an "unsigned" version of a "signed" comparison.  */
 523 static inline TCGCond tcg_unsigned_cond(TCGCond c)
 524 {
 525     return c & 2 ? (TCGCond)(c ^ 6) : c;
 526 }
 527
 528 /* Create a "signed" version of an "unsigned" comparison.  */
 529 static inline TCGCond tcg_signed_cond(TCGCond c)
 530 {
 531     return c & 4 ? (TCGCond)(c ^ 6) : c;
 532 }
 533
 534 /* Must a comparison be considered unsigned?  */
 535 static inline bool is_unsigned_cond(TCGCond c)
 536 {
 537     return (c & 4) != 0;
 538 }
 539
 540 /* Create a "high" version of a double-word comparison.
 541    This removes equality from a LTE or GTE comparison.  */
 542 static inline TCGCond tcg_high_cond(TCGCond c)
 543 {
 544     switch (c) {
 545     case TCG_COND_GE:
 546     case TCG_COND_LE:
 547     case TCG_COND_GEU:
 548     case TCG_COND_LEU:
 549         return (TCGCond)(c ^ 8);
 550     default:
 551         return c;
 552     }
 553 }
 554
 555 typedef enum TCGTempVal {
 556     TEMP_VAL_DEAD,
 557     TEMP_VAL_REG,
 558     TEMP_VAL_MEM,
 559     TEMP_VAL_CONST,
 560 } TCGTempVal;
 561
 562 typedef struct TCGTemp {
 563     TCGReg reg:8;
 564     TCGTempVal val_type:8;
 565     TCGType base_type:8;
 566     TCGType type:8;
 567     unsigned int fixed_reg:1;
 568     unsigned int indirect_reg:1;
 569     unsigned int indirect_base:1;
 570     unsigned int mem_coherent:1;
 571     unsigned int mem_allocated:1;
 572     /* If true, the temp is saved across both basic blocks and
 573        translation blocks.  */
 574     unsigned int temp_global:1;
 575     /* If true, the temp is saved across basic blocks but dead
 576        at the end of translation blocks.  If false, the temp is
 577        dead at the end of basic blocks.  */
 578     unsigned int temp_local:1;
 579     unsigned int temp_allocated:1;
 580
 581     tcg_target_long val;
 582     struct TCGTemp *mem_base;
 583     intptr_t mem_offset;
 584     const char *name;
 585
 586     /* Pass-specific information that can be stored for a temporary.
 587        One word worth of integer data, and one pointer to data
 588        allocated separately.  */
 589     uintptr_t state;
 590     void *state_ptr;
 591 } TCGTemp;
 592
 593 typedef struct TCGContext TCGContext;
 594
 595 typedef struct TCGTempSet {
 596     unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)];
 597 } TCGTempSet;
 598
 599 /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding,
 600    this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands.
 601    There are never more than 2 outputs, which means that we can store all
 602    dead + sync data within 16 bits.  */
 603 #define DEAD_ARG  4
 604 #define SYNC_ARG  1
 605 typedef uint16_t TCGLifeData;
 606
 607 /* The layout here is designed to avoid a bitfield crossing of
 608    a 32-bit boundary, which would cause GCC to add extra padding.  */
 609 typedef struct TCGOp {
 610     TCGOpcode opc   : 8;        /*  8 */
 611
 612     /* Parameters for this opcode.  See below.  */
 613     unsigned param1 : 4;        /* 12 */
 614     unsigned param2 : 4;        /* 16 */
 615
 616     /* Lifetime data of the operands.  */
 617     unsigned life   : 16;       /* 32 */
 618
 619     /* Next and previous opcodes.  */
 620     QTAILQ_ENTRY(TCGOp) link;
 621
 622     /* Arguments for the opcode.  */
 623     TCGArg args[MAX_OPC_PARAM];
 624
 625     /* Register preferences for the output(s).  */
 626     TCGRegSet output_pref[2];
 627 } TCGOp;
 628
 629 #define TCGOP_CALLI(X)    (X)->param1
 630 #define TCGOP_CALLO(X)    (X)->param2
 631
 632 #define TCGOP_VECL(X)     (X)->param1
 633 #define TCGOP_VECE(X)     (X)->param2
 634
 635 /* Make sure operands fit in the bitfields above.  */
 636 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8));
 637
 638 typedef struct TCGProfile {
 639     int64_t cpu_exec_time;
 640     int64_t tb_count1;
 641     int64_t tb_count;
 642     int64_t op_count; /* total insn count */
 643     int op_count_max; /* max insn per TB */
 644     int temp_count_max;
 645     int64_t temp_count;
 646     int64_t del_op_count;
 647     int64_t code_in_len;
 648     int64_t code_out_len;
 649     int64_t search_out_len;
 650     int64_t interm_time;
 651     int64_t code_time;
 652     int64_t la_time;
 653     int64_t opt_time;
 654     int64_t restore_count;
 655     int64_t restore_time;
 656     int64_t table_op_count[NB_OPS];
 657 } TCGProfile;
 658
 659 struct TCGContext {
 660     uint8_t *pool_cur, *pool_end;
 661     TCGPool *pool_first, *pool_current, *pool_first_large;
 662     int nb_labels;
 663     int nb_globals;
 664     int nb_temps;
 665     int nb_indirects;
 666     int nb_ops;
 667
 668     /* goto_tb support */
 669     tcg_insn_unit *code_buf;
 670     uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */
 671     uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */
 672     uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */
 673
 674     TCGRegSet reserved_regs;
 675     uint32_t tb_cflags; /* cflags of the current TB */
 676     intptr_t current_frame_offset;
 677     intptr_t frame_start;
 678     intptr_t frame_end;
 679     TCGTemp *frame_temp;
 680
 681     tcg_insn_unit *code_ptr;
 682
 683 #ifdef CONFIG_PROFILER
 684     TCGProfile prof;
 685 #endif
 686
 687 #ifdef CONFIG_DEBUG_TCG
 688     int temps_in_use;
 689     int goto_tb_issue_mask;
 690 #endif
 691
 692     /* Code generation.  Note that we specifically do not use tcg_insn_unit
 693        here, because there's too much arithmetic throughout that relies
 694        on addition and subtraction working on bytes.  Rely on the GCC
 695        extension that allows arithmetic on void*.  */
 696     void *code_gen_prologue;
 697     void *code_gen_epilogue;
 698     void *code_gen_buffer;
 699     size_t code_gen_buffer_size;
 700     void *code_gen_ptr;
 701     void *data_gen_ptr;
 702
 703     /* Threshold to flush the translated code buffer.  */
 704     void *code_gen_highwater;
 705
 706     size_t tb_phys_invalidate_count;
 707
 708     /* Track which vCPU triggers events */
 709     CPUState *cpu;                      /* *_trans */
 710
 711     /* These structures are private to tcg-target.inc.c.  */
 712 #ifdef TCG_TARGET_NEED_LDST_LABELS
 713     QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels;
 714 #endif
 715 #ifdef TCG_TARGET_NEED_POOL_LABELS
 716     struct TCGLabelPoolData *pool_labels;
 717 #endif
 718
 719     TCGLabel *exitreq_label;
 720
 721     TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
 722     TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
 723
 724     QTAILQ_HEAD(, TCGOp) ops, free_ops;
 725
 726     /* Tells which temporary holds a given register.
 727        It does not take into account fixed registers */
 728     TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
 729
 730     uint16_t gen_insn_end_off[TCG_MAX_INSNS];
 731     target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
 732 };
 733
 734 extern TCGContext tcg_init_ctx;
 735 extern __thread TCGContext *tcg_ctx;
 736 extern TCGv_env cpu_env;
 737
 738 static inline size_t temp_idx(TCGTemp *ts)
 739 {
 740     ptrdiff_t n = ts - tcg_ctx->temps;
 741     tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps);
 742     return n;
 743 }
 744
 745 static inline TCGArg temp_arg(TCGTemp *ts)
 746 {
 747     return (uintptr_t)ts;
 748 }
 749
 750 static inline TCGTemp *arg_temp(TCGArg a)
 751 {
 752     return (TCGTemp *)(uintptr_t)a;
 753 }
 754
 755 /* Using the offset of a temporary, relative to TCGContext, rather than
 756    its index means that we don't use 0.  That leaves offset 0 free for
 757    a NULL representation without having to leave index 0 unused.  */
 758 static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v)
 759 {
 760     uintptr_t o = (uintptr_t)v;
 761     TCGTemp *t = (void *)tcg_ctx + o;
 762     tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o);
 763     return t;
 764 }
 765
 766 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v)
 767 {
 768     return tcgv_i32_temp((TCGv_i32)v);
 769 }
 770
 771 static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v)
 772 {
 773     return tcgv_i32_temp((TCGv_i32)v);
 774 }
 775
 776 static inline TCGTemp *tcgv_vec_temp(TCGv_vec v)
 777 {
 778     return tcgv_i32_temp((TCGv_i32)v);
 779 }
 780
 781 static inline TCGArg tcgv_i32_arg(TCGv_i32 v)
 782 {
 783     return temp_arg(tcgv_i32_temp(v));
 784 }
 785
 786 static inline TCGArg tcgv_i64_arg(TCGv_i64 v)
 787 {
 788     return temp_arg(tcgv_i64_temp(v));
 789 }
 790
 791 static inline TCGArg tcgv_ptr_arg(TCGv_ptr v)
 792 {
 793     return temp_arg(tcgv_ptr_temp(v));
 794 }
 795
 796 static inline TCGArg tcgv_vec_arg(TCGv_vec v)
 797 {
 798     return temp_arg(tcgv_vec_temp(v));
 799 }
 800
 801 static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t)
 802 {
 803     (void)temp_idx(t); /* trigger embedded assert */
 804     return (TCGv_i32)((void *)t - (void *)tcg_ctx);
 805 }
 806
 807 static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t)
 808 {
 809     return (TCGv_i64)temp_tcgv_i32(t);
 810 }
 811
 812 static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t)
 813 {
 814     return (TCGv_ptr)temp_tcgv_i32(t);
 815 }
 816
 817 static inline TCGv_vec temp_tcgv_vec(TCGTemp *t)
 818 {
 819     return (TCGv_vec)temp_tcgv_i32(t);
 820 }
 821
 822 #if TCG_TARGET_REG_BITS == 32
 823 static inline TCGv_i32 TCGV_LOW(TCGv_i64 t)
 824 {
 825     return temp_tcgv_i32(tcgv_i64_temp(t));
 826 }
 827
 828 static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t)
 829 {
 830     return temp_tcgv_i32(tcgv_i64_temp(t) + 1);
 831 }
 832 #endif
 833
 834 static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v)
 835 {
 836     op->args[arg] = v;
 837 }
 838
 839 static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v)
 840 {
 841 #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
 842     tcg_set_insn_param(op, arg, v);
 843 #else
 844     tcg_set_insn_param(op, arg * 2, v);
 845     tcg_set_insn_param(op, arg * 2 + 1, v >> 32);
 846 #endif
 847 }
 848
 849 /* The last op that was emitted.  */
 850 static inline TCGOp *tcg_last_op(void)
 851 {
 852     return QTAILQ_LAST(&tcg_ctx->ops);
 853 }
 854
 855 /* Test for whether to terminate the TB for using too many opcodes.  */
 856 static inline bool tcg_op_buf_full(void)
 857 {
 858     /* This is not a hard limit, it merely stops translation when
 859      * we have produced "enough" opcodes.  We want to limit TB size
 860      * such that a RISC host can reasonably use a 16-bit signed
 861      * branch within the TB.  We also need to be mindful of the
 862      * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[]
 863      * and TCGContext.gen_insn_end_off[].
 864      */
 865     return tcg_ctx->nb_ops >= 4000;
 866 }
 867
 868 /* pool based memory allocation */
 869
 870 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */
 871 void *tcg_malloc_internal(TCGContext *s, int size);
 872 void tcg_pool_reset(TCGContext *s);
 873 TranslationBlock *tcg_tb_alloc(TCGContext *s);
 874
 875 void tcg_region_init(void);
 876 void tcg_region_reset_all(void);
 877
 878 size_t tcg_code_size(void);
 879 size_t tcg_code_capacity(void);
 880
 881 void tcg_tb_insert(TranslationBlock *tb);
 882 void tcg_tb_remove(TranslationBlock *tb);
 883 size_t tcg_tb_phys_invalidate_count(void);
 884 TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr);
 885 void tcg_tb_foreach(GTraverseFunc func, gpointer user_data);
 886 size_t tcg_nb_tbs(void);
 887
 888 /* user-mode: Called with mmap_lock held.  */
 889 static inline void *tcg_malloc(int size)
 890 {
 891     TCGContext *s = tcg_ctx;
 892     uint8_t *ptr, *ptr_end;
 893
 894     /* ??? This is a weak placeholder for minimum malloc alignment.  */
 895     size = QEMU_ALIGN_UP(size, 8);
 896
 897     ptr = s->pool_cur;
 898     ptr_end = ptr + size;
 899     if (unlikely(ptr_end > s->pool_end)) {
 900         return tcg_malloc_internal(tcg_ctx, size);
 901     } else {
 902         s->pool_cur = ptr_end;
 903         return ptr;
 904     }
 905 }
 906
 907 void tcg_context_init(TCGContext *s);
 908 void tcg_register_thread(void);
 909 void tcg_prologue_init(TCGContext *s);
 910 void tcg_func_start(TCGContext *s);
 911
 912 int tcg_gen_code(TCGContext *s, TranslationBlock *tb);
 913
 914 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
 915
 916 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr,
 917                                      intptr_t, const char *);
 918 TCGTemp *tcg_temp_new_internal(TCGType, bool);
 919 void tcg_temp_free_internal(TCGTemp *);
 920 TCGv_vec tcg_temp_new_vec(TCGType type);
 921 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match);
 922
 923 static inline void tcg_temp_free_i32(TCGv_i32 arg)
 924 {
 925     tcg_temp_free_internal(tcgv_i32_temp(arg));
 926 }
 927
 928 static inline void tcg_temp_free_i64(TCGv_i64 arg)
 929 {
 930     tcg_temp_free_internal(tcgv_i64_temp(arg));
 931 }
 932
 933 static inline void tcg_temp_free_ptr(TCGv_ptr arg)
 934 {
 935     tcg_temp_free_internal(tcgv_ptr_temp(arg));
 936 }
 937
 938 static inline void tcg_temp_free_vec(TCGv_vec arg)
 939 {
 940     tcg_temp_free_internal(tcgv_vec_temp(arg));
 941 }
 942
 943 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
 944                                               const char *name)
 945 {
 946     TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
 947     return temp_tcgv_i32(t);
 948 }
 949
 950 static inline TCGv_i32 tcg_temp_new_i32(void)
 951 {
 952     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, false);
 953     return temp_tcgv_i32(t);
 954 }
 955
 956 static inline TCGv_i32 tcg_temp_local_new_i32(void)
 957 {
 958     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, true);
 959     return temp_tcgv_i32(t);
 960 }
 961
 962 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
 963                                               const char *name)
 964 {
 965     TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
 966     return temp_tcgv_i64(t);
 967 }
 968
 969 static inline TCGv_i64 tcg_temp_new_i64(void)
 970 {
 971     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, false);
 972     return temp_tcgv_i64(t);
 973 }
 974
 975 static inline TCGv_i64 tcg_temp_local_new_i64(void)
 976 {
 977     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, true);
 978     return temp_tcgv_i64(t);
 979 }
 980
 981 static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset,
 982                                               const char *name)
 983 {
 984     TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name);
 985     return temp_tcgv_ptr(t);
 986 }
 987
 988 static inline TCGv_ptr tcg_temp_new_ptr(void)
 989 {
 990     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, false);
 991     return temp_tcgv_ptr(t);
 992 }
 993
 994 static inline TCGv_ptr tcg_temp_local_new_ptr(void)
 995 {
 996     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, true);
 997     return temp_tcgv_ptr(t);
 998 }
 999
1000 #if defined(CONFIG_DEBUG_TCG)
1001 /* If you call tcg_clear_temp_count() at the start of a section of
1002  * code which is not supposed to leak any TCG temporaries, then
1003  * calling tcg_check_temp_count() at the end of the section will
1004  * return 1 if the section did in fact leak a temporary.
1005  */
1006 void tcg_clear_temp_count(void);
1007 int tcg_check_temp_count(void);
1008 #else
1009 #define tcg_clear_temp_count() do { } while (0)
1010 #define tcg_check_temp_count() 0
1011 #endif
1012
1013 int64_t tcg_cpu_exec_time(void);
1014 void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf);
1015 void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf);
1016
1017 #define TCG_CT_ALIAS  0x80
1018 #define TCG_CT_IALIAS 0x40
1019 #define TCG_CT_NEWREG 0x20 /* output requires a new register */
1020 #define TCG_CT_REG    0x01
1021 #define TCG_CT_CONST  0x02 /* any constant of register size */
1022
1023 typedef struct TCGArgConstraint {
1024     uint16_t ct;
1025     uint8_t alias_index;
1026     union {
1027         TCGRegSet regs;
1028     } u;
1029 } TCGArgConstraint;
1030
1031 #define TCG_MAX_OP_ARGS 16
1032
1033 /* Bits for TCGOpDef->flags, 8 bits available.  */
1034 enum {
1035     /* Instruction exits the translation block.  */
1036     TCG_OPF_BB_EXIT      = 0x01,
1037     /* Instruction defines the end of a basic block.  */
1038     TCG_OPF_BB_END       = 0x02,
1039     /* Instruction clobbers call registers and potentially update globals.  */
1040     TCG_OPF_CALL_CLOBBER = 0x04,
1041     /* Instruction has side effects: it cannot be removed if its outputs
1042        are not used, and might trigger exceptions.  */
1043     TCG_OPF_SIDE_EFFECTS = 0x08,
1044     /* Instruction operands are 64-bits (otherwise 32-bits).  */
1045     TCG_OPF_64BIT        = 0x10,
1046     /* Instruction is optional and not implemented by the host, or insn
1047        is generic and should not be implemened by the host.  */
1048     TCG_OPF_NOT_PRESENT  = 0x20,
1049     /* Instruction operands are vectors.  */
1050     TCG_OPF_VECTOR       = 0x40,
1051 };
1052
1053 typedef struct TCGOpDef {
1054     const char *name;
1055     uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
1056     uint8_t flags;
1057     TCGArgConstraint *args_ct;
1058     int *sorted_args;
1059 #if defined(CONFIG_DEBUG_TCG)
1060     int used;
1061 #endif
1062 } TCGOpDef;
1063
1064 extern TCGOpDef tcg_op_defs[];
1065 extern const size_t tcg_op_defs_max;
1066
1067 typedef struct TCGTargetOpDef {
1068     TCGOpcode op;
1069     const char *args_ct_str[TCG_MAX_OP_ARGS];
1070 } TCGTargetOpDef;
1071
1072 #define tcg_abort() \
1073 do {\
1074     fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
1075     abort();\
1076 } while (0)
1077
1078 bool tcg_op_supported(TCGOpcode op);
1079
1080 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args);
1081
1082 TCGOp *tcg_emit_op(TCGOpcode opc);
1083 void tcg_op_remove(TCGContext *s, TCGOp *op);
1084 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc);
1085 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc);
1086
1087 void tcg_optimize(TCGContext *s);
1088
1089 TCGv_i32 tcg_const_i32(int32_t val);
1090 TCGv_i64 tcg_const_i64(int64_t val);
1091 TCGv_i32 tcg_const_local_i32(int32_t val);
1092 TCGv_i64 tcg_const_local_i64(int64_t val);
1093 TCGv_vec tcg_const_zeros_vec(TCGType);
1094 TCGv_vec tcg_const_ones_vec(TCGType);
1095 TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec);
1096 TCGv_vec tcg_const_ones_vec_matching(TCGv_vec);
1097
1098 #if UINTPTR_MAX == UINT32_MAX
1099 # define tcg_const_ptr(x)        ((TCGv_ptr)tcg_const_i32((intptr_t)(x)))
1100 # define tcg_const_local_ptr(x)  ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x)))
1101 #else
1102 # define tcg_const_ptr(x)        ((TCGv_ptr)tcg_const_i64((intptr_t)(x)))
1103 # define tcg_const_local_ptr(x)  ((TCGv_ptr)tcg_const_local_i64((intptr_t)(x)))
1104 #endif
1105
1106 TCGLabel *gen_new_label(void);
1107
1108 /**
1109  * label_arg
1110  * @l: label
1111  *
1112  * Encode a label for storage in the TCG opcode stream.
1113  */
1114
1115 static inline TCGArg label_arg(TCGLabel *l)
1116 {
1117     return (uintptr_t)l;
1118 }
1119
1120 /**
1121  * arg_label
1122  * @i: value
1123  *
1124  * The opposite of label_arg.  Retrieve a label from the
1125  * encoding of the TCG opcode stream.
1126  */
1127
1128 static inline TCGLabel *arg_label(TCGArg i)
1129 {
1130     return (TCGLabel *)(uintptr_t)i;
1131 }
1132
1133 /**
1134  * tcg_ptr_byte_diff
1135  * @a, @b: addresses to be differenced
1136  *
1137  * There are many places within the TCG backends where we need a byte
1138  * difference between two pointers.  While this can be accomplished
1139  * with local casting, it's easy to get wrong -- especially if one is
1140  * concerned with the signedness of the result.
1141  *
1142  * This version relies on GCC's void pointer arithmetic to get the
1143  * correct result.
1144  */
1145
1146 static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b)
1147 {
1148     return a - b;
1149 }
1150
1151 /**
1152  * tcg_pcrel_diff
1153  * @s: the tcg context
1154  * @target: address of the target
1155  *
1156  * Produce a pc-relative difference, from the current code_ptr
1157  * to the destination address.
1158  */
1159
1160 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target)
1161 {
1162     return tcg_ptr_byte_diff(target, s->code_ptr);
1163 }
1164
1165 /**
1166  * tcg_current_code_size
1167  * @s: the tcg context
1168  *
1169  * Compute the current code size within the translation block.
1170  * This is used to fill in qemu's data structures for goto_tb.
1171  */
1172
1173 static inline size_t tcg_current_code_size(TCGContext *s)
1174 {
1175     return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);
1176 }
1177
1178 /* Combine the TCGMemOp and mmu_idx parameters into a single value.  */
1179 typedef uint32_t TCGMemOpIdx;
1180
1181 /**
1182  * make_memop_idx
1183  * @op: memory operation
1184  * @idx: mmu index
1185  *
1186  * Encode these values into a single parameter.
1187  */
1188 static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)
1189 {
1190     tcg_debug_assert(idx <= 15);
1191     return (op << 4) | idx;
1192 }
1193
1194 /**
1195  * get_memop
1196  * @oi: combined op/idx parameter
1197  *
1198  * Extract the memory operation from the combined value.
1199  */
1200 static inline TCGMemOp get_memop(TCGMemOpIdx oi)
1201 {
1202     return oi >> 4;
1203 }
1204
1205 /**
1206  * get_mmuidx
1207  * @oi: combined op/idx parameter
1208  *
1209  * Extract the mmu index from the combined value.
1210  */
1211 static inline unsigned get_mmuidx(TCGMemOpIdx oi)
1212 {
1213     return oi & 15;
1214 }
1215
1216 /**
1217  * tcg_qemu_tb_exec:
1218  * @env: pointer to CPUArchState for the CPU
1219  * @tb_ptr: address of generated code for the TB to execute
1220  *
1221  * Start executing code from a given translation block.
1222  * Where translation blocks have been linked, execution
1223  * may proceed from the given TB into successive ones.
1224  * Control eventually returns only when some action is needed
1225  * from the top-level loop: either control must pass to a TB
1226  * which has not yet been directly linked, or an asynchronous
1227  * event such as an interrupt needs handling.
1228  *
1229  * Return: The return value is the value passed to the corresponding
1230  * tcg_gen_exit_tb() at translation time of the last TB attempted to execute.
1231  * The value is either zero or a 4-byte aligned pointer to that TB combined
1232  * with additional information in its two least significant bits. The
1233  * additional information is encoded as follows:
1234  *  0, 1: the link between this TB and the next is via the specified
1235  *        TB index (0 or 1). That is, we left the TB via (the equivalent
1236  *        of) "goto_tb <index>". The main loop uses this to determine
1237  *        how to link the TB just executed to the next.
1238  *  2:    we are using instruction counting code generation, and we
1239  *        did not start executing this TB because the instruction counter
1240  *        would hit zero midway through it. In this case the pointer
1241  *        returned is the TB we were about to execute, and the caller must
1242  *        arrange to execute the remaining count of instructions.
1243  *  3:    we stopped because the CPU's exit_request flag was set
1244  *        (usually meaning that there is an interrupt that needs to be
1245  *        handled). The pointer returned is the TB we were about to execute
1246  *        when we noticed the pending exit request.
1247  *
1248  * If the bottom two bits indicate an exit-via-index then the CPU
1249  * state is correctly synchronised and ready for execution of the next
1250  * TB (and in particular the guest PC is the address to execute next).
1251  * Otherwise, we gave up on execution of this TB before it started, and
1252  * the caller must fix up the CPU state by calling the CPU's
1253  * synchronize_from_tb() method with the TB pointer we return (falling
1254  * back to calling the CPU's set_pc method with tb->pb if no
1255  * synchronize_from_tb() method exists).
1256  *
1257  * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
1258  * to this default (which just calls the prologue.code emitted by
1259  * tcg_target_qemu_prologue()).
1260  */
1261 #define TB_EXIT_MASK      3
1262 #define TB_EXIT_IDX0      0
1263 #define TB_EXIT_IDX1      1
1264 #define TB_EXIT_IDXMAX    1
1265 #define TB_EXIT_REQUESTED 3
1266
1267 #ifdef HAVE_TCG_QEMU_TB_EXEC
1268 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
1269 #else
1270 # define tcg_qemu_tb_exec(env, tb_ptr) \
1271     ((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_ptr)
1272 #endif
1273
1274 void tcg_register_jit(void *buf, size_t buf_size);
1275
1276 #if TCG_TARGET_MAYBE_vec
1277 /* Return zero if the tuple (opc, type, vece) is unsupportable;
1278    return > 0 if it is directly supportable;
1279    return < 0 if we must call tcg_expand_vec_op.  */
1280 int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned);
1281 #else
1282 static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve)
1283 {
1284     return 0;
1285 }
1286 #endif
1287
1288 /* Expand the tuple (opc, type, vece) on the given arguments.  */
1289 void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...);
1290
1291 /* Replicate a constant C accoring to the log2 of the element size.  */
1292 uint64_t dup_const(unsigned vece, uint64_t c);
1293
1294 #define dup_const(VECE, C)                                         \
1295     (__builtin_constant_p(VECE)                                    \
1296      ? (  (VECE) == MO_8  ? 0x0101010101010101ull * (uint8_t)(C)   \
1297         : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C)  \
1298         : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C)  \
1299         : dup_const(VECE, C))                                      \
1300      : dup_const(VECE, C))
1301
1302
1303 /*
1304  * Memory helpers that will be used by TCG generated code.
1305  */
1306 #ifdef CONFIG_SOFTMMU
1307 /* Value zero-extended to tcg register size.  */
1308 tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
1309                                      TCGMemOpIdx oi, uintptr_t retaddr);
1310 tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
1311                                     TCGMemOpIdx oi, uintptr_t retaddr);
1312 tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
1313                                     TCGMemOpIdx oi, uintptr_t retaddr);
1314 uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
1315                            TCGMemOpIdx oi, uintptr_t retaddr);
1316 tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
1317                                     TCGMemOpIdx oi, uintptr_t retaddr);
1318 tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
1319                                     TCGMemOpIdx oi, uintptr_t retaddr);
1320 uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
1321                            TCGMemOpIdx oi, uintptr_t retaddr);
1322
1323 /* Value sign-extended to tcg register size.  */
1324 tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
1325                                      TCGMemOpIdx oi, uintptr_t retaddr);
1326 tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
1327                                     TCGMemOpIdx oi, uintptr_t retaddr);
1328 tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
1329                                     TCGMemOpIdx oi, uintptr_t retaddr);
1330 tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
1331                                     TCGMemOpIdx oi, uintptr_t retaddr);
1332 tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
1333                                     TCGMemOpIdx oi, uintptr_t retaddr);
1334
1335 void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
1336                         TCGMemOpIdx oi, uintptr_t retaddr);
1337 void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1338                        TCGMemOpIdx oi, uintptr_t retaddr);
1339 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1340                        TCGMemOpIdx oi, uintptr_t retaddr);
1341 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1342                        TCGMemOpIdx oi, uintptr_t retaddr);
1343 void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1344                        TCGMemOpIdx oi, uintptr_t retaddr);
1345 void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1346                        TCGMemOpIdx oi, uintptr_t retaddr);
1347 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1348                        TCGMemOpIdx oi, uintptr_t retaddr);
1349
1350 uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
1351                             TCGMemOpIdx oi, uintptr_t retaddr);
1352 uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
1353                             TCGMemOpIdx oi, uintptr_t retaddr);
1354 uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
1355                             TCGMemOpIdx oi, uintptr_t retaddr);
1356 uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
1357                             TCGMemOpIdx oi, uintptr_t retaddr);
1358 uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
1359                             TCGMemOpIdx oi, uintptr_t retaddr);
1360 uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
1361                             TCGMemOpIdx oi, uintptr_t retaddr);
1362 uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
1363                             TCGMemOpIdx oi, uintptr_t retaddr);
1364
1365 /* Temporary aliases until backends are converted.  */
1366 #ifdef TARGET_WORDS_BIGENDIAN
1367 # define helper_ret_ldsw_mmu  helper_be_ldsw_mmu
1368 # define helper_ret_lduw_mmu  helper_be_lduw_mmu
1369 # define helper_ret_ldsl_mmu  helper_be_ldsl_mmu
1370 # define helper_ret_ldul_mmu  helper_be_ldul_mmu
1371 # define helper_ret_ldl_mmu   helper_be_ldul_mmu
1372 # define helper_ret_ldq_mmu   helper_be_ldq_mmu
1373 # define helper_ret_stw_mmu   helper_be_stw_mmu
1374 # define helper_ret_stl_mmu   helper_be_stl_mmu
1375 # define helper_ret_stq_mmu   helper_be_stq_mmu
1376 # define helper_ret_ldw_cmmu  helper_be_ldw_cmmu
1377 # define helper_ret_ldl_cmmu  helper_be_ldl_cmmu
1378 # define helper_ret_ldq_cmmu  helper_be_ldq_cmmu
1379 #else
1380 # define helper_ret_ldsw_mmu  helper_le_ldsw_mmu
1381 # define helper_ret_lduw_mmu  helper_le_lduw_mmu
1382 # define helper_ret_ldsl_mmu  helper_le_ldsl_mmu
1383 # define helper_ret_ldul_mmu  helper_le_ldul_mmu
1384 # define helper_ret_ldl_mmu   helper_le_ldul_mmu
1385 # define helper_ret_ldq_mmu   helper_le_ldq_mmu
1386 # define helper_ret_stw_mmu   helper_le_stw_mmu
1387 # define helper_ret_stl_mmu   helper_le_stl_mmu
1388 # define helper_ret_stq_mmu   helper_le_stq_mmu
1389 # define helper_ret_ldw_cmmu  helper_le_ldw_cmmu
1390 # define helper_ret_ldl_cmmu  helper_le_ldl_cmmu
1391 # define helper_ret_ldq_cmmu  helper_le_ldq_cmmu
1392 #endif
1393
1394 uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
1395                                     uint32_t cmpv, uint32_t newv,
1396                                     TCGMemOpIdx oi, uintptr_t retaddr);
1397 uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr,
1398                                        uint32_t cmpv, uint32_t newv,
1399                                        TCGMemOpIdx oi, uintptr_t retaddr);
1400 uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr,
1401                                        uint32_t cmpv, uint32_t newv,
1402                                        TCGMemOpIdx oi, uintptr_t retaddr);
1403 uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr,
1404                                        uint64_t cmpv, uint64_t newv,
1405                                        TCGMemOpIdx oi, uintptr_t retaddr);
1406 uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr,
1407                                        uint32_t cmpv, uint32_t newv,
1408                                        TCGMemOpIdx oi, uintptr_t retaddr);
1409 uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr,
1410                                        uint32_t cmpv, uint32_t newv,
1411                                        TCGMemOpIdx oi, uintptr_t retaddr);
1412 uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr,
1413                                        uint64_t cmpv, uint64_t newv,
1414                                        TCGMemOpIdx oi, uintptr_t retaddr);
1415
1416 #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX)         \
1417 TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu         \
1418     (CPUArchState *env, target_ulong addr, TYPE val,  \
1419      TCGMemOpIdx oi, uintptr_t retaddr);
1420
1421 #ifdef CONFIG_ATOMIC64
1422 #define GEN_ATOMIC_HELPER_ALL(NAME)          \
1423     GEN_ATOMIC_HELPER(NAME, uint32_t, b)     \
1424     GEN_ATOMIC_HELPER(NAME, uint32_t, w_le)  \
1425     GEN_ATOMIC_HELPER(NAME, uint32_t, w_be)  \
1426     GEN_ATOMIC_HELPER(NAME, uint32_t, l_le)  \
1427     GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)  \
1428     GEN_ATOMIC_HELPER(NAME, uint64_t, q_le)  \
1429     GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
1430 #else
1431 #define GEN_ATOMIC_HELPER_ALL(NAME)          \
1432     GEN_ATOMIC_HELPER(NAME, uint32_t, b)     \
1433     GEN_ATOMIC_HELPER(NAME, uint32_t, w_le)  \
1434     GEN_ATOMIC_HELPER(NAME, uint32_t, w_be)  \
1435     GEN_ATOMIC_HELPER(NAME, uint32_t, l_le)  \
1436     GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)
1437 #endif
1438
1439 GEN_ATOMIC_HELPER_ALL(fetch_add)
1440 GEN_ATOMIC_HELPER_ALL(fetch_sub)
1441 GEN_ATOMIC_HELPER_ALL(fetch_and)
1442 GEN_ATOMIC_HELPER_ALL(fetch_or)
1443 GEN_ATOMIC_HELPER_ALL(fetch_xor)
1444 GEN_ATOMIC_HELPER_ALL(fetch_smin)
1445 GEN_ATOMIC_HELPER_ALL(fetch_umin)
1446 GEN_ATOMIC_HELPER_ALL(fetch_smax)
1447 GEN_ATOMIC_HELPER_ALL(fetch_umax)
1448
1449 GEN_ATOMIC_HELPER_ALL(add_fetch)
1450 GEN_ATOMIC_HELPER_ALL(sub_fetch)
1451 GEN_ATOMIC_HELPER_ALL(and_fetch)
1452 GEN_ATOMIC_HELPER_ALL(or_fetch)
1453 GEN_ATOMIC_HELPER_ALL(xor_fetch)
1454 GEN_ATOMIC_HELPER_ALL(smin_fetch)
1455 GEN_ATOMIC_HELPER_ALL(umin_fetch)
1456 GEN_ATOMIC_HELPER_ALL(smax_fetch)
1457 GEN_ATOMIC_HELPER_ALL(umax_fetch)
1458
1459 GEN_ATOMIC_HELPER_ALL(xchg)
1460
1461 #undef GEN_ATOMIC_HELPER_ALL
1462 #undef GEN_ATOMIC_HELPER
1463 #endif /* CONFIG_SOFTMMU */
1464
1465 /*
1466  * These aren't really a "proper" helpers because TCG cannot manage Int128.
1467  * However, use the same format as the others, for use by the backends.
1468  *
1469  * The cmpxchg functions are only defined if HAVE_CMPXCHG128;
1470  * the ld/st functions are only defined if HAVE_ATOMIC128,
1471  * as defined by <qemu/atomic128.h>.
1472  */
1473 Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr,
1474                                      Int128 cmpv, Int128 newv,
1475                                      TCGMemOpIdx oi, uintptr_t retaddr);
1476 Int128 helper_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr,
1477                                      Int128 cmpv, Int128 newv,
1478                                      TCGMemOpIdx oi, uintptr_t retaddr);
1479
1480 Int128 helper_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr,
1481                                 TCGMemOpIdx oi, uintptr_t retaddr);
1482 Int128 helper_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr,
1483                                 TCGMemOpIdx oi, uintptr_t retaddr);
1484 void helper_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1485                               TCGMemOpIdx oi, uintptr_t retaddr);
1486 void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1487                               TCGMemOpIdx oi, uintptr_t retaddr);
1488
1489 #endif /* TCG_H */