target/ppc/mmu-hash64.h

   1 #ifndef MMU_HASH64_H
   2 #define MMU_HASH64_H
   3
   4 #ifndef CONFIG_USER_ONLY
   5
   6 #ifdef TARGET_PPC64
   7 void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu);
   8 int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
   9                   target_ulong esid, target_ulong vsid);
  10 hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr);
  11 int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, int rw,
  12                                 int mmu_idx);
  13 void ppc_hash64_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
  14                            uint64_t pte0, uint64_t pte1);
  15 void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
  16                                target_ulong pte_index,
  17                                target_ulong pte0, target_ulong pte1);
  18 unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
  19                                           uint64_t pte0, uint64_t pte1);
  20 void ppc_hash64_update_vrma(CPUPPCState *env);
  21 void ppc_hash64_update_rmls(CPUPPCState *env);
  22 #endif
  23
  24 /*
  25  * SLB definitions
  26  */
  27
  28 /* Bits in the SLB ESID word */
  29 #define SLB_ESID_ESID           0xFFFFFFFFF0000000ULL
  30 #define SLB_ESID_V              0x0000000008000000ULL /* valid */
  31
  32 /* Bits in the SLB VSID word */
  33 #define SLB_VSID_SHIFT          12
  34 #define SLB_VSID_SHIFT_1T       24
  35 #define SLB_VSID_SSIZE_SHIFT    62
  36 #define SLB_VSID_B              0xc000000000000000ULL
  37 #define SLB_VSID_B_256M         0x0000000000000000ULL
  38 #define SLB_VSID_B_1T           0x4000000000000000ULL
  39 #define SLB_VSID_VSID           0x3FFFFFFFFFFFF000ULL
  40 #define SLB_VSID_VRMA           (0x0001FFFFFF000000ULL | SLB_VSID_B_1T)
  41 #define SLB_VSID_PTEM           (SLB_VSID_B | SLB_VSID_VSID)
  42 #define SLB_VSID_KS             0x0000000000000800ULL
  43 #define SLB_VSID_KP             0x0000000000000400ULL
  44 #define SLB_VSID_N              0x0000000000000200ULL /* no-execute */
  45 #define SLB_VSID_L              0x0000000000000100ULL
  46 #define SLB_VSID_C              0x0000000000000080ULL /* class */
  47 #define SLB_VSID_LP             0x0000000000000030ULL
  48 #define SLB_VSID_ATTR           0x0000000000000FFFULL
  49 #define SLB_VSID_LLP_MASK       (SLB_VSID_L | SLB_VSID_LP)
  50 #define SLB_VSID_4K             0x0000000000000000ULL
  51 #define SLB_VSID_64K            0x0000000000000110ULL
  52 #define SLB_VSID_16M            0x0000000000000100ULL
  53 #define SLB_VSID_16G            0x0000000000000120ULL
  54
  55 /*
  56  * Hash page table definitions
  57  */
  58
  59 #define SDR_64_HTABORG         0x0FFFFFFFFFFC0000ULL
  60 #define SDR_64_HTABSIZE        0x000000000000001FULL
  61
  62 #define HPTES_PER_GROUP         8
  63 #define HASH_PTE_SIZE_64        16
  64 #define HASH_PTEG_SIZE_64       (HASH_PTE_SIZE_64 * HPTES_PER_GROUP)
  65
  66 #define HPTE64_V_SSIZE_SHIFT    62
  67 #define HPTE64_V_AVPN_SHIFT     7
  68 #define HPTE64_V_AVPN           0x3fffffffffffff80ULL
  69 #define HPTE64_V_AVPN_VAL(x)    (((x) & HPTE64_V_AVPN) >> HPTE64_V_AVPN_SHIFT)
  70 #define HPTE64_V_COMPARE(x, y)  (!(((x) ^ (y)) & 0xffffffffffffff83ULL))
  71 #define HPTE64_V_LARGE          0x0000000000000004ULL
  72 #define HPTE64_V_SECONDARY      0x0000000000000002ULL
  73 #define HPTE64_V_VALID          0x0000000000000001ULL
  74
  75 #define HPTE64_R_PP0            0x8000000000000000ULL
  76 #define HPTE64_R_TS             0x4000000000000000ULL
  77 #define HPTE64_R_KEY_HI         0x3000000000000000ULL
  78 #define HPTE64_R_RPN_SHIFT      12
  79 #define HPTE64_R_RPN            0x0ffffffffffff000ULL
  80 #define HPTE64_R_FLAGS          0x00000000000003ffULL
  81 #define HPTE64_R_PP             0x0000000000000003ULL
  82 #define HPTE64_R_N              0x0000000000000004ULL
  83 #define HPTE64_R_G              0x0000000000000008ULL
  84 #define HPTE64_R_M              0x0000000000000010ULL
  85 #define HPTE64_R_I              0x0000000000000020ULL
  86 #define HPTE64_R_W              0x0000000000000040ULL
  87 #define HPTE64_R_WIMG           0x0000000000000078ULL
  88 #define HPTE64_R_C              0x0000000000000080ULL
  89 #define HPTE64_R_R              0x0000000000000100ULL
  90 #define HPTE64_R_KEY_LO         0x0000000000000e00ULL
  91 #define HPTE64_R_KEY(x)         ((((x) & HPTE64_R_KEY_HI) >> 57) | \
  92                                  (((x) & HPTE64_R_KEY_LO) >> 9))
  93
  94 #define HPTE64_V_1TB_SEG        0x4000000000000000ULL
  95 #define HPTE64_V_VRMA_MASK      0x4001ffffff000000ULL
  96
  97 static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu)
  98 {
  99     return cpu->env.spr[SPR_SDR1] & SDR_64_HTABORG;
 100 }
 101
 102 static inline hwaddr ppc_hash64_hpt_mask(PowerPCCPU *cpu)
 103 {
 104     if (cpu->vhyp) {
 105         PPCVirtualHypervisorClass *vhc =
 106             PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
 107         return vhc->hpt_mask(cpu->vhyp);
 108     }
 109     return (1ULL << ((cpu->env.spr[SPR_SDR1] & SDR_64_HTABSIZE) + 18 - 7)) - 1;
 110 }
 111
 112 struct ppc_hash_pte64 {
 113     uint64_t pte0, pte1;
 114 };
 115
 116 const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
 117                                              hwaddr ptex, int n);
 118 void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes,
 119                             hwaddr ptex, int n);
 120
 121 static inline uint64_t ppc_hash64_hpte0(PowerPCCPU *cpu,
 122                                         const ppc_hash_pte64_t *hptes, int i)
 123 {
 124     return ldq_p(&(hptes[i].pte0));
 125 }
 126
 127 static inline uint64_t ppc_hash64_hpte1(PowerPCCPU *cpu,
 128                                         const ppc_hash_pte64_t *hptes, int i)
 129 {
 130     return ldq_p(&(hptes[i].pte1));
 131 }
 132
 133 #endif /* CONFIG_USER_ONLY */
 134
 135 #endif /* MMU_HASH64_H */