hw/openrisc_sim.c

   1 /*
   2  * OpenRISC simulator for use as an IIS.
   3  *
   4  * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
   5  *                         Feng Gao <gf91597@gmail.com>
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "hw.h"
  22 #include "boards.h"
  23 #include "elf.h"
  24 #include "pc.h"
  25 #include "loader.h"
  26 #include "exec-memory.h"
  27 #include "sysemu.h"
  28 #include "sysbus.h"
  29 #include "qtest.h"
  30
  31 #define KERNEL_LOAD_ADDR 0x100
  32
  33 static void main_cpu_reset(void *opaque)
  34 {
  35     OpenRISCCPU *cpu = opaque;
  36
  37     cpu_reset(CPU(cpu));
  38 }
  39
  40 static void openrisc_sim_net_init(MemoryRegion *address_space,
  41                                   target_phys_addr_t base,
  42                                   target_phys_addr_t descriptors,
  43                                   qemu_irq irq, NICInfo *nd)
  44 {
  45     DeviceState *dev;
  46     SysBusDevice *s;
  47
  48     dev = qdev_create(NULL, "open_eth");
  49     qdev_set_nic_properties(dev, nd);
  50     qdev_init_nofail(dev);
  51
  52     s = sysbus_from_qdev(dev);
  53     sysbus_connect_irq(s, 0, irq);
  54     memory_region_add_subregion(address_space, base,
  55                                 sysbus_mmio_get_region(s, 0));
  56     memory_region_add_subregion(address_space, descriptors,
  57                                 sysbus_mmio_get_region(s, 1));
  58 }
  59
  60 static void cpu_openrisc_load_kernel(ram_addr_t ram_size,
  61                                      const char *kernel_filename,
  62                                      OpenRISCCPU *cpu)
  63 {
  64     long kernel_size;
  65     uint64_t elf_entry;
  66     target_phys_addr_t entry;
  67
  68     if (kernel_filename && !qtest_enabled()) {
  69         kernel_size = load_elf(kernel_filename, NULL, NULL,
  70                                &elf_entry, NULL, NULL, 1, ELF_MACHINE, 1);
  71         entry = elf_entry;
  72         if (kernel_size < 0) {
  73             kernel_size = load_uimage(kernel_filename,
  74                                       &entry, NULL, NULL);
  75         }
  76         if (kernel_size < 0) {
  77             kernel_size = load_image_targphys(kernel_filename,
  78                                               KERNEL_LOAD_ADDR,
  79                                               ram_size - KERNEL_LOAD_ADDR);
  80             entry = KERNEL_LOAD_ADDR;
  81         }
  82
  83         if (kernel_size < 0) {
  84             qemu_log("QEMU: couldn't load the kernel '%s'\n",
  85                     kernel_filename);
  86             exit(1);
  87         }
  88     }
  89
  90     cpu->env.pc = entry;
  91 }
  92
  93 static void openrisc_sim_init(QEMUMachineInitArgs *args)
  94 {
  95     ram_addr_t ram_size = args->ram_size;
  96     const char *cpu_model = args->cpu_model;
  97     const char *kernel_filename = args->kernel_filename;
  98    OpenRISCCPU *cpu = NULL;
  99     MemoryRegion *ram;
 100     int n;
 101
 102     if (!cpu_model) {
 103         cpu_model = "or1200";
 104     }
 105
 106     for (n = 0; n < smp_cpus; n++) {
 107         cpu = cpu_openrisc_init(cpu_model);
 108         if (cpu == NULL) {
 109             qemu_log("Unable to find CPU defineition!\n");
 110             exit(1);
 111         }
 112         qemu_register_reset(main_cpu_reset, cpu);
 113         main_cpu_reset(cpu);
 114     }
 115
 116     ram = g_malloc(sizeof(*ram));
 117     memory_region_init_ram(ram, "openrisc.ram", ram_size);
 118     vmstate_register_ram_global(ram);
 119     memory_region_add_subregion(get_system_memory(), 0, ram);
 120
 121     cpu_openrisc_pic_init(cpu);
 122     cpu_openrisc_clock_init(cpu);
 123
 124     serial_mm_init(get_system_memory(), 0x90000000, 0, cpu->env.irq[2],
 125                    115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
 126
 127     if (nd_table[0].used) {
 128         openrisc_sim_net_init(get_system_memory(), 0x92000000,
 129                               0x92000400, cpu->env.irq[4], nd_table);
 130     }
 131
 132     cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
 133 }
 134
 135 static QEMUMachine openrisc_sim_machine = {
 136     .name = "or32-sim",
 137     .desc = "or32 simulation",
 138     .init = openrisc_sim_init,
 139     .max_cpus = 1,
 140     .is_default = 1,
 141 };
 142
 143 static void openrisc_sim_machine_init(void)
 144 {
 145     qemu_register_machine(&openrisc_sim_machine);
 146 }
 147
 148 machine_init(openrisc_sim_machine_init);