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virtio-net: add migration support for RSS and hash report
[qemu/kevin.git] / hw / sparc / sun4m.c
blobee52b5cbbcd22284384225c80ad50cdbd1415743
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qapi/error.h"
28 #include "qemu-common.h"
29 #include "cpu.h"
30 #include "hw/sysbus.h"
31 #include "qemu/error-report.h"
32 #include "qemu/timer.h"
33 #include "hw/sparc/sun4m_iommu.h"
34 #include "hw/rtc/m48t59.h"
35 #include "migration/vmstate.h"
36 #include "hw/sparc/sparc32_dma.h"
37 #include "hw/block/fdc.h"
38 #include "sysemu/reset.h"
39 #include "sysemu/runstate.h"
40 #include "sysemu/sysemu.h"
41 #include "net/net.h"
42 #include "hw/boards.h"
43 #include "hw/scsi/esp.h"
44 #include "hw/nvram/sun_nvram.h"
45 #include "hw/qdev-properties.h"
46 #include "hw/nvram/chrp_nvram.h"
47 #include "hw/nvram/fw_cfg.h"
48 #include "hw/char/escc.h"
49 #include "hw/misc/empty_slot.h"
50 #include "hw/misc/unimp.h"
51 #include "hw/irq.h"
52 #include "hw/loader.h"
53 #include "elf.h"
54 #include "trace.h"
55
56 /*
57 * Sun4m architecture was used in the following machines:
58 *
59 * SPARCserver 6xxMP/xx
60 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
61 * SPARCclassic X (4/10)
62 * SPARCstation LX/ZX (4/30)
63 * SPARCstation Voyager
64 * SPARCstation 10/xx, SPARCserver 10/xx
65 * SPARCstation 5, SPARCserver 5
66 * SPARCstation 20/xx, SPARCserver 20
67 * SPARCstation 4
68 *
69 * See for example: http://www.sunhelp.org/faq/sunref1.html
70 */
71
72 #define KERNEL_LOAD_ADDR 0x00004000
73 #define CMDLINE_ADDR 0x007ff000
74 #define INITRD_LOAD_ADDR 0x00800000
75 #define PROM_SIZE_MAX (1 * MiB)
76 #define PROM_VADDR 0xffd00000
77 #define PROM_FILENAME "openbios-sparc32"
78 #define CFG_ADDR 0xd00000510ULL
79 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
80 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
81 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
82
83 #define MAX_CPUS 16
84 #define MAX_PILS 16
85 #define MAX_VSIMMS 4
86
87 #define ESCC_CLOCK 4915200
88
89 struct sun4m_hwdef {
90 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
91 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
92 hwaddr serial_base, fd_base;
93 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
94 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
95 hwaddr bpp_base, dbri_base, sx_base;
96 struct {
97 hwaddr reg_base, vram_base;
98 } vsimm[MAX_VSIMMS];
99 hwaddr ecc_base;
100 uint64_t max_mem;
101 uint32_t ecc_version;
102 uint32_t iommu_version;
103 uint16_t machine_id;
104 uint8_t nvram_machine_id;
105 };
106
107 const char *fw_cfg_arch_key_name(uint16_t key)
108 {
109 static const struct {
110 uint16_t key;
111 const char *name;
112 } fw_cfg_arch_wellknown_keys[] = {
113 {FW_CFG_SUN4M_DEPTH, "depth"},
114 {FW_CFG_SUN4M_WIDTH, "width"},
115 {FW_CFG_SUN4M_HEIGHT, "height"},
116 };
117
118 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
119 if (fw_cfg_arch_wellknown_keys[i].key == key) {
120 return fw_cfg_arch_wellknown_keys[i].name;
121 }
122 }
123 return NULL;
124 }
125
126 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
127 Error **errp)
128 {
129 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
130 }
131
132 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
133 const char *cmdline, const char *boot_devices,
134 ram_addr_t RAM_size, uint32_t kernel_size,
135 int width, int height, int depth,
136 int nvram_machine_id, const char *arch)
137 {
138 unsigned int i;
139 int sysp_end;
140 uint8_t image[0x1ff0];
141 NvramClass *k = NVRAM_GET_CLASS(nvram);
142
143 memset(image, '\0', sizeof(image));
144
145 /* OpenBIOS nvram variables partition */
146 sysp_end = chrp_nvram_create_system_partition(image, 0);
147
148 /* Free space partition */
149 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
150
151 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
152 nvram_machine_id);
153
154 for (i = 0; i < sizeof(image); i++) {
155 (k->write)(nvram, i, image[i]);
156 }
157 }
158
159 void cpu_check_irqs(CPUSPARCState *env)
160 {
161 CPUState *cs;
162
163 /* We should be holding the BQL before we mess with IRQs */
164 g_assert(qemu_mutex_iothread_locked());
165
166 if (env->pil_in && (env->interrupt_index == 0 ||
167 (env->interrupt_index & ~15) == TT_EXTINT)) {
168 unsigned int i;
169
170 for (i = 15; i > 0; i--) {
171 if (env->pil_in & (1 << i)) {
172 int old_interrupt = env->interrupt_index;
173
174 env->interrupt_index = TT_EXTINT | i;
175 if (old_interrupt != env->interrupt_index) {
176 cs = env_cpu(env);
177 trace_sun4m_cpu_interrupt(i);
178 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
179 }
180 break;
181 }
182 }
183 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
184 cs = env_cpu(env);
185 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
186 env->interrupt_index = 0;
187 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
188 }
189 }
190
191 static void cpu_kick_irq(SPARCCPU *cpu)
192 {
193 CPUSPARCState *env = &cpu->env;
194 CPUState *cs = CPU(cpu);
195
196 cs->halted = 0;
197 cpu_check_irqs(env);
198 qemu_cpu_kick(cs);
199 }
200
201 static void cpu_set_irq(void *opaque, int irq, int level)
202 {
203 SPARCCPU *cpu = opaque;
204 CPUSPARCState *env = &cpu->env;
205
206 if (level) {
207 trace_sun4m_cpu_set_irq_raise(irq);
208 env->pil_in |= 1 << irq;
209 cpu_kick_irq(cpu);
210 } else {
211 trace_sun4m_cpu_set_irq_lower(irq);
212 env->pil_in &= ~(1 << irq);
213 cpu_check_irqs(env);
214 }
215 }
216
217 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
218 {
219 }
220
221 static void main_cpu_reset(void *opaque)
222 {
223 SPARCCPU *cpu = opaque;
224 CPUState *cs = CPU(cpu);
225
226 cpu_reset(cs);
227 cs->halted = 0;
228 }
229
230 static void secondary_cpu_reset(void *opaque)
231 {
232 SPARCCPU *cpu = opaque;
233 CPUState *cs = CPU(cpu);
234
235 cpu_reset(cs);
236 cs->halted = 1;
237 }
238
239 static void cpu_halt_signal(void *opaque, int irq, int level)
240 {
241 if (level && current_cpu) {
242 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
243 }
244 }
245
246 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
247 {
248 return addr - 0xf0000000ULL;
249 }
250
251 static unsigned long sun4m_load_kernel(const char *kernel_filename,
252 const char *initrd_filename,
253 ram_addr_t RAM_size,
254 uint32_t *initrd_size)
255 {
256 int linux_boot;
257 unsigned int i;
258 long kernel_size;
259 uint8_t *ptr;
260
261 linux_boot = (kernel_filename != NULL);
262
263 kernel_size = 0;
264 if (linux_boot) {
265 int bswap_needed;
266
267 #ifdef BSWAP_NEEDED
268 bswap_needed = 1;
269 #else
270 bswap_needed = 0;
271 #endif
272 kernel_size = load_elf(kernel_filename, NULL,
273 translate_kernel_address, NULL,
274 NULL, NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
275 if (kernel_size < 0)
276 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
277 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
278 TARGET_PAGE_SIZE);
279 if (kernel_size < 0)
280 kernel_size = load_image_targphys(kernel_filename,
281 KERNEL_LOAD_ADDR,
282 RAM_size - KERNEL_LOAD_ADDR);
283 if (kernel_size < 0) {
284 error_report("could not load kernel '%s'", kernel_filename);
285 exit(1);
286 }
287
288 /* load initrd */
289 *initrd_size = 0;
290 if (initrd_filename) {
291 *initrd_size = load_image_targphys(initrd_filename,
292 INITRD_LOAD_ADDR,
293 RAM_size - INITRD_LOAD_ADDR);
294 if ((int)*initrd_size < 0) {
295 error_report("could not load initial ram disk '%s'",
296 initrd_filename);
297 exit(1);
298 }
299 }
300 if (*initrd_size > 0) {
301 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
302 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24);
303 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */
304 stl_p(ptr + 16, INITRD_LOAD_ADDR);
305 stl_p(ptr + 20, *initrd_size);
306 break;
307 }
308 }
309 }
310 }
311 return kernel_size;
312 }
313
314 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
315 {
316 DeviceState *dev;
317 SysBusDevice *s;
318
319 dev = qdev_new(TYPE_SUN4M_IOMMU);
320 qdev_prop_set_uint32(dev, "version", version);
321 s = SYS_BUS_DEVICE(dev);
322 sysbus_realize_and_unref(s, &error_fatal);
323 sysbus_connect_irq(s, 0, irq);
324 sysbus_mmio_map(s, 0, addr);
325
326 return s;
327 }
328
329 static void *sparc32_dma_init(hwaddr dma_base,
330 hwaddr esp_base, qemu_irq espdma_irq,
331 hwaddr le_base, qemu_irq ledma_irq)
332 {
333 DeviceState *dma;
334 ESPDMADeviceState *espdma;
335 LEDMADeviceState *ledma;
336 SysBusESPState *esp;
337 SysBusPCNetState *lance;
338
339 dma = qdev_new(TYPE_SPARC32_DMA);
340 sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
341 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
342
343 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
344 OBJECT(dma), "espdma"));
345 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
346
347 esp = ESP_STATE(object_resolve_path_component(OBJECT(espdma), "esp"));
348 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
349 scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
350
351 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
352 OBJECT(dma), "ledma"));
353 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
354
355 lance = SYSBUS_PCNET(object_resolve_path_component(
356 OBJECT(ledma), "lance"));
357 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
358
359 return dma;
360 }
361
362 static DeviceState *slavio_intctl_init(hwaddr addr,
363 hwaddr addrg,
364 qemu_irq **parent_irq)
365 {
366 DeviceState *dev;
367 SysBusDevice *s;
368 unsigned int i, j;
369
370 dev = qdev_new("slavio_intctl");
371
372 s = SYS_BUS_DEVICE(dev);
373 sysbus_realize_and_unref(s, &error_fatal);
374
375 for (i = 0; i < MAX_CPUS; i++) {
376 for (j = 0; j < MAX_PILS; j++) {
377 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
378 }
379 }
380 sysbus_mmio_map(s, 0, addrg);
381 for (i = 0; i < MAX_CPUS; i++) {
382 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
383 }
384
385 return dev;
386 }
387
388 #define SYS_TIMER_OFFSET 0x10000ULL
389 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
390
391 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
392 qemu_irq *cpu_irqs, unsigned int num_cpus)
393 {
394 DeviceState *dev;
395 SysBusDevice *s;
396 unsigned int i;
397
398 dev = qdev_new("slavio_timer");
399 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
400 s = SYS_BUS_DEVICE(dev);
401 sysbus_realize_and_unref(s, &error_fatal);
402 sysbus_connect_irq(s, 0, master_irq);
403 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
404
405 for (i = 0; i < MAX_CPUS; i++) {
406 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
407 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
408 }
409 }
410
411 static qemu_irq slavio_system_powerdown;
412
413 static void slavio_powerdown_req(Notifier *n, void *opaque)
414 {
415 qemu_irq_raise(slavio_system_powerdown);
416 }
417
418 static Notifier slavio_system_powerdown_notifier = {
419 .notify = slavio_powerdown_req
420 };
421
422 #define MISC_LEDS 0x01600000
423 #define MISC_CFG 0x01800000
424 #define MISC_DIAG 0x01a00000
425 #define MISC_MDM 0x01b00000
426 #define MISC_SYS 0x01f00000
427
428 static void slavio_misc_init(hwaddr base,
429 hwaddr aux1_base,
430 hwaddr aux2_base, qemu_irq irq,
431 qemu_irq fdc_tc)
432 {
433 DeviceState *dev;
434 SysBusDevice *s;
435
436 dev = qdev_new("slavio_misc");
437 s = SYS_BUS_DEVICE(dev);
438 sysbus_realize_and_unref(s, &error_fatal);
439 if (base) {
440 /* 8 bit registers */
441 /* Slavio control */
442 sysbus_mmio_map(s, 0, base + MISC_CFG);
443 /* Diagnostics */
444 sysbus_mmio_map(s, 1, base + MISC_DIAG);
445 /* Modem control */
446 sysbus_mmio_map(s, 2, base + MISC_MDM);
447 /* 16 bit registers */
448 /* ss600mp diag LEDs */
449 sysbus_mmio_map(s, 3, base + MISC_LEDS);
450 /* 32 bit registers */
451 /* System control */
452 sysbus_mmio_map(s, 4, base + MISC_SYS);
453 }
454 if (aux1_base) {
455 /* AUX 1 (Misc System Functions) */
456 sysbus_mmio_map(s, 5, aux1_base);
457 }
458 if (aux2_base) {
459 /* AUX 2 (Software Powerdown Control) */
460 sysbus_mmio_map(s, 6, aux2_base);
461 }
462 sysbus_connect_irq(s, 0, irq);
463 sysbus_connect_irq(s, 1, fdc_tc);
464 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
465 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
466 }
467
468 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
469 {
470 DeviceState *dev;
471 SysBusDevice *s;
472
473 dev = qdev_new("eccmemctl");
474 qdev_prop_set_uint32(dev, "version", version);
475 s = SYS_BUS_DEVICE(dev);
476 sysbus_realize_and_unref(s, &error_fatal);
477 sysbus_connect_irq(s, 0, irq);
478 sysbus_mmio_map(s, 0, base);
479 if (version == 0) { // SS-600MP only
480 sysbus_mmio_map(s, 1, base + 0x1000);
481 }
482 }
483
484 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
485 {
486 DeviceState *dev;
487 SysBusDevice *s;
488
489 dev = qdev_new("apc");
490 s = SYS_BUS_DEVICE(dev);
491 sysbus_realize_and_unref(s, &error_fatal);
492 /* Power management (APC) XXX: not a Slavio device */
493 sysbus_mmio_map(s, 0, power_base);
494 sysbus_connect_irq(s, 0, cpu_halt);
495 }
496
497 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
498 int height, int depth)
499 {
500 DeviceState *dev;
501 SysBusDevice *s;
502
503 dev = qdev_new("SUNW,tcx");
504 qdev_prop_set_uint32(dev, "vram_size", vram_size);
505 qdev_prop_set_uint16(dev, "width", width);
506 qdev_prop_set_uint16(dev, "height", height);
507 qdev_prop_set_uint16(dev, "depth", depth);
508 s = SYS_BUS_DEVICE(dev);
509 sysbus_realize_and_unref(s, &error_fatal);
510
511 /* 10/ROM : FCode ROM */
512 sysbus_mmio_map(s, 0, addr);
513 /* 2/STIP : Stipple */
514 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
515 /* 3/BLIT : Blitter */
516 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
517 /* 5/RSTIP : Raw Stipple */
518 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
519 /* 6/RBLIT : Raw Blitter */
520 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
521 /* 7/TEC : Transform Engine */
522 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
523 /* 8/CMAP : DAC */
524 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
525 /* 9/THC : */
526 if (depth == 8) {
527 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
528 } else {
529 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
530 }
531 /* 11/DHC : */
532 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
533 /* 12/ALT : */
534 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
535 /* 0/DFB8 : 8-bit plane */
536 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
537 /* 1/DFB24 : 24bit plane */
538 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
539 /* 4/RDFB32: Raw framebuffer. Control plane */
540 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
541 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
542 if (depth == 8) {
543 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
544 }
545
546 sysbus_connect_irq(s, 0, irq);
547 }
548
549 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
550 int height, int depth)
551 {
552 DeviceState *dev;
553 SysBusDevice *s;
554
555 dev = qdev_new("cgthree");
556 qdev_prop_set_uint32(dev, "vram-size", vram_size);
557 qdev_prop_set_uint16(dev, "width", width);
558 qdev_prop_set_uint16(dev, "height", height);
559 qdev_prop_set_uint16(dev, "depth", depth);
560 s = SYS_BUS_DEVICE(dev);
561 sysbus_realize_and_unref(s, &error_fatal);
562
563 /* FCode ROM */
564 sysbus_mmio_map(s, 0, addr);
565 /* DAC */
566 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
567 /* 8-bit plane */
568 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
569
570 sysbus_connect_irq(s, 0, irq);
571 }
572
573 /* NCR89C100/MACIO Internal ID register */
574
575 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
576
577 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
578
579 static void idreg_init(hwaddr addr)
580 {
581 DeviceState *dev;
582 SysBusDevice *s;
583
584 dev = qdev_new(TYPE_MACIO_ID_REGISTER);
585 s = SYS_BUS_DEVICE(dev);
586 sysbus_realize_and_unref(s, &error_fatal);
587
588 sysbus_mmio_map(s, 0, addr);
589 address_space_write_rom(&address_space_memory, addr,
590 MEMTXATTRS_UNSPECIFIED,
591 idreg_data, sizeof(idreg_data));
592 }
593
594 #define MACIO_ID_REGISTER(obj) \
595 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
596
597 typedef struct IDRegState {
598 SysBusDevice parent_obj;
599
600 MemoryRegion mem;
601 } IDRegState;
602
603 static void idreg_realize(DeviceState *ds, Error **errp)
604 {
605 IDRegState *s = MACIO_ID_REGISTER(ds);
606 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
607 Error *local_err = NULL;
608
609 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg",
610 sizeof(idreg_data), &local_err);
611 if (local_err) {
612 error_propagate(errp, local_err);
613 return;
614 }
615
616 vmstate_register_ram_global(&s->mem);
617 memory_region_set_readonly(&s->mem, true);
618 sysbus_init_mmio(dev, &s->mem);
619 }
620
621 static void idreg_class_init(ObjectClass *oc, void *data)
622 {
623 DeviceClass *dc = DEVICE_CLASS(oc);
624
625 dc->realize = idreg_realize;
626 }
627
628 static const TypeInfo idreg_info = {
629 .name = TYPE_MACIO_ID_REGISTER,
630 .parent = TYPE_SYS_BUS_DEVICE,
631 .instance_size = sizeof(IDRegState),
632 .class_init = idreg_class_init,
633 };
634
635 #define TYPE_TCX_AFX "tcx_afx"
636 #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
637
638 typedef struct AFXState {
639 SysBusDevice parent_obj;
640
641 MemoryRegion mem;
642 } AFXState;
643
644 /* SS-5 TCX AFX register */
645 static void afx_init(hwaddr addr)
646 {
647 DeviceState *dev;
648 SysBusDevice *s;
649
650 dev = qdev_new(TYPE_TCX_AFX);
651 s = SYS_BUS_DEVICE(dev);
652 sysbus_realize_and_unref(s, &error_fatal);
653
654 sysbus_mmio_map(s, 0, addr);
655 }
656
657 static void afx_realize(DeviceState *ds, Error **errp)
658 {
659 AFXState *s = TCX_AFX(ds);
660 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
661 Error *local_err = NULL;
662
663 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4,
664 &local_err);
665 if (local_err) {
666 error_propagate(errp, local_err);
667 return;
668 }
669
670 vmstate_register_ram_global(&s->mem);
671 sysbus_init_mmio(dev, &s->mem);
672 }
673
674 static void afx_class_init(ObjectClass *oc, void *data)
675 {
676 DeviceClass *dc = DEVICE_CLASS(oc);
677
678 dc->realize = afx_realize;
679 }
680
681 static const TypeInfo afx_info = {
682 .name = TYPE_TCX_AFX,
683 .parent = TYPE_SYS_BUS_DEVICE,
684 .instance_size = sizeof(AFXState),
685 .class_init = afx_class_init,
686 };
687
688 #define TYPE_OPENPROM "openprom"
689 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
690
691 typedef struct PROMState {
692 SysBusDevice parent_obj;
693
694 MemoryRegion prom;
695 } PROMState;
696
697 /* Boot PROM (OpenBIOS) */
698 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
699 {
700 hwaddr *base_addr = (hwaddr *)opaque;
701 return addr + *base_addr - PROM_VADDR;
702 }
703
704 static void prom_init(hwaddr addr, const char *bios_name)
705 {
706 DeviceState *dev;
707 SysBusDevice *s;
708 char *filename;
709 int ret;
710
711 dev = qdev_new(TYPE_OPENPROM);
712 s = SYS_BUS_DEVICE(dev);
713 sysbus_realize_and_unref(s, &error_fatal);
714
715 sysbus_mmio_map(s, 0, addr);
716
717 /* load boot prom */
718 if (bios_name == NULL) {
719 bios_name = PROM_FILENAME;
720 }
721 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
722 if (filename) {
723 ret = load_elf(filename, NULL,
724 translate_prom_address, &addr, NULL,
725 NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
726 if (ret < 0 || ret > PROM_SIZE_MAX) {
727 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
728 }
729 g_free(filename);
730 } else {
731 ret = -1;
732 }
733 if (ret < 0 || ret > PROM_SIZE_MAX) {
734 error_report("could not load prom '%s'", bios_name);
735 exit(1);
736 }
737 }
738
739 static void prom_realize(DeviceState *ds, Error **errp)
740 {
741 PROMState *s = OPENPROM(ds);
742 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
743 Error *local_err = NULL;
744
745 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom",
746 PROM_SIZE_MAX, &local_err);
747 if (local_err) {
748 error_propagate(errp, local_err);
749 return;
750 }
751
752 vmstate_register_ram_global(&s->prom);
753 memory_region_set_readonly(&s->prom, true);
754 sysbus_init_mmio(dev, &s->prom);
755 }
756
757 static Property prom_properties[] = {
758 {/* end of property list */},
759 };
760
761 static void prom_class_init(ObjectClass *klass, void *data)
762 {
763 DeviceClass *dc = DEVICE_CLASS(klass);
764
765 device_class_set_props(dc, prom_properties);
766 dc->realize = prom_realize;
767 }
768
769 static const TypeInfo prom_info = {
770 .name = TYPE_OPENPROM,
771 .parent = TYPE_SYS_BUS_DEVICE,
772 .instance_size = sizeof(PROMState),
773 .class_init = prom_class_init,
774 };
775
776 #define TYPE_SUN4M_MEMORY "memory"
777 #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
778
779 typedef struct RamDevice {
780 SysBusDevice parent_obj;
781 HostMemoryBackend *memdev;
782 } RamDevice;
783
784 /* System RAM */
785 static void ram_realize(DeviceState *dev, Error **errp)
786 {
787 RamDevice *d = SUN4M_RAM(dev);
788 MemoryRegion *ram = host_memory_backend_get_memory(d->memdev);
789
790 sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram);
791 }
792
793 static void ram_initfn(Object *obj)
794 {
795 RamDevice *d = SUN4M_RAM(obj);
796 object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND,
797 (Object **)&d->memdev,
798 object_property_allow_set_link,
799 OBJ_PROP_LINK_STRONG);
800 object_property_set_description(obj, "memdev", "Set RAM backend"
801 "Valid value is ID of a hostmem backend");
802 }
803
804 static void ram_class_init(ObjectClass *klass, void *data)
805 {
806 DeviceClass *dc = DEVICE_CLASS(klass);
807
808 dc->realize = ram_realize;
809 }
810
811 static const TypeInfo ram_info = {
812 .name = TYPE_SUN4M_MEMORY,
813 .parent = TYPE_SYS_BUS_DEVICE,
814 .instance_size = sizeof(RamDevice),
815 .instance_init = ram_initfn,
816 .class_init = ram_class_init,
817 };
818
819 static void cpu_devinit(const char *cpu_type, unsigned int id,
820 uint64_t prom_addr, qemu_irq **cpu_irqs)
821 {
822 CPUState *cs;
823 SPARCCPU *cpu;
824 CPUSPARCState *env;
825
826 cpu = SPARC_CPU(cpu_create(cpu_type));
827 env = &cpu->env;
828
829 cpu_sparc_set_id(env, id);
830 if (id == 0) {
831 qemu_register_reset(main_cpu_reset, cpu);
832 } else {
833 qemu_register_reset(secondary_cpu_reset, cpu);
834 cs = CPU(cpu);
835 cs->halted = 1;
836 }
837 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
838 env->prom_addr = prom_addr;
839 }
840
841 static void dummy_fdc_tc(void *opaque, int irq, int level)
842 {
843 }
844
845 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
846 MachineState *machine)
847 {
848 DeviceState *slavio_intctl;
849 unsigned int i;
850 void *nvram;
851 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
852 qemu_irq fdc_tc;
853 unsigned long kernel_size;
854 uint32_t initrd_size;
855 DriveInfo *fd[MAX_FD];
856 FWCfgState *fw_cfg;
857 DeviceState *dev;
858 SysBusDevice *s;
859 unsigned int smp_cpus = machine->smp.cpus;
860 unsigned int max_cpus = machine->smp.max_cpus;
861 Object *ram_memdev = object_resolve_path_type(machine->ram_memdev_id,
862 TYPE_MEMORY_BACKEND, NULL);
863
864 if (machine->ram_size > hwdef->max_mem) {
865 error_report("Too much memory for this machine: %" PRId64 ","
866 " maximum %" PRId64,
867 machine->ram_size / MiB, hwdef->max_mem / MiB);
868 exit(1);
869 }
870
871 /* init CPUs */
872 for(i = 0; i < smp_cpus; i++) {
873 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]);
874 }
875
876 for (i = smp_cpus; i < MAX_CPUS; i++)
877 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
878
879 /* Create and map RAM frontend */
880 dev = qdev_new("memory");
881 object_property_set_link(OBJECT(dev), ram_memdev, "memdev", &error_fatal);
882 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
883 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0);
884
885 /* models without ECC don't trap when missing ram is accessed */
886 if (!hwdef->ecc_base) {
887 empty_slot_init("ecc", machine->ram_size,
888 hwdef->max_mem - machine->ram_size);
889 }
890
891 prom_init(hwdef->slavio_base, bios_name);
892
893 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
894 hwdef->intctl_base + 0x10000ULL,
895 cpu_irqs);
896
897 for (i = 0; i < 32; i++) {
898 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
899 }
900 for (i = 0; i < MAX_CPUS; i++) {
901 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
902 }
903
904 if (hwdef->idreg_base) {
905 idreg_init(hwdef->idreg_base);
906 }
907
908 if (hwdef->afx_base) {
909 afx_init(hwdef->afx_base);
910 }
911
912 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]);
913
914 if (hwdef->iommu_pad_base) {
915 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
916 Software shouldn't use aliased addresses, neither should it crash
917 when does. Using empty_slot instead of aliasing can help with
918 debugging such accesses */
919 empty_slot_init("iommu.alias",
920 hwdef->iommu_pad_base, hwdef->iommu_pad_len);
921 }
922
923 sparc32_dma_init(hwdef->dma_base,
924 hwdef->esp_base, slavio_irq[18],
925 hwdef->le_base, slavio_irq[16]);
926
927 if (graphic_depth != 8 && graphic_depth != 24) {
928 error_report("Unsupported depth: %d", graphic_depth);
929 exit (1);
930 }
931 if (vga_interface_type != VGA_NONE) {
932 if (vga_interface_type == VGA_CG3) {
933 if (graphic_depth != 8) {
934 error_report("Unsupported depth: %d", graphic_depth);
935 exit(1);
936 }
937
938 if (!(graphic_width == 1024 && graphic_height == 768) &&
939 !(graphic_width == 1152 && graphic_height == 900)) {
940 error_report("Unsupported resolution: %d x %d", graphic_width,
941 graphic_height);
942 exit(1);
943 }
944
945 /* sbus irq 5 */
946 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
947 graphic_width, graphic_height, graphic_depth);
948 } else {
949 /* If no display specified, default to TCX */
950 if (graphic_depth != 8 && graphic_depth != 24) {
951 error_report("Unsupported depth: %d", graphic_depth);
952 exit(1);
953 }
954
955 if (!(graphic_width == 1024 && graphic_height == 768)) {
956 error_report("Unsupported resolution: %d x %d",
957 graphic_width, graphic_height);
958 exit(1);
959 }
960
961 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
962 graphic_width, graphic_height, graphic_depth);
963 }
964 }
965
966 for (i = 0; i < MAX_VSIMMS; i++) {
967 /* vsimm registers probed by OBP */
968 if (hwdef->vsimm[i].reg_base) {
969 char *name = g_strdup_printf("vsimm[%d]", i);
970 empty_slot_init(name, hwdef->vsimm[i].reg_base, 0x2000);
971 g_free(name);
972 }
973 }
974
975 if (hwdef->sx_base) {
976 create_unimplemented_device("SUNW,sx", hwdef->sx_base, 0x2000);
977 }
978
979 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
980
981 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
982
983 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
984 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
985 dev = qdev_new(TYPE_ESCC);
986 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics);
987 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
988 qdev_prop_set_uint32(dev, "it_shift", 1);
989 qdev_prop_set_chr(dev, "chrB", NULL);
990 qdev_prop_set_chr(dev, "chrA", NULL);
991 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
992 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
993 s = SYS_BUS_DEVICE(dev);
994 sysbus_realize_and_unref(s, &error_fatal);
995 sysbus_connect_irq(s, 0, slavio_irq[14]);
996 sysbus_connect_irq(s, 1, slavio_irq[14]);
997 sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
998
999 dev = qdev_new(TYPE_ESCC);
1000 qdev_prop_set_uint32(dev, "disabled", 0);
1001 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
1002 qdev_prop_set_uint32(dev, "it_shift", 1);
1003 qdev_prop_set_chr(dev, "chrB", serial_hd(1));
1004 qdev_prop_set_chr(dev, "chrA", serial_hd(0));
1005 qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
1006 qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
1007
1008 s = SYS_BUS_DEVICE(dev);
1009 sysbus_realize_and_unref(s, &error_fatal);
1010 sysbus_connect_irq(s, 0, slavio_irq[15]);
1011 sysbus_connect_irq(s, 1, slavio_irq[15]);
1012 sysbus_mmio_map(s, 0, hwdef->serial_base);
1013
1014 if (hwdef->apc_base) {
1015 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
1016 }
1017
1018 if (hwdef->fd_base) {
1019 /* there is zero or one floppy drive */
1020 memset(fd, 0, sizeof(fd));
1021 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1022 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1023 &fdc_tc);
1024 } else {
1025 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
1026 }
1027
1028 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1029 slavio_irq[30], fdc_tc);
1030
1031 if (hwdef->cs_base) {
1032 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1033 slavio_irq[5]);
1034 }
1035
1036 if (hwdef->dbri_base) {
1037 /* ISDN chip with attached CS4215 audio codec */
1038 /* prom space */
1039 create_unimplemented_device("SUNW,DBRI.prom",
1040 hwdef->dbri_base + 0x1000, 0x30);
1041 /* reg space */
1042 create_unimplemented_device("SUNW,DBRI",
1043 hwdef->dbri_base + 0x10000, 0x100);
1044 }
1045
1046 if (hwdef->bpp_base) {
1047 /* parallel port */
1048 create_unimplemented_device("SUNW,bpp", hwdef->bpp_base, 0x20);
1049 }
1050
1051 initrd_size = 0;
1052 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1053 machine->initrd_filename,
1054 machine->ram_size, &initrd_size);
1055
1056 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1057 machine->boot_order, machine->ram_size, kernel_size,
1058 graphic_width, graphic_height, graphic_depth,
1059 hwdef->nvram_machine_id, "Sun4m");
1060
1061 if (hwdef->ecc_base)
1062 ecc_init(hwdef->ecc_base, slavio_irq[28],
1063 hwdef->ecc_version);
1064
1065 dev = qdev_new(TYPE_FW_CFG_MEM);
1066 fw_cfg = FW_CFG(dev);
1067 qdev_prop_set_uint32(dev, "data_width", 1);
1068 qdev_prop_set_bit(dev, "dma_enabled", false);
1069 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
1070 OBJECT(fw_cfg));
1071 s = SYS_BUS_DEVICE(dev);
1072 sysbus_realize_and_unref(s, &error_fatal);
1073 sysbus_mmio_map(s, 0, CFG_ADDR);
1074 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
1075
1076 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1077 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1078 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
1079 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1080 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1081 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1082 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1083 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1084 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1085 if (machine->kernel_cmdline) {
1086 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1087 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1088 machine->kernel_cmdline);
1089 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1090 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1091 strlen(machine->kernel_cmdline) + 1);
1092 } else {
1093 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1094 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1095 }
1096 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1097 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1098 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1099 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1100 }
1101
1102 enum {
1103 ss5_id = 32,
1104 vger_id,
1105 lx_id,
1106 ss4_id,
1107 scls_id,
1108 sbook_id,
1109 ss10_id = 64,
1110 ss20_id,
1111 ss600mp_id,
1112 };
1113
1114 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1115 /* SS-5 */
1116 {
1117 .iommu_base = 0x10000000,
1118 .iommu_pad_base = 0x10004000,
1119 .iommu_pad_len = 0x0fffb000,
1120 .tcx_base = 0x50000000,
1121 .cs_base = 0x6c000000,
1122 .slavio_base = 0x70000000,
1123 .ms_kb_base = 0x71000000,
1124 .serial_base = 0x71100000,
1125 .nvram_base = 0x71200000,
1126 .fd_base = 0x71400000,
1127 .counter_base = 0x71d00000,
1128 .intctl_base = 0x71e00000,
1129 .idreg_base = 0x78000000,
1130 .dma_base = 0x78400000,
1131 .esp_base = 0x78800000,
1132 .le_base = 0x78c00000,
1133 .apc_base = 0x6a000000,
1134 .afx_base = 0x6e000000,
1135 .aux1_base = 0x71900000,
1136 .aux2_base = 0x71910000,
1137 .nvram_machine_id = 0x80,
1138 .machine_id = ss5_id,
1139 .iommu_version = 0x05000000,
1140 .max_mem = 0x10000000,
1141 },
1142 /* SS-10 */
1143 {
1144 .iommu_base = 0xfe0000000ULL,
1145 .tcx_base = 0xe20000000ULL,
1146 .slavio_base = 0xff0000000ULL,
1147 .ms_kb_base = 0xff1000000ULL,
1148 .serial_base = 0xff1100000ULL,
1149 .nvram_base = 0xff1200000ULL,
1150 .fd_base = 0xff1700000ULL,
1151 .counter_base = 0xff1300000ULL,
1152 .intctl_base = 0xff1400000ULL,
1153 .idreg_base = 0xef0000000ULL,
1154 .dma_base = 0xef0400000ULL,
1155 .esp_base = 0xef0800000ULL,
1156 .le_base = 0xef0c00000ULL,
1157 .apc_base = 0xefa000000ULL, // XXX should not exist
1158 .aux1_base = 0xff1800000ULL,
1159 .aux2_base = 0xff1a01000ULL,
1160 .ecc_base = 0xf00000000ULL,
1161 .ecc_version = 0x10000000, // version 0, implementation 1
1162 .nvram_machine_id = 0x72,
1163 .machine_id = ss10_id,
1164 .iommu_version = 0x03000000,
1165 .max_mem = 0xf00000000ULL,
1166 },
1167 /* SS-600MP */
1168 {
1169 .iommu_base = 0xfe0000000ULL,
1170 .tcx_base = 0xe20000000ULL,
1171 .slavio_base = 0xff0000000ULL,
1172 .ms_kb_base = 0xff1000000ULL,
1173 .serial_base = 0xff1100000ULL,
1174 .nvram_base = 0xff1200000ULL,
1175 .counter_base = 0xff1300000ULL,
1176 .intctl_base = 0xff1400000ULL,
1177 .dma_base = 0xef0081000ULL,
1178 .esp_base = 0xef0080000ULL,
1179 .le_base = 0xef0060000ULL,
1180 .apc_base = 0xefa000000ULL, // XXX should not exist
1181 .aux1_base = 0xff1800000ULL,
1182 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1183 .ecc_base = 0xf00000000ULL,
1184 .ecc_version = 0x00000000, // version 0, implementation 0
1185 .nvram_machine_id = 0x71,
1186 .machine_id = ss600mp_id,
1187 .iommu_version = 0x01000000,
1188 .max_mem = 0xf00000000ULL,
1189 },
1190 /* SS-20 */
1191 {
1192 .iommu_base = 0xfe0000000ULL,
1193 .tcx_base = 0xe20000000ULL,
1194 .slavio_base = 0xff0000000ULL,
1195 .ms_kb_base = 0xff1000000ULL,
1196 .serial_base = 0xff1100000ULL,
1197 .nvram_base = 0xff1200000ULL,
1198 .fd_base = 0xff1700000ULL,
1199 .counter_base = 0xff1300000ULL,
1200 .intctl_base = 0xff1400000ULL,
1201 .idreg_base = 0xef0000000ULL,
1202 .dma_base = 0xef0400000ULL,
1203 .esp_base = 0xef0800000ULL,
1204 .le_base = 0xef0c00000ULL,
1205 .bpp_base = 0xef4800000ULL,
1206 .apc_base = 0xefa000000ULL, // XXX should not exist
1207 .aux1_base = 0xff1800000ULL,
1208 .aux2_base = 0xff1a01000ULL,
1209 .dbri_base = 0xee0000000ULL,
1210 .sx_base = 0xf80000000ULL,
1211 .vsimm = {
1212 {
1213 .reg_base = 0x9c000000ULL,
1214 .vram_base = 0xfc000000ULL
1215 }, {
1216 .reg_base = 0x90000000ULL,
1217 .vram_base = 0xf0000000ULL
1218 }, {
1219 .reg_base = 0x94000000ULL
1220 }, {
1221 .reg_base = 0x98000000ULL
1222 }
1223 },
1224 .ecc_base = 0xf00000000ULL,
1225 .ecc_version = 0x20000000, // version 0, implementation 2
1226 .nvram_machine_id = 0x72,
1227 .machine_id = ss20_id,
1228 .iommu_version = 0x13000000,
1229 .max_mem = 0xf00000000ULL,
1230 },
1231 /* Voyager */
1232 {
1233 .iommu_base = 0x10000000,
1234 .tcx_base = 0x50000000,
1235 .slavio_base = 0x70000000,
1236 .ms_kb_base = 0x71000000,
1237 .serial_base = 0x71100000,
1238 .nvram_base = 0x71200000,
1239 .fd_base = 0x71400000,
1240 .counter_base = 0x71d00000,
1241 .intctl_base = 0x71e00000,
1242 .idreg_base = 0x78000000,
1243 .dma_base = 0x78400000,
1244 .esp_base = 0x78800000,
1245 .le_base = 0x78c00000,
1246 .apc_base = 0x71300000, // pmc
1247 .aux1_base = 0x71900000,
1248 .aux2_base = 0x71910000,
1249 .nvram_machine_id = 0x80,
1250 .machine_id = vger_id,
1251 .iommu_version = 0x05000000,
1252 .max_mem = 0x10000000,
1253 },
1254 /* LX */
1255 {
1256 .iommu_base = 0x10000000,
1257 .iommu_pad_base = 0x10004000,
1258 .iommu_pad_len = 0x0fffb000,
1259 .tcx_base = 0x50000000,
1260 .slavio_base = 0x70000000,
1261 .ms_kb_base = 0x71000000,
1262 .serial_base = 0x71100000,
1263 .nvram_base = 0x71200000,
1264 .fd_base = 0x71400000,
1265 .counter_base = 0x71d00000,
1266 .intctl_base = 0x71e00000,
1267 .idreg_base = 0x78000000,
1268 .dma_base = 0x78400000,
1269 .esp_base = 0x78800000,
1270 .le_base = 0x78c00000,
1271 .aux1_base = 0x71900000,
1272 .aux2_base = 0x71910000,
1273 .nvram_machine_id = 0x80,
1274 .machine_id = lx_id,
1275 .iommu_version = 0x04000000,
1276 .max_mem = 0x10000000,
1277 },
1278 /* SS-4 */
1279 {
1280 .iommu_base = 0x10000000,
1281 .tcx_base = 0x50000000,
1282 .cs_base = 0x6c000000,
1283 .slavio_base = 0x70000000,
1284 .ms_kb_base = 0x71000000,
1285 .serial_base = 0x71100000,
1286 .nvram_base = 0x71200000,
1287 .fd_base = 0x71400000,
1288 .counter_base = 0x71d00000,
1289 .intctl_base = 0x71e00000,
1290 .idreg_base = 0x78000000,
1291 .dma_base = 0x78400000,
1292 .esp_base = 0x78800000,
1293 .le_base = 0x78c00000,
1294 .apc_base = 0x6a000000,
1295 .aux1_base = 0x71900000,
1296 .aux2_base = 0x71910000,
1297 .nvram_machine_id = 0x80,
1298 .machine_id = ss4_id,
1299 .iommu_version = 0x05000000,
1300 .max_mem = 0x10000000,
1301 },
1302 /* SPARCClassic */
1303 {
1304 .iommu_base = 0x10000000,
1305 .tcx_base = 0x50000000,
1306 .slavio_base = 0x70000000,
1307 .ms_kb_base = 0x71000000,
1308 .serial_base = 0x71100000,
1309 .nvram_base = 0x71200000,
1310 .fd_base = 0x71400000,
1311 .counter_base = 0x71d00000,
1312 .intctl_base = 0x71e00000,
1313 .idreg_base = 0x78000000,
1314 .dma_base = 0x78400000,
1315 .esp_base = 0x78800000,
1316 .le_base = 0x78c00000,
1317 .apc_base = 0x6a000000,
1318 .aux1_base = 0x71900000,
1319 .aux2_base = 0x71910000,
1320 .nvram_machine_id = 0x80,
1321 .machine_id = scls_id,
1322 .iommu_version = 0x05000000,
1323 .max_mem = 0x10000000,
1324 },
1325 /* SPARCbook */
1326 {
1327 .iommu_base = 0x10000000,
1328 .tcx_base = 0x50000000, // XXX
1329 .slavio_base = 0x70000000,
1330 .ms_kb_base = 0x71000000,
1331 .serial_base = 0x71100000,
1332 .nvram_base = 0x71200000,
1333 .fd_base = 0x71400000,
1334 .counter_base = 0x71d00000,
1335 .intctl_base = 0x71e00000,
1336 .idreg_base = 0x78000000,
1337 .dma_base = 0x78400000,
1338 .esp_base = 0x78800000,
1339 .le_base = 0x78c00000,
1340 .apc_base = 0x6a000000,
1341 .aux1_base = 0x71900000,
1342 .aux2_base = 0x71910000,
1343 .nvram_machine_id = 0x80,
1344 .machine_id = sbook_id,
1345 .iommu_version = 0x05000000,
1346 .max_mem = 0x10000000,
1347 },
1348 };
1349
1350 /* SPARCstation 5 hardware initialisation */
1351 static void ss5_init(MachineState *machine)
1352 {
1353 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1354 }
1355
1356 /* SPARCstation 10 hardware initialisation */
1357 static void ss10_init(MachineState *machine)
1358 {
1359 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1360 }
1361
1362 /* SPARCserver 600MP hardware initialisation */
1363 static void ss600mp_init(MachineState *machine)
1364 {
1365 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1366 }
1367
1368 /* SPARCstation 20 hardware initialisation */
1369 static void ss20_init(MachineState *machine)
1370 {
1371 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1372 }
1373
1374 /* SPARCstation Voyager hardware initialisation */
1375 static void vger_init(MachineState *machine)
1376 {
1377 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1378 }
1379
1380 /* SPARCstation LX hardware initialisation */
1381 static void ss_lx_init(MachineState *machine)
1382 {
1383 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1384 }
1385
1386 /* SPARCstation 4 hardware initialisation */
1387 static void ss4_init(MachineState *machine)
1388 {
1389 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1390 }
1391
1392 /* SPARCClassic hardware initialisation */
1393 static void scls_init(MachineState *machine)
1394 {
1395 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1396 }
1397
1398 /* SPARCbook hardware initialisation */
1399 static void sbook_init(MachineState *machine)
1400 {
1401 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1402 }
1403
1404 static void ss5_class_init(ObjectClass *oc, void *data)
1405 {
1406 MachineClass *mc = MACHINE_CLASS(oc);
1407
1408 mc->desc = "Sun4m platform, SPARCstation 5";
1409 mc->init = ss5_init;
1410 mc->block_default_type = IF_SCSI;
1411 mc->is_default = true;
1412 mc->default_boot_order = "c";
1413 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1414 mc->default_display = "tcx";
1415 mc->default_ram_id = "sun4m.ram";
1416 }
1417
1418 static const TypeInfo ss5_type = {
1419 .name = MACHINE_TYPE_NAME("SS-5"),
1420 .parent = TYPE_MACHINE,
1421 .class_init = ss5_class_init,
1422 };
1423
1424 static void ss10_class_init(ObjectClass *oc, void *data)
1425 {
1426 MachineClass *mc = MACHINE_CLASS(oc);
1427
1428 mc->desc = "Sun4m platform, SPARCstation 10";
1429 mc->init = ss10_init;
1430 mc->block_default_type = IF_SCSI;
1431 mc->max_cpus = 4;
1432 mc->default_boot_order = "c";
1433 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1434 mc->default_display = "tcx";
1435 mc->default_ram_id = "sun4m.ram";
1436 }
1437
1438 static const TypeInfo ss10_type = {
1439 .name = MACHINE_TYPE_NAME("SS-10"),
1440 .parent = TYPE_MACHINE,
1441 .class_init = ss10_class_init,
1442 };
1443
1444 static void ss600mp_class_init(ObjectClass *oc, void *data)
1445 {
1446 MachineClass *mc = MACHINE_CLASS(oc);
1447
1448 mc->desc = "Sun4m platform, SPARCserver 600MP";
1449 mc->init = ss600mp_init;
1450 mc->block_default_type = IF_SCSI;
1451 mc->max_cpus = 4;
1452 mc->default_boot_order = "c";
1453 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1454 mc->default_display = "tcx";
1455 mc->default_ram_id = "sun4m.ram";
1456 }
1457
1458 static const TypeInfo ss600mp_type = {
1459 .name = MACHINE_TYPE_NAME("SS-600MP"),
1460 .parent = TYPE_MACHINE,
1461 .class_init = ss600mp_class_init,
1462 };
1463
1464 static void ss20_class_init(ObjectClass *oc, void *data)
1465 {
1466 MachineClass *mc = MACHINE_CLASS(oc);
1467
1468 mc->desc = "Sun4m platform, SPARCstation 20";
1469 mc->init = ss20_init;
1470 mc->block_default_type = IF_SCSI;
1471 mc->max_cpus = 4;
1472 mc->default_boot_order = "c";
1473 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1474 mc->default_display = "tcx";
1475 mc->default_ram_id = "sun4m.ram";
1476 }
1477
1478 static const TypeInfo ss20_type = {
1479 .name = MACHINE_TYPE_NAME("SS-20"),
1480 .parent = TYPE_MACHINE,
1481 .class_init = ss20_class_init,
1482 };
1483
1484 static void voyager_class_init(ObjectClass *oc, void *data)
1485 {
1486 MachineClass *mc = MACHINE_CLASS(oc);
1487
1488 mc->desc = "Sun4m platform, SPARCstation Voyager";
1489 mc->init = vger_init;
1490 mc->block_default_type = IF_SCSI;
1491 mc->default_boot_order = "c";
1492 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1493 mc->default_display = "tcx";
1494 mc->default_ram_id = "sun4m.ram";
1495 }
1496
1497 static const TypeInfo voyager_type = {
1498 .name = MACHINE_TYPE_NAME("Voyager"),
1499 .parent = TYPE_MACHINE,
1500 .class_init = voyager_class_init,
1501 };
1502
1503 static void ss_lx_class_init(ObjectClass *oc, void *data)
1504 {
1505 MachineClass *mc = MACHINE_CLASS(oc);
1506
1507 mc->desc = "Sun4m platform, SPARCstation LX";
1508 mc->init = ss_lx_init;
1509 mc->block_default_type = IF_SCSI;
1510 mc->default_boot_order = "c";
1511 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1512 mc->default_display = "tcx";
1513 mc->default_ram_id = "sun4m.ram";
1514 }
1515
1516 static const TypeInfo ss_lx_type = {
1517 .name = MACHINE_TYPE_NAME("LX"),
1518 .parent = TYPE_MACHINE,
1519 .class_init = ss_lx_class_init,
1520 };
1521
1522 static void ss4_class_init(ObjectClass *oc, void *data)
1523 {
1524 MachineClass *mc = MACHINE_CLASS(oc);
1525
1526 mc->desc = "Sun4m platform, SPARCstation 4";
1527 mc->init = ss4_init;
1528 mc->block_default_type = IF_SCSI;
1529 mc->default_boot_order = "c";
1530 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1531 mc->default_display = "tcx";
1532 mc->default_ram_id = "sun4m.ram";
1533 }
1534
1535 static const TypeInfo ss4_type = {
1536 .name = MACHINE_TYPE_NAME("SS-4"),
1537 .parent = TYPE_MACHINE,
1538 .class_init = ss4_class_init,
1539 };
1540
1541 static void scls_class_init(ObjectClass *oc, void *data)
1542 {
1543 MachineClass *mc = MACHINE_CLASS(oc);
1544
1545 mc->desc = "Sun4m platform, SPARCClassic";
1546 mc->init = scls_init;
1547 mc->block_default_type = IF_SCSI;
1548 mc->default_boot_order = "c";
1549 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1550 mc->default_display = "tcx";
1551 mc->default_ram_id = "sun4m.ram";
1552 }
1553
1554 static const TypeInfo scls_type = {
1555 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1556 .parent = TYPE_MACHINE,
1557 .class_init = scls_class_init,
1558 };
1559
1560 static void sbook_class_init(ObjectClass *oc, void *data)
1561 {
1562 MachineClass *mc = MACHINE_CLASS(oc);
1563
1564 mc->desc = "Sun4m platform, SPARCbook";
1565 mc->init = sbook_init;
1566 mc->block_default_type = IF_SCSI;
1567 mc->default_boot_order = "c";
1568 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1569 mc->default_display = "tcx";
1570 mc->default_ram_id = "sun4m.ram";
1571 }
1572
1573 static const TypeInfo sbook_type = {
1574 .name = MACHINE_TYPE_NAME("SPARCbook"),
1575 .parent = TYPE_MACHINE,
1576 .class_init = sbook_class_init,
1577 };
1578
1579 static void sun4m_register_types(void)
1580 {
1581 type_register_static(&idreg_info);
1582 type_register_static(&afx_info);
1583 type_register_static(&prom_info);
1584 type_register_static(&ram_info);
1585
1586 type_register_static(&ss5_type);
1587 type_register_static(&ss10_type);
1588 type_register_static(&ss600mp_type);
1589 type_register_static(&ss20_type);
1590 type_register_static(&voyager_type);
1591 type_register_static(&ss_lx_type);
1592 type_register_static(&ss4_type);
1593 type_register_static(&scls_type);
1594 type_register_static(&sbook_type);
1595 }
1596
1597 type_init(sun4m_register_types)
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