hw/i386/fw_cfg.c

   1 /*
   2  * QEMU fw_cfg helpers (X86 specific)
   3  *
   4  * Copyright (c) 2019 Red Hat, Inc.
   5  *
   6  * Author:
   7  *   Philippe Mathieu-Daudé <philmd@redhat.com>
   8  *
   9  * SPDX-License-Identifier: GPL-2.0-or-later
  10  *
  11  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  12  * See the COPYING file in the top-level directory.
  13  */
  14
  15 #include "qemu/osdep.h"
  16 #include "sysemu/numa.h"
  17 #include "hw/acpi/acpi.h"
  18 #include "hw/firmware/smbios.h"
  19 #include "hw/i386/fw_cfg.h"
  20 #include "hw/timer/hpet.h"
  21 #include "hw/nvram/fw_cfg.h"
  22 #include "e820_memory_layout.h"
  23 #include "kvm_i386.h"
  24 #include "config-devices.h"
  25
  26 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
  27
  28 const char *fw_cfg_arch_key_name(uint16_t key)
  29 {
  30     static const struct {
  31         uint16_t key;
  32         const char *name;
  33     } fw_cfg_arch_wellknown_keys[] = {
  34         {FW_CFG_ACPI_TABLES, "acpi_tables"},
  35         {FW_CFG_SMBIOS_ENTRIES, "smbios_entries"},
  36         {FW_CFG_IRQ0_OVERRIDE, "irq0_override"},
  37         {FW_CFG_E820_TABLE, "e820_table"},
  38         {FW_CFG_HPET, "hpet"},
  39     };
  40
  41     for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
  42         if (fw_cfg_arch_wellknown_keys[i].key == key) {
  43             return fw_cfg_arch_wellknown_keys[i].name;
  44         }
  45     }
  46     return NULL;
  47 }
  48
  49 void fw_cfg_build_smbios(MachineState *ms, FWCfgState *fw_cfg)
  50 {
  51 #ifdef CONFIG_SMBIOS
  52     uint8_t *smbios_tables, *smbios_anchor;
  53     size_t smbios_tables_len, smbios_anchor_len;
  54     struct smbios_phys_mem_area *mem_array;
  55     unsigned i, array_count;
  56     X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
  57
  58     /* tell smbios about cpuid version and features */
  59     smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
  60
  61     smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len);
  62     if (smbios_tables) {
  63         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
  64                          smbios_tables, smbios_tables_len);
  65     }
  66
  67     /* build the array of physical mem area from e820 table */
  68     mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
  69     for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
  70         uint64_t addr, len;
  71
  72         if (e820_get_entry(i, E820_RAM, &addr, &len)) {
  73             mem_array[array_count].address = addr;
  74             mem_array[array_count].length = len;
  75             array_count++;
  76         }
  77     }
  78     smbios_get_tables(ms, mem_array, array_count,
  79                       &smbios_tables, &smbios_tables_len,
  80                       &smbios_anchor, &smbios_anchor_len);
  81     g_free(mem_array);
  82
  83     if (smbios_anchor) {
  84         fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
  85                         smbios_tables, smbios_tables_len);
  86         fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
  87                         smbios_anchor, smbios_anchor_len);
  88     }
  89 #endif
  90 }
  91
  92 FWCfgState *fw_cfg_arch_create(MachineState *ms,
  93                                       uint16_t boot_cpus,
  94                                       uint16_t apic_id_limit)
  95 {
  96     FWCfgState *fw_cfg;
  97     uint64_t *numa_fw_cfg;
  98     int i;
  99     MachineClass *mc = MACHINE_GET_CLASS(ms);
 100     const CPUArchIdList *cpus = mc->possible_cpu_arch_ids(ms);
 101     int nb_numa_nodes = ms->numa_state->num_nodes;
 102
 103     fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4,
 104                                 &address_space_memory);
 105     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, boot_cpus);
 106
 107     /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
 108      *
 109      * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for
 110      * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table,
 111      * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface
 112      * for CPU hotplug also uses APIC ID and not "CPU index".
 113      * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs",
 114      * but the "limit to the APIC ID values SeaBIOS may see".
 115      *
 116      * So for compatibility reasons with old BIOSes we are stuck with
 117      * "etc/max-cpus" actually being apic_id_limit
 118      */
 119     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, apic_id_limit);
 120     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 121 #ifdef CONFIG_ACPI
 122     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES,
 123                      acpi_tables, acpi_tables_len);
 124 #endif
 125     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
 126
 127     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
 128                      &e820_reserve, sizeof(e820_reserve));
 129     fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
 130                     sizeof(struct e820_entry) * e820_get_num_entries());
 131
 132     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg));
 133     /* allocate memory for the NUMA channel: one (64bit) word for the number
 134      * of nodes, one word for each VCPU->node and one word for each node to
 135      * hold the amount of memory.
 136      */
 137     numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes);
 138     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 139     for (i = 0; i < cpus->len; i++) {
 140         unsigned int apic_id = cpus->cpus[i].arch_id;
 141         assert(apic_id < apic_id_limit);
 142         numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id);
 143     }
 144     for (i = 0; i < nb_numa_nodes; i++) {
 145         numa_fw_cfg[apic_id_limit + 1 + i] =
 146             cpu_to_le64(ms->numa_state->nodes[i].node_mem);
 147     }
 148     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg,
 149                      (1 + apic_id_limit + nb_numa_nodes) *
 150                      sizeof(*numa_fw_cfg));
 151
 152     return fw_cfg;
 153 }
 154
 155 void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg)
 156 {
 157     X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
 158     CPUX86State *env = &cpu->env;
 159     uint32_t unused, ecx, edx;
 160     uint64_t feature_control_bits = 0;
 161     uint64_t *val;
 162
 163     cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx);
 164     if (ecx & CPUID_EXT_VMX) {
 165         feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
 166     }
 167
 168     if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) ==
 169         (CPUID_EXT2_MCE | CPUID_EXT2_MCA) &&
 170         (env->mcg_cap & MCG_LMCE_P)) {
 171         feature_control_bits |= FEATURE_CONTROL_LMCE;
 172     }
 173
 174     if (!feature_control_bits) {
 175         return;
 176     }
 177
 178     val = g_malloc(sizeof(*val));
 179     *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED);
 180     fw_cfg_add_file(fw_cfg, "etc/msr_feature_control", val, sizeof(*val));
 181 }