2 * PowerPC memory access emulation helpers for QEMU.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "exec/exec-all.h"
22 #include "qemu/host-utils.h"
23 #include "exec/helper-proto.h"
25 #include "helper_regs.h"
26 #include "exec/exec-all.h"
27 #include "exec/cpu_ldst.h"
31 static inline bool needs_byteswap(const CPUPPCState
*env
)
33 #if defined(TARGET_WORDS_BIGENDIAN)
40 /*****************************************************************************/
41 /* Memory load and stores */
43 static inline target_ulong
addr_add(CPUPPCState
*env
, target_ulong addr
,
46 #if defined(TARGET_PPC64)
47 if (!msr_is_64bit(env
, env
->msr
)) {
48 return (uint32_t)(addr
+ arg
);
56 void helper_lmw(CPUPPCState
*env
, target_ulong addr
, uint32_t reg
)
58 for (; reg
< 32; reg
++) {
59 if (needs_byteswap(env
)) {
60 env
->gpr
[reg
] = bswap32(cpu_ldl_data(env
, addr
));
62 env
->gpr
[reg
] = cpu_ldl_data(env
, addr
);
64 addr
= addr_add(env
, addr
, 4);
68 void helper_stmw(CPUPPCState
*env
, target_ulong addr
, uint32_t reg
)
70 for (; reg
< 32; reg
++) {
71 if (needs_byteswap(env
)) {
72 cpu_stl_data(env
, addr
, bswap32((uint32_t)env
->gpr
[reg
]));
74 cpu_stl_data(env
, addr
, (uint32_t)env
->gpr
[reg
]);
76 addr
= addr_add(env
, addr
, 4);
80 static void do_lsw(CPUPPCState
*env
, target_ulong addr
, uint32_t nb
,
81 uint32_t reg
, uintptr_t raddr
)
85 for (; nb
> 3; nb
-= 4) {
86 env
->gpr
[reg
] = cpu_ldl_data_ra(env
, addr
, raddr
);
88 addr
= addr_add(env
, addr
, 4);
90 if (unlikely(nb
> 0)) {
92 for (sh
= 24; nb
> 0; nb
--, sh
-= 8) {
93 env
->gpr
[reg
] |= cpu_ldub_data_ra(env
, addr
, raddr
) << sh
;
94 addr
= addr_add(env
, addr
, 1);
99 void helper_lsw(CPUPPCState
*env
, target_ulong addr
, uint32_t nb
, uint32_t reg
)
101 do_lsw(env
, addr
, nb
, reg
, GETPC());
104 /* PPC32 specification says we must generate an exception if
105 * rA is in the range of registers to be loaded.
106 * In an other hand, IBM says this is valid, but rA won't be loaded.
107 * For now, I'll follow the spec...
109 void helper_lswx(CPUPPCState
*env
, target_ulong addr
, uint32_t reg
,
110 uint32_t ra
, uint32_t rb
)
112 if (likely(xer_bc
!= 0)) {
113 int num_used_regs
= (xer_bc
+ 3) / 4;
114 if (unlikely((ra
!= 0 && lsw_reg_in_range(reg
, num_used_regs
, ra
)) ||
115 lsw_reg_in_range(reg
, num_used_regs
, rb
))) {
116 raise_exception_err_ra(env
, POWERPC_EXCP_PROGRAM
,
118 POWERPC_EXCP_INVAL_LSWX
, GETPC());
120 do_lsw(env
, addr
, xer_bc
, reg
, GETPC());
125 void helper_stsw(CPUPPCState
*env
, target_ulong addr
, uint32_t nb
,
130 for (; nb
> 3; nb
-= 4) {
131 cpu_stl_data_ra(env
, addr
, env
->gpr
[reg
], GETPC());
132 reg
= (reg
+ 1) % 32;
133 addr
= addr_add(env
, addr
, 4);
135 if (unlikely(nb
> 0)) {
136 for (sh
= 24; nb
> 0; nb
--, sh
-= 8) {
137 cpu_stb_data_ra(env
, addr
, (env
->gpr
[reg
] >> sh
) & 0xFF, GETPC());
138 addr
= addr_add(env
, addr
, 1);
143 static void do_dcbz(CPUPPCState
*env
, target_ulong addr
, int dcache_line_size
)
147 addr
&= ~(dcache_line_size
- 1);
148 for (i
= 0; i
< dcache_line_size
; i
+= 4) {
149 cpu_stl_data(env
, addr
+ i
, 0);
151 if (env
->reserve_addr
== addr
) {
152 env
->reserve_addr
= (target_ulong
)-1ULL;
156 void helper_dcbz(CPUPPCState
*env
, target_ulong addr
, uint32_t is_dcbzl
)
158 int dcbz_size
= env
->dcache_line_size
;
160 #if defined(TARGET_PPC64)
162 (env
->excp_model
== POWERPC_EXCP_970
) &&
163 ((env
->spr
[SPR_970_HID5
] >> 7) & 0x3) == 1) {
168 /* XXX add e500mc support */
170 do_dcbz(env
, addr
, dcbz_size
);
173 void helper_icbi(CPUPPCState
*env
, target_ulong addr
)
175 addr
&= ~(env
->dcache_line_size
- 1);
176 /* Invalidate one cache line :
177 * PowerPC specification says this is to be treated like a load
178 * (not a fetch) by the MMU. To be sure it will be so,
179 * do the load "by hand".
181 cpu_ldl_data(env
, addr
);
184 /* XXX: to be tested */
185 target_ulong
helper_lscbx(CPUPPCState
*env
, target_ulong addr
, uint32_t reg
,
186 uint32_t ra
, uint32_t rb
)
191 for (i
= 0; i
< xer_bc
; i
++) {
192 c
= cpu_ldub_data(env
, addr
);
193 addr
= addr_add(env
, addr
, 1);
194 /* ra (if not 0) and rb are never modified */
195 if (likely(reg
!= rb
&& (ra
== 0 || reg
!= ra
))) {
196 env
->gpr
[reg
] = (env
->gpr
[reg
] & ~(0xFF << d
)) | (c
<< d
);
198 if (unlikely(c
== xer_cmp
)) {
201 if (likely(d
!= 0)) {
212 /*****************************************************************************/
213 /* Altivec extension helpers */
214 #if defined(HOST_WORDS_BIGENDIAN)
222 /* We use msr_le to determine index ordering in a vector. However,
223 byteswapping is not simply controlled by msr_le. We also need to take
224 into account endianness of the target. This is done for the little-endian
225 PPC64 user-mode target. */
227 #define LVE(name, access, swap, element) \
228 void helper_##name(CPUPPCState *env, ppc_avr_t *r, \
231 size_t n_elems = ARRAY_SIZE(r->element); \
232 int adjust = HI_IDX*(n_elems - 1); \
233 int sh = sizeof(r->element[0]) >> 1; \
234 int index = (addr & 0xf) >> sh; \
236 index = n_elems - index - 1; \
239 if (needs_byteswap(env)) { \
240 r->element[LO_IDX ? index : (adjust - index)] = \
241 swap(access(env, addr, GETPC())); \
243 r->element[LO_IDX ? index : (adjust - index)] = \
244 access(env, addr, GETPC()); \
248 LVE(lvebx
, cpu_ldub_data_ra
, I
, u8
)
249 LVE(lvehx
, cpu_lduw_data_ra
, bswap16
, u16
)
250 LVE(lvewx
, cpu_ldl_data_ra
, bswap32
, u32
)
254 #define STVE(name, access, swap, element) \
255 void helper_##name(CPUPPCState *env, ppc_avr_t *r, \
258 size_t n_elems = ARRAY_SIZE(r->element); \
259 int adjust = HI_IDX * (n_elems - 1); \
260 int sh = sizeof(r->element[0]) >> 1; \
261 int index = (addr & 0xf) >> sh; \
263 index = n_elems - index - 1; \
266 if (needs_byteswap(env)) { \
267 access(env, addr, swap(r->element[LO_IDX ? index : \
268 (adjust - index)]), \
271 access(env, addr, r->element[LO_IDX ? index : \
272 (adjust - index)], GETPC()); \
276 STVE(stvebx
, cpu_stb_data_ra
, I
, u8
)
277 STVE(stvehx
, cpu_stw_data_ra
, bswap16
, u16
)
278 STVE(stvewx
, cpu_stl_data_ra
, bswap32
, u32
)
285 void helper_tbegin(CPUPPCState
*env
)
287 /* As a degenerate implementation, always fail tbegin. The reason
288 * given is "Nesting overflow". The "persistent" bit is set,
289 * providing a hint to the error handler to not retry. The TFIAR
290 * captures the address of the failure, which is this tbegin
291 * instruction. Instruction execution will continue with the
292 * next instruction in memory, which is precisely what we want.
295 env
->spr
[SPR_TEXASR
] =
296 (1ULL << TEXASR_FAILURE_PERSISTENT
) |
297 (1ULL << TEXASR_NESTING_OVERFLOW
) |
298 (msr_hv
<< TEXASR_PRIVILEGE_HV
) |
299 (msr_pr
<< TEXASR_PRIVILEGE_PR
) |
300 (1ULL << TEXASR_FAILURE_SUMMARY
) |
301 (1ULL << TEXASR_TFIAR_EXACT
);
302 env
->spr
[SPR_TFIAR
] = env
->nip
| (msr_hv
<< 1) | msr_pr
;
303 env
->spr
[SPR_TFHAR
] = env
->nip
+ 4;
304 env
->crf
[0] = 0xB; /* 0b1010 = transaction failure */