target-ppc/excp_helper.c

   1 /*
   2  *  PowerPC exception emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "exec/helper-proto.h"
  22 #include "exec/exec-all.h"
  23 #include "exec/cpu_ldst.h"
  24
  25 #include "helper_regs.h"
  26
  27 //#define DEBUG_OP
  28 //#define DEBUG_SOFTWARE_TLB
  29 //#define DEBUG_EXCEPTIONS
  30
  31 #ifdef DEBUG_EXCEPTIONS
  32 #  define LOG_EXCP(...) qemu_log(__VA_ARGS__)
  33 #else
  34 #  define LOG_EXCP(...) do { } while (0)
  35 #endif
  36
  37 /*****************************************************************************/
  38 /* PowerPC Hypercall emulation */
  39
  40 void (*cpu_ppc_hypercall)(PowerPCCPU *);
  41
  42 /*****************************************************************************/
  43 /* Exception processing */
  44 #if defined(CONFIG_USER_ONLY)
  45 void ppc_cpu_do_interrupt(CPUState *cs)
  46 {
  47     PowerPCCPU *cpu = POWERPC_CPU(cs);
  48     CPUPPCState *env = &cpu->env;
  49
  50     cs->exception_index = POWERPC_EXCP_NONE;
  51     env->error_code = 0;
  52 }
  53
  54 static void ppc_hw_interrupt(CPUPPCState *env)
  55 {
  56     CPUState *cs = CPU(ppc_env_get_cpu(env));
  57
  58     cs->exception_index = POWERPC_EXCP_NONE;
  59     env->error_code = 0;
  60 }
  61 #else /* defined(CONFIG_USER_ONLY) */
  62 static inline void dump_syscall(CPUPPCState *env)
  63 {
  64     qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64
  65                   " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64
  66                   " nip=" TARGET_FMT_lx "\n",
  67                   ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
  68                   ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
  69                   ppc_dump_gpr(env, 6), env->nip);
  70 }
  71
  72 /* Note that this function should be greatly optimized
  73  * when called with a constant excp, from ppc_hw_interrupt
  74  */
  75 static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
  76 {
  77     CPUState *cs = CPU(cpu);
  78     CPUPPCState *env = &cpu->env;
  79     target_ulong msr, new_msr, vector;
  80     int srr0, srr1, asrr0, asrr1, lev, ail;
  81     bool lpes0;
  82
  83     qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
  84                   " => %08x (%02x)\n", env->nip, excp, env->error_code);
  85
  86     /* new srr1 value excluding must-be-zero bits */
  87     if (excp_model == POWERPC_EXCP_BOOKE) {
  88         msr = env->msr;
  89     } else {
  90         msr = env->msr & ~0x783f0000ULL;
  91     }
  92
  93     /* new interrupt handler msr preserves existing HV and ME unless
  94      * explicitly overriden
  95      */
  96     new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
  97
  98     /* target registers */
  99     srr0 = SPR_SRR0;
 100     srr1 = SPR_SRR1;
 101     asrr0 = -1;
 102     asrr1 = -1;
 103
 104     /* check for special resume at 0x100 from doze/nap/sleep/winkle on P7/P8 */
 105     if (env->in_pm_state) {
 106         env->in_pm_state = false;
 107
 108         /* Pretend to be returning from doze always as we don't lose state */
 109         msr |= (0x1ull << (63 - 47));
 110
 111         /* Non-machine check are routed to 0x100 with a wakeup cause
 112          * encoded in SRR1
 113          */
 114         if (excp != POWERPC_EXCP_MCHECK) {
 115             switch (excp) {
 116             case POWERPC_EXCP_RESET:
 117                 msr |= 0x4ull << (63 - 45);
 118                 break;
 119             case POWERPC_EXCP_EXTERNAL:
 120                 msr |= 0x8ull << (63 - 45);
 121                 break;
 122             case POWERPC_EXCP_DECR:
 123                 msr |= 0x6ull << (63 - 45);
 124                 break;
 125             case POWERPC_EXCP_SDOOR:
 126                 msr |= 0x5ull << (63 - 45);
 127                 break;
 128             case POWERPC_EXCP_SDOOR_HV:
 129                 msr |= 0x3ull << (63 - 45);
 130                 break;
 131             case POWERPC_EXCP_HV_MAINT:
 132                 msr |= 0xaull << (63 - 45);
 133                 break;
 134             default:
 135                 cpu_abort(cs, "Unsupported exception %d in Power Save mode\n",
 136                           excp);
 137             }
 138             excp = POWERPC_EXCP_RESET;
 139         }
 140     }
 141
 142     /* Exception targetting modifiers
 143      *
 144      * LPES0 is supported on POWER7/8
 145      * LPES1 is not supported (old iSeries mode)
 146      *
 147      * On anything else, we behave as if LPES0 is 1
 148      * (externals don't alter MSR:HV)
 149      *
 150      * AIL is initialized here but can be cleared by
 151      * selected exceptions
 152      */
 153 #if defined(TARGET_PPC64)
 154     if (excp_model == POWERPC_EXCP_POWER7 ||
 155         excp_model == POWERPC_EXCP_POWER8) {
 156         lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
 157         if (excp_model == POWERPC_EXCP_POWER8) {
 158             ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT;
 159         } else {
 160             ail = 0;
 161         }
 162     } else
 163 #endif /* defined(TARGET_PPC64) */
 164     {
 165         lpes0 = true;
 166         ail = 0;
 167     }
 168
 169     /* Hypervisor emulation assistance interrupt only exists on server
 170      * arch 2.05 server or later. We also don't want to generate it if
 171      * we don't have HVB in msr_mask (PAPR mode).
 172      */
 173     if (excp == POWERPC_EXCP_HV_EMU
 174 #if defined(TARGET_PPC64)
 175         && !((env->mmu_model & POWERPC_MMU_64) && (env->msr_mask & MSR_HVB))
 176 #endif /* defined(TARGET_PPC64) */
 177
 178     ) {
 179         excp = POWERPC_EXCP_PROGRAM;
 180     }
 181
 182     switch (excp) {
 183     case POWERPC_EXCP_NONE:
 184         /* Should never happen */
 185         return;
 186     case POWERPC_EXCP_CRITICAL:    /* Critical input                         */
 187         switch (excp_model) {
 188         case POWERPC_EXCP_40x:
 189             srr0 = SPR_40x_SRR2;
 190             srr1 = SPR_40x_SRR3;
 191             break;
 192         case POWERPC_EXCP_BOOKE:
 193             srr0 = SPR_BOOKE_CSRR0;
 194             srr1 = SPR_BOOKE_CSRR1;
 195             break;
 196         case POWERPC_EXCP_G2:
 197             break;
 198         default:
 199             goto excp_invalid;
 200         }
 201         goto store_next;
 202     case POWERPC_EXCP_MCHECK:    /* Machine check exception                  */
 203         if (msr_me == 0) {
 204             /* Machine check exception is not enabled.
 205              * Enter checkstop state.
 206              */
 207             fprintf(stderr, "Machine check while not allowed. "
 208                     "Entering checkstop state\n");
 209             if (qemu_log_separate()) {
 210                 qemu_log("Machine check while not allowed. "
 211                         "Entering checkstop state\n");
 212             }
 213             cs->halted = 1;
 214             cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
 215         }
 216         new_msr |= (target_ulong)MSR_HVB;
 217         ail = 0;
 218
 219         /* machine check exceptions don't have ME set */
 220         new_msr &= ~((target_ulong)1 << MSR_ME);
 221
 222         /* XXX: should also have something loaded in DAR / DSISR */
 223         switch (excp_model) {
 224         case POWERPC_EXCP_40x:
 225             srr0 = SPR_40x_SRR2;
 226             srr1 = SPR_40x_SRR3;
 227             break;
 228         case POWERPC_EXCP_BOOKE:
 229             /* FIXME: choose one or the other based on CPU type */
 230             srr0 = SPR_BOOKE_MCSRR0;
 231             srr1 = SPR_BOOKE_MCSRR1;
 232             asrr0 = SPR_BOOKE_CSRR0;
 233             asrr1 = SPR_BOOKE_CSRR1;
 234             break;
 235         default:
 236             break;
 237         }
 238         goto store_next;
 239     case POWERPC_EXCP_DSI:       /* Data storage exception                   */
 240         LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx
 241                  "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
 242         goto store_next;
 243     case POWERPC_EXCP_ISI:       /* Instruction storage exception            */
 244         LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx
 245                  "\n", msr, env->nip);
 246         msr |= env->error_code;
 247         goto store_next;
 248     case POWERPC_EXCP_EXTERNAL:  /* External input                           */
 249         cs = CPU(cpu);
 250
 251         if (!lpes0) {
 252             new_msr |= (target_ulong)MSR_HVB;
 253             new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
 254             srr0 = SPR_HSRR0;
 255             srr1 = SPR_HSRR1;
 256         }
 257         if (env->mpic_proxy) {
 258             /* IACK the IRQ on delivery */
 259             env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
 260         }
 261         goto store_next;
 262     case POWERPC_EXCP_ALIGN:     /* Alignment exception                      */
 263         /* XXX: this is false */
 264         /* Get rS/rD and rA from faulting opcode */
 265         env->spr[SPR_DSISR] |= (cpu_ldl_code(env, (env->nip - 4))
 266                                 & 0x03FF0000) >> 16;
 267         goto store_next;
 268     case POWERPC_EXCP_PROGRAM:   /* Program exception                        */
 269         switch (env->error_code & ~0xF) {
 270         case POWERPC_EXCP_FP:
 271             if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
 272                 LOG_EXCP("Ignore floating point exception\n");
 273                 cs->exception_index = POWERPC_EXCP_NONE;
 274                 env->error_code = 0;
 275                 return;
 276             }
 277
 278             /* FP exceptions always have NIP pointing to the faulting
 279              * instruction, so always use store_next and claim we are
 280              * precise in the MSR.
 281              */
 282             msr |= 0x00100000;
 283             goto store_next;
 284         case POWERPC_EXCP_INVAL:
 285             LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip);
 286             msr |= 0x00080000;
 287             env->spr[SPR_BOOKE_ESR] = ESR_PIL;
 288             /* Some invalids will have the PC in the right place already */
 289             if (env->error_code & POWERPC_EXCP_INVAL_LSWX) {
 290                 goto store_next;
 291             }
 292             break;
 293         case POWERPC_EXCP_PRIV:
 294             msr |= 0x00040000;
 295             env->spr[SPR_BOOKE_ESR] = ESR_PPR;
 296             break;
 297         case POWERPC_EXCP_TRAP:
 298             msr |= 0x00020000;
 299             env->spr[SPR_BOOKE_ESR] = ESR_PTR;
 300             break;
 301         default:
 302             /* Should never occur */
 303             cpu_abort(cs, "Invalid program exception %d. Aborting\n",
 304                       env->error_code);
 305             break;
 306         }
 307         goto store_current;
 308     case POWERPC_EXCP_HV_EMU:
 309         srr0 = SPR_HSRR0;
 310         srr1 = SPR_HSRR1;
 311         new_msr |= (target_ulong)MSR_HVB;
 312         new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
 313         /* Some invalids will have the PC in the right place already */
 314         if (env->error_code == (POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX)) {
 315                 goto store_next;
 316         }
 317         goto store_current;
 318     case POWERPC_EXCP_FPU:       /* Floating-point unavailable exception     */
 319         goto store_current;
 320     case POWERPC_EXCP_SYSCALL:   /* System call exception                    */
 321         dump_syscall(env);
 322         lev = env->error_code;
 323
 324         /* "PAPR mode" built-in hypercall emulation */
 325         if ((lev == 1) && cpu_ppc_hypercall) {
 326             cpu_ppc_hypercall(cpu);
 327             return;
 328         }
 329         if (lev == 1) {
 330             new_msr |= (target_ulong)MSR_HVB;
 331         }
 332         goto store_next;
 333     case POWERPC_EXCP_APU:       /* Auxiliary processor unavailable          */
 334         goto store_current;
 335     case POWERPC_EXCP_DECR:      /* Decrementer exception                    */
 336         goto store_next;
 337     case POWERPC_EXCP_FIT:       /* Fixed-interval timer interrupt           */
 338         /* FIT on 4xx */
 339         LOG_EXCP("FIT exception\n");
 340         goto store_next;
 341     case POWERPC_EXCP_WDT:       /* Watchdog timer interrupt                 */
 342         LOG_EXCP("WDT exception\n");
 343         switch (excp_model) {
 344         case POWERPC_EXCP_BOOKE:
 345             srr0 = SPR_BOOKE_CSRR0;
 346             srr1 = SPR_BOOKE_CSRR1;
 347             break;
 348         default:
 349             break;
 350         }
 351         goto store_next;
 352     case POWERPC_EXCP_DTLB:      /* Data TLB error                           */
 353         goto store_next;
 354     case POWERPC_EXCP_ITLB:      /* Instruction TLB error                    */
 355         goto store_next;
 356     case POWERPC_EXCP_DEBUG:     /* Debug interrupt                          */
 357         switch (excp_model) {
 358         case POWERPC_EXCP_BOOKE:
 359             /* FIXME: choose one or the other based on CPU type */
 360             srr0 = SPR_BOOKE_DSRR0;
 361             srr1 = SPR_BOOKE_DSRR1;
 362             asrr0 = SPR_BOOKE_CSRR0;
 363             asrr1 = SPR_BOOKE_CSRR1;
 364             break;
 365         default:
 366             break;
 367         }
 368         /* XXX: TODO */
 369         cpu_abort(cs, "Debug exception is not implemented yet !\n");
 370         goto store_next;
 371     case POWERPC_EXCP_SPEU:      /* SPE/embedded floating-point unavailable  */
 372         env->spr[SPR_BOOKE_ESR] = ESR_SPV;
 373         goto store_current;
 374     case POWERPC_EXCP_EFPDI:     /* Embedded floating-point data interrupt   */
 375         /* XXX: TODO */
 376         cpu_abort(cs, "Embedded floating point data exception "
 377                   "is not implemented yet !\n");
 378         env->spr[SPR_BOOKE_ESR] = ESR_SPV;
 379         goto store_next;
 380     case POWERPC_EXCP_EFPRI:     /* Embedded floating-point round interrupt  */
 381         /* XXX: TODO */
 382         cpu_abort(cs, "Embedded floating point round exception "
 383                   "is not implemented yet !\n");
 384         env->spr[SPR_BOOKE_ESR] = ESR_SPV;
 385         goto store_next;
 386     case POWERPC_EXCP_EPERFM:    /* Embedded performance monitor interrupt   */
 387         /* XXX: TODO */
 388         cpu_abort(cs,
 389                   "Performance counter exception is not implemented yet !\n");
 390         goto store_next;
 391     case POWERPC_EXCP_DOORI:     /* Embedded doorbell interrupt              */
 392         goto store_next;
 393     case POWERPC_EXCP_DOORCI:    /* Embedded doorbell critical interrupt     */
 394         srr0 = SPR_BOOKE_CSRR0;
 395         srr1 = SPR_BOOKE_CSRR1;
 396         goto store_next;
 397     case POWERPC_EXCP_RESET:     /* System reset exception                   */
 398         if (msr_pow) {
 399             /* indicate that we resumed from power save mode */
 400             msr |= 0x10000;
 401         } else {
 402             new_msr &= ~((target_ulong)1 << MSR_ME);
 403         }
 404
 405         new_msr |= (target_ulong)MSR_HVB;
 406         ail = 0;
 407         goto store_next;
 408     case POWERPC_EXCP_DSEG:      /* Data segment exception                   */
 409         goto store_next;
 410     case POWERPC_EXCP_ISEG:      /* Instruction segment exception            */
 411         goto store_next;
 412     case POWERPC_EXCP_HDECR:     /* Hypervisor decrementer exception         */
 413         srr0 = SPR_HSRR0;
 414         srr1 = SPR_HSRR1;
 415         new_msr |= (target_ulong)MSR_HVB;
 416         new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
 417         goto store_next;
 418     case POWERPC_EXCP_TRACE:     /* Trace exception                          */
 419         goto store_next;
 420     case POWERPC_EXCP_HDSI:      /* Hypervisor data storage exception        */
 421         srr0 = SPR_HSRR0;
 422         srr1 = SPR_HSRR1;
 423         new_msr |= (target_ulong)MSR_HVB;
 424         new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
 425         goto store_next;
 426     case POWERPC_EXCP_HISI:      /* Hypervisor instruction storage exception */
 427         srr0 = SPR_HSRR0;
 428         srr1 = SPR_HSRR1;
 429         new_msr |= (target_ulong)MSR_HVB;
 430         new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
 431         goto store_next;
 432     case POWERPC_EXCP_HDSEG:     /* Hypervisor data segment exception        */
 433         srr0 = SPR_HSRR0;
 434         srr1 = SPR_HSRR1;
 435         new_msr |= (target_ulong)MSR_HVB;
 436         new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
 437         goto store_next;
 438     case POWERPC_EXCP_HISEG:     /* Hypervisor instruction segment exception */
 439         srr0 = SPR_HSRR0;
 440         srr1 = SPR_HSRR1;
 441         new_msr |= (target_ulong)MSR_HVB;
 442         new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
 443         goto store_next;
 444     case POWERPC_EXCP_VPU:       /* Vector unavailable exception             */
 445         goto store_current;
 446     case POWERPC_EXCP_VSXU:       /* VSX unavailable exception               */
 447         goto store_current;
 448     case POWERPC_EXCP_FU:         /* Facility unavailable exception          */
 449         goto store_current;
 450     case POWERPC_EXCP_PIT:       /* Programmable interval timer interrupt    */
 451         LOG_EXCP("PIT exception\n");
 452         goto store_next;
 453     case POWERPC_EXCP_IO:        /* IO error exception                       */
 454         /* XXX: TODO */
 455         cpu_abort(cs, "601 IO error exception is not implemented yet !\n");
 456         goto store_next;
 457     case POWERPC_EXCP_RUNM:      /* Run mode exception                       */
 458         /* XXX: TODO */
 459         cpu_abort(cs, "601 run mode exception is not implemented yet !\n");
 460         goto store_next;
 461     case POWERPC_EXCP_EMUL:      /* Emulation trap exception                 */
 462         /* XXX: TODO */
 463         cpu_abort(cs, "602 emulation trap exception "
 464                   "is not implemented yet !\n");
 465         goto store_next;
 466     case POWERPC_EXCP_IFTLB:     /* Instruction fetch TLB error              */
 467         switch (excp_model) {
 468         case POWERPC_EXCP_602:
 469         case POWERPC_EXCP_603:
 470         case POWERPC_EXCP_603E:
 471         case POWERPC_EXCP_G2:
 472             goto tlb_miss_tgpr;
 473         case POWERPC_EXCP_7x5:
 474             goto tlb_miss;
 475         case POWERPC_EXCP_74xx:
 476             goto tlb_miss_74xx;
 477         default:
 478             cpu_abort(cs, "Invalid instruction TLB miss exception\n");
 479             break;
 480         }
 481         break;
 482     case POWERPC_EXCP_DLTLB:     /* Data load TLB miss                       */
 483         switch (excp_model) {
 484         case POWERPC_EXCP_602:
 485         case POWERPC_EXCP_603:
 486         case POWERPC_EXCP_603E:
 487         case POWERPC_EXCP_G2:
 488             goto tlb_miss_tgpr;
 489         case POWERPC_EXCP_7x5:
 490             goto tlb_miss;
 491         case POWERPC_EXCP_74xx:
 492             goto tlb_miss_74xx;
 493         default:
 494             cpu_abort(cs, "Invalid data load TLB miss exception\n");
 495             break;
 496         }
 497         break;
 498     case POWERPC_EXCP_DSTLB:     /* Data store TLB miss                      */
 499         switch (excp_model) {
 500         case POWERPC_EXCP_602:
 501         case POWERPC_EXCP_603:
 502         case POWERPC_EXCP_603E:
 503         case POWERPC_EXCP_G2:
 504         tlb_miss_tgpr:
 505             /* Swap temporary saved registers with GPRs */
 506             if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
 507                 new_msr |= (target_ulong)1 << MSR_TGPR;
 508                 hreg_swap_gpr_tgpr(env);
 509             }
 510             goto tlb_miss;
 511         case POWERPC_EXCP_7x5:
 512         tlb_miss:
 513 #if defined(DEBUG_SOFTWARE_TLB)
 514             if (qemu_log_enabled()) {
 515                 const char *es;
 516                 target_ulong *miss, *cmp;
 517                 int en;
 518
 519                 if (excp == POWERPC_EXCP_IFTLB) {
 520                     es = "I";
 521                     en = 'I';
 522                     miss = &env->spr[SPR_IMISS];
 523                     cmp = &env->spr[SPR_ICMP];
 524                 } else {
 525                     if (excp == POWERPC_EXCP_DLTLB) {
 526                         es = "DL";
 527                     } else {
 528                         es = "DS";
 529                     }
 530                     en = 'D';
 531                     miss = &env->spr[SPR_DMISS];
 532                     cmp = &env->spr[SPR_DCMP];
 533                 }
 534                 qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
 535                          TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 "
 536                          TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
 537                          env->spr[SPR_HASH1], env->spr[SPR_HASH2],
 538                          env->error_code);
 539             }
 540 #endif
 541             msr |= env->crf[0] << 28;
 542             msr |= env->error_code; /* key, D/I, S/L bits */
 543             /* Set way using a LRU mechanism */
 544             msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
 545             break;
 546         case POWERPC_EXCP_74xx:
 547         tlb_miss_74xx:
 548 #if defined(DEBUG_SOFTWARE_TLB)
 549             if (qemu_log_enabled()) {
 550                 const char *es;
 551                 target_ulong *miss, *cmp;
 552                 int en;
 553
 554                 if (excp == POWERPC_EXCP_IFTLB) {
 555                     es = "I";
 556                     en = 'I';
 557                     miss = &env->spr[SPR_TLBMISS];
 558                     cmp = &env->spr[SPR_PTEHI];
 559                 } else {
 560                     if (excp == POWERPC_EXCP_DLTLB) {
 561                         es = "DL";
 562                     } else {
 563                         es = "DS";
 564                     }
 565                     en = 'D';
 566                     miss = &env->spr[SPR_TLBMISS];
 567                     cmp = &env->spr[SPR_PTEHI];
 568                 }
 569                 qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
 570                          TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
 571                          env->error_code);
 572             }
 573 #endif
 574             msr |= env->error_code; /* key bit */
 575             break;
 576         default:
 577             cpu_abort(cs, "Invalid data store TLB miss exception\n");
 578             break;
 579         }
 580         goto store_next;
 581     case POWERPC_EXCP_FPA:       /* Floating-point assist exception          */
 582         /* XXX: TODO */
 583         cpu_abort(cs, "Floating point assist exception "
 584                   "is not implemented yet !\n");
 585         goto store_next;
 586     case POWERPC_EXCP_DABR:      /* Data address breakpoint                  */
 587         /* XXX: TODO */
 588         cpu_abort(cs, "DABR exception is not implemented yet !\n");
 589         goto store_next;
 590     case POWERPC_EXCP_IABR:      /* Instruction address breakpoint           */
 591         /* XXX: TODO */
 592         cpu_abort(cs, "IABR exception is not implemented yet !\n");
 593         goto store_next;
 594     case POWERPC_EXCP_SMI:       /* System management interrupt              */
 595         /* XXX: TODO */
 596         cpu_abort(cs, "SMI exception is not implemented yet !\n");
 597         goto store_next;
 598     case POWERPC_EXCP_THERM:     /* Thermal interrupt                        */
 599         /* XXX: TODO */
 600         cpu_abort(cs, "Thermal management exception "
 601                   "is not implemented yet !\n");
 602         goto store_next;
 603     case POWERPC_EXCP_PERFM:     /* Embedded performance monitor interrupt   */
 604         /* XXX: TODO */
 605         cpu_abort(cs,
 606                   "Performance counter exception is not implemented yet !\n");
 607         goto store_next;
 608     case POWERPC_EXCP_VPUA:      /* Vector assist exception                  */
 609         /* XXX: TODO */
 610         cpu_abort(cs, "VPU assist exception is not implemented yet !\n");
 611         goto store_next;
 612     case POWERPC_EXCP_SOFTP:     /* Soft patch exception                     */
 613         /* XXX: TODO */
 614         cpu_abort(cs,
 615                   "970 soft-patch exception is not implemented yet !\n");
 616         goto store_next;
 617     case POWERPC_EXCP_MAINT:     /* Maintenance exception                    */
 618         /* XXX: TODO */
 619         cpu_abort(cs,
 620                   "970 maintenance exception is not implemented yet !\n");
 621         goto store_next;
 622     case POWERPC_EXCP_MEXTBR:    /* Maskable external breakpoint             */
 623         /* XXX: TODO */
 624         cpu_abort(cs, "Maskable external exception "
 625                   "is not implemented yet !\n");
 626         goto store_next;
 627     case POWERPC_EXCP_NMEXTBR:   /* Non maskable external breakpoint         */
 628         /* XXX: TODO */
 629         cpu_abort(cs, "Non maskable external exception "
 630                   "is not implemented yet !\n");
 631         goto store_next;
 632     default:
 633     excp_invalid:
 634         cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
 635         break;
 636     store_current:
 637         /* save current instruction location */
 638         env->spr[srr0] = env->nip - 4;
 639         break;
 640     store_next:
 641         /* save next instruction location */
 642         env->spr[srr0] = env->nip;
 643         break;
 644     }
 645     /* Save MSR */
 646     env->spr[srr1] = msr;
 647
 648     /* Sanity check */
 649     if (!(env->msr_mask & MSR_HVB) && (srr0 == SPR_HSRR0)) {
 650         cpu_abort(cs, "Trying to deliver HV exception %d with "
 651                   "no HV support\n", excp);
 652     }
 653
 654     /* If any alternate SRR register are defined, duplicate saved values */
 655     if (asrr0 != -1) {
 656         env->spr[asrr0] = env->spr[srr0];
 657     }
 658     if (asrr1 != -1) {
 659         env->spr[asrr1] = env->spr[srr1];
 660     }
 661
 662     /* Sort out endianness of interrupt, this differs depending on the
 663      * CPU, the HV mode, etc...
 664      */
 665 #ifdef TARGET_PPC64
 666     if (excp_model == POWERPC_EXCP_POWER7) {
 667         if (!(new_msr & MSR_HVB) && (env->spr[SPR_LPCR] & LPCR_ILE)) {
 668             new_msr |= (target_ulong)1 << MSR_LE;
 669         }
 670     } else if (excp_model == POWERPC_EXCP_POWER8) {
 671         if (new_msr & MSR_HVB) {
 672             if (env->spr[SPR_HID0] & HID0_HILE) {
 673                 new_msr |= (target_ulong)1 << MSR_LE;
 674             }
 675         } else if (env->spr[SPR_LPCR] & LPCR_ILE) {
 676             new_msr |= (target_ulong)1 << MSR_LE;
 677         }
 678     } else if (msr_ile) {
 679         new_msr |= (target_ulong)1 << MSR_LE;
 680     }
 681 #else
 682     if (msr_ile) {
 683         new_msr |= (target_ulong)1 << MSR_LE;
 684     }
 685 #endif
 686
 687     /* Jump to handler */
 688     vector = env->excp_vectors[excp];
 689     if (vector == (target_ulong)-1ULL) {
 690         cpu_abort(cs, "Raised an exception without defined vector %d\n",
 691                   excp);
 692     }
 693     vector |= env->excp_prefix;
 694
 695     /* AIL only works if there is no HV transition and we are running with
 696      * translations enabled
 697      */
 698     if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1) ||
 699         ((new_msr & MSR_HVB) && !(msr & MSR_HVB))) {
 700         ail = 0;
 701     }
 702     /* Handle AIL */
 703     if (ail) {
 704         new_msr |= (1 << MSR_IR) | (1 << MSR_DR);
 705         switch(ail) {
 706         case AIL_0001_8000:
 707             vector |= 0x18000;
 708             break;
 709         case AIL_C000_0000_0000_4000:
 710             vector |= 0xc000000000004000ull;
 711             break;
 712         default:
 713             cpu_abort(cs, "Invalid AIL combination %d\n", ail);
 714             break;
 715         }
 716     }
 717
 718 #if defined(TARGET_PPC64)
 719     if (excp_model == POWERPC_EXCP_BOOKE) {
 720         if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
 721             /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
 722             new_msr |= (target_ulong)1 << MSR_CM;
 723         } else {
 724             vector = (uint32_t)vector;
 725         }
 726     } else {
 727         if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) {
 728             vector = (uint32_t)vector;
 729         } else {
 730             new_msr |= (target_ulong)1 << MSR_SF;
 731         }
 732     }
 733 #endif
 734     /* We don't use hreg_store_msr here as already have treated
 735      * any special case that could occur. Just store MSR and update hflags
 736      *
 737      * Note: We *MUST* not use hreg_store_msr() as-is anyway because it
 738      * will prevent setting of the HV bit which some exceptions might need
 739      * to do.
 740      */
 741     env->msr = new_msr & env->msr_mask;
 742     hreg_compute_hflags(env);
 743     env->nip = vector;
 744     /* Reset exception state */
 745     cs->exception_index = POWERPC_EXCP_NONE;
 746     env->error_code = 0;
 747
 748     /* Any interrupt is context synchronizing, check if TCG TLB
 749      * needs a delayed flush on ppc64
 750      */
 751     check_tlb_flush(env);
 752 }
 753
 754 void ppc_cpu_do_interrupt(CPUState *cs)
 755 {
 756     PowerPCCPU *cpu = POWERPC_CPU(cs);
 757     CPUPPCState *env = &cpu->env;
 758
 759     powerpc_excp(cpu, env->excp_model, cs->exception_index);
 760 }
 761
 762 static void ppc_hw_interrupt(CPUPPCState *env)
 763 {
 764     PowerPCCPU *cpu = ppc_env_get_cpu(env);
 765 #if 0
 766     CPUState *cs = CPU(cpu);
 767
 768     qemu_log_mask(CPU_LOG_INT, "%s: %p pending %08x req %08x me %d ee %d\n",
 769                   __func__, env, env->pending_interrupts,
 770                   cs->interrupt_request, (int)msr_me, (int)msr_ee);
 771 #endif
 772     /* External reset */
 773     if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
 774         env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
 775         powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET);
 776         return;
 777     }
 778     /* Machine check exception */
 779     if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
 780         env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
 781         powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_MCHECK);
 782         return;
 783     }
 784 #if 0 /* TODO */
 785     /* External debug exception */
 786     if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
 787         env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
 788         powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DEBUG);
 789         return;
 790     }
 791 #endif
 792     /* Hypervisor decrementer exception */
 793     if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
 794         /* LPCR will be clear when not supported so this will work */
 795         bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE);
 796         if ((msr_ee != 0 || msr_hv == 0) && hdice) {
 797             /* HDEC clears on delivery */
 798             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
 799             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_HDECR);
 800             return;
 801         }
 802     }
 803     /* Extermal interrupt can ignore MSR:EE under some circumstances */
 804     if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
 805         bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
 806         if (msr_ee != 0 || (env->has_hv_mode && msr_hv == 0 && !lpes0)) {
 807             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_EXTERNAL);
 808             return;
 809         }
 810     }
 811     if (msr_ce != 0) {
 812         /* External critical interrupt */
 813         if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
 814             /* Taking a critical external interrupt does not clear the external
 815              * critical interrupt status
 816              */
 817 #if 0
 818             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
 819 #endif
 820             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_CRITICAL);
 821             return;
 822         }
 823     }
 824     if (msr_ee != 0) {
 825         /* Watchdog timer on embedded PowerPC */
 826         if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
 827             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
 828             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_WDT);
 829             return;
 830         }
 831         if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
 832             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
 833             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORCI);
 834             return;
 835         }
 836         /* Fixed interval timer on embedded PowerPC */
 837         if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
 838             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
 839             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_FIT);
 840             return;
 841         }
 842         /* Programmable interval timer on embedded PowerPC */
 843         if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
 844             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
 845             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PIT);
 846             return;
 847         }
 848         /* Decrementer exception */
 849         if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
 850             if (ppc_decr_clear_on_delivery(env)) {
 851                 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
 852             }
 853             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DECR);
 854             return;
 855         }
 856         if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
 857             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
 858             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORI);
 859             return;
 860         }
 861         if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
 862             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
 863             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PERFM);
 864             return;
 865         }
 866         /* Thermal interrupt */
 867         if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
 868             env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
 869             powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_THERM);
 870             return;
 871         }
 872     }
 873 }
 874
 875 void ppc_cpu_do_system_reset(CPUState *cs)
 876 {
 877     PowerPCCPU *cpu = POWERPC_CPU(cs);
 878     CPUPPCState *env = &cpu->env;
 879
 880     powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET);
 881 }
 882 #endif /* !CONFIG_USER_ONLY */
 883
 884 bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 885 {
 886     PowerPCCPU *cpu = POWERPC_CPU(cs);
 887     CPUPPCState *env = &cpu->env;
 888
 889     if (interrupt_request & CPU_INTERRUPT_HARD) {
 890         ppc_hw_interrupt(env);
 891         if (env->pending_interrupts == 0) {
 892             cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
 893         }
 894         return true;
 895     }
 896     return false;
 897 }
 898
 899 #if defined(DEBUG_OP)
 900 static void cpu_dump_rfi(target_ulong RA, target_ulong msr)
 901 {
 902     qemu_log("Return from exception at " TARGET_FMT_lx " with flags "
 903              TARGET_FMT_lx "\n", RA, msr);
 904 }
 905 #endif
 906
 907 /*****************************************************************************/
 908 /* Exceptions processing helpers */
 909
 910 void raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
 911                             uint32_t error_code, uintptr_t raddr)
 912 {
 913     CPUState *cs = CPU(ppc_env_get_cpu(env));
 914
 915     cs->exception_index = exception;
 916     env->error_code = error_code;
 917     cpu_loop_exit_restore(cs, raddr);
 918 }
 919
 920 void raise_exception_err(CPUPPCState *env, uint32_t exception,
 921                          uint32_t error_code)
 922 {
 923     raise_exception_err_ra(env, exception, error_code, 0);
 924 }
 925
 926 void raise_exception(CPUPPCState *env, uint32_t exception)
 927 {
 928     raise_exception_err_ra(env, exception, 0, 0);
 929 }
 930
 931 void raise_exception_ra(CPUPPCState *env, uint32_t exception,
 932                         uintptr_t raddr)
 933 {
 934     raise_exception_err_ra(env, exception, 0, raddr);
 935 }
 936
 937 void helper_raise_exception_err(CPUPPCState *env, uint32_t exception,
 938                                 uint32_t error_code)
 939 {
 940     raise_exception_err_ra(env, exception, error_code, 0);
 941 }
 942
 943 void helper_raise_exception(CPUPPCState *env, uint32_t exception)
 944 {
 945     raise_exception_err_ra(env, exception, 0, 0);
 946 }
 947
 948 #if !defined(CONFIG_USER_ONLY)
 949 void helper_store_msr(CPUPPCState *env, target_ulong val)
 950 {
 951     uint32_t excp = hreg_store_msr(env, val, 0);
 952
 953     if (excp != 0) {
 954         CPUState *cs = CPU(ppc_env_get_cpu(env));
 955         cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
 956         raise_exception(env, excp);
 957     }
 958 }
 959
 960 #if defined(TARGET_PPC64)
 961 void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn)
 962 {
 963     CPUState *cs;
 964
 965     cs = CPU(ppc_env_get_cpu(env));
 966     cs->halted = 1;
 967     env->in_pm_state = true;
 968
 969     /* The architecture specifies that HDEC interrupts are
 970      * discarded in PM states
 971      */
 972     env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
 973
 974     /* Technically, nap doesn't set EE, but if we don't set it
 975      * then ppc_hw_interrupt() won't deliver. We could add some
 976      * other tests there based on LPCR but it's simpler to just
 977      * whack EE in. It will be cleared by the 0x100 at wakeup
 978      * anyway. It will still be observable by the guest in SRR1
 979      * but this doesn't seem to be a problem.
 980      */
 981     env->msr |= (1ull << MSR_EE);
 982     raise_exception(env, EXCP_HLT);
 983 }
 984 #endif /* defined(TARGET_PPC64) */
 985
 986 static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
 987 {
 988     CPUState *cs = CPU(ppc_env_get_cpu(env));
 989
 990     /* MSR:POW cannot be set by any form of rfi */
 991     msr &= ~(1ULL << MSR_POW);
 992
 993 #if defined(TARGET_PPC64)
 994     /* Switching to 32-bit ? Crop the nip */
 995     if (!msr_is_64bit(env, msr)) {
 996         nip = (uint32_t)nip;
 997     }
 998 #else
 999     nip = (uint32_t)nip;
1000 #endif
1001     /* XXX: beware: this is false if VLE is supported */
1002     env->nip = nip & ~((target_ulong)0x00000003);
1003     hreg_store_msr(env, msr, 1);
1004 #if defined(DEBUG_OP)
1005     cpu_dump_rfi(env->nip, env->msr);
1006 #endif
1007     /* No need to raise an exception here,
1008      * as rfi is always the last insn of a TB
1009      */
1010     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
1011
1012     /* Context synchronizing: check if TCG TLB needs flush */
1013     check_tlb_flush(env);
1014 }
1015
1016 void helper_rfi(CPUPPCState *env)
1017 {
1018     do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful);
1019 }
1020
1021 #define MSR_BOOK3S_MASK
1022 #if defined(TARGET_PPC64)
1023 void helper_rfid(CPUPPCState *env)
1024 {
1025     /* The architeture defines a number of rules for which bits
1026      * can change but in practice, we handle this in hreg_store_msr()
1027      * which will be called by do_rfi(), so there is no need to filter
1028      * here
1029      */
1030     do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]);
1031 }
1032
1033 void helper_hrfid(CPUPPCState *env)
1034 {
1035     do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
1036 }
1037 #endif
1038
1039 /*****************************************************************************/
1040 /* Embedded PowerPC specific helpers */
1041 void helper_40x_rfci(CPUPPCState *env)
1042 {
1043     do_rfi(env, env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3]);
1044 }
1045
1046 void helper_rfci(CPUPPCState *env)
1047 {
1048     do_rfi(env, env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1]);
1049 }
1050
1051 void helper_rfdi(CPUPPCState *env)
1052 {
1053     /* FIXME: choose CSRR1 or DSRR1 based on cpu type */
1054     do_rfi(env, env->spr[SPR_BOOKE_DSRR0], env->spr[SPR_BOOKE_DSRR1]);
1055 }
1056
1057 void helper_rfmci(CPUPPCState *env)
1058 {
1059     /* FIXME: choose CSRR1 or MCSRR1 based on cpu type */
1060     do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
1061 }
1062 #endif
1063
1064 void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
1065                uint32_t flags)
1066 {
1067     if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1068                   ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1069                   ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1070                   ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1071                   ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
1072         raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1073     }
1074 }
1075
1076 #if defined(TARGET_PPC64)
1077 void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
1078                uint32_t flags)
1079 {
1080     if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1081                   ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1082                   ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1083                   ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1084                   ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) {
1085         raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1086     }
1087 }
1088 #endif
1089
1090 #if !defined(CONFIG_USER_ONLY)
1091 /*****************************************************************************/
1092 /* PowerPC 601 specific instructions (POWER bridge) */
1093
1094 void helper_rfsvc(CPUPPCState *env)
1095 {
1096     do_rfi(env, env->lr, env->ctr & 0x0000FFFF);
1097 }
1098
1099 /* Embedded.Processor Control */
1100 static int dbell2irq(target_ulong rb)
1101 {
1102     int msg = rb & DBELL_TYPE_MASK;
1103     int irq = -1;
1104
1105     switch (msg) {
1106     case DBELL_TYPE_DBELL:
1107         irq = PPC_INTERRUPT_DOORBELL;
1108         break;
1109     case DBELL_TYPE_DBELL_CRIT:
1110         irq = PPC_INTERRUPT_CDOORBELL;
1111         break;
1112     case DBELL_TYPE_G_DBELL:
1113     case DBELL_TYPE_G_DBELL_CRIT:
1114     case DBELL_TYPE_G_DBELL_MC:
1115         /* XXX implement */
1116     default:
1117         break;
1118     }
1119
1120     return irq;
1121 }
1122
1123 void helper_msgclr(CPUPPCState *env, target_ulong rb)
1124 {
1125     int irq = dbell2irq(rb);
1126
1127     if (irq < 0) {
1128         return;
1129     }
1130
1131     env->pending_interrupts &= ~(1 << irq);
1132 }
1133
1134 void helper_msgsnd(target_ulong rb)
1135 {
1136     int irq = dbell2irq(rb);
1137     int pir = rb & DBELL_PIRTAG_MASK;
1138     CPUState *cs;
1139
1140     if (irq < 0) {
1141         return;
1142     }
1143
1144     CPU_FOREACH(cs) {
1145         PowerPCCPU *cpu = POWERPC_CPU(cs);
1146         CPUPPCState *cenv = &cpu->env;
1147
1148         if ((rb & DBELL_BRDCAST) || (cenv->spr[SPR_BOOKE_PIR] == pir)) {
1149             cenv->pending_interrupts |= 1 << irq;
1150             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
1151         }
1152     }
1153 }
1154 #endif