target-microblaze/cpu.h

   1 /*
   2  *  MicroBlaze virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Edgar E. Iglesias
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_MICROBLAZE_H
  20 #define CPU_MICROBLAZE_H
  21
  22 #include "config.h"
  23 #include "qemu-common.h"
  24
  25 #define TARGET_LONG_BITS 32
  26
  27 #define CPUState struct CPUMBState
  28
  29 #include "cpu-defs.h"
  30 #include "softfloat.h"
  31 struct CPUMBState;
  32 #if !defined(CONFIG_USER_ONLY)
  33 #include "mmu.h"
  34 #endif
  35
  36 #define TARGET_HAS_ICE 1
  37
  38 #define ELF_MACHINE     EM_MICROBLAZE
  39
  40 #define EXCP_NMI        1
  41 #define EXCP_MMU        2
  42 #define EXCP_IRQ        3
  43 #define EXCP_BREAK      4
  44 #define EXCP_HW_BREAK   5
  45 #define EXCP_HW_EXCP    6
  46
  47 /* MicroBlaze-specific interrupt pending bits.  */
  48 #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
  49
  50 /* Register aliases. R0 - R15 */
  51 #define R_SP     1
  52 #define SR_PC    0
  53 #define SR_MSR   1
  54 #define SR_EAR   3
  55 #define SR_ESR   5
  56 #define SR_FSR   7
  57 #define SR_BTR   0xb
  58 #define SR_EDR   0xd
  59
  60 /* MSR flags.  */
  61 #define MSR_BE  (1<<0) /* 0x001 */
  62 #define MSR_IE  (1<<1) /* 0x002 */
  63 #define MSR_C   (1<<2) /* 0x004 */
  64 #define MSR_BIP (1<<3) /* 0x008 */
  65 #define MSR_FSL (1<<4) /* 0x010 */
  66 #define MSR_ICE (1<<5) /* 0x020 */
  67 #define MSR_DZ  (1<<6) /* 0x040 */
  68 #define MSR_DCE (1<<7) /* 0x080 */
  69 #define MSR_EE  (1<<8) /* 0x100 */
  70 #define MSR_EIP (1<<9) /* 0x200 */
  71 #define MSR_PVR (1<<10) /* 0x400 */
  72 #define MSR_CC  (1<<31)
  73
  74 /* Machine State Register (MSR) Fields */
  75 #define MSR_UM (1<<11) /* User Mode */
  76 #define MSR_UMS        (1<<12) /* User Mode Save */
  77 #define MSR_VM (1<<13) /* Virtual Mode */
  78 #define MSR_VMS        (1<<14) /* Virtual Mode Save */
  79
  80 #define MSR_KERNEL      MSR_EE|MSR_VM
  81 //#define MSR_USER     MSR_KERNEL|MSR_UM|MSR_IE
  82 #define MSR_KERNEL_VMS  MSR_EE|MSR_VMS
  83 //#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE
  84
  85 /* Exception State Register (ESR) Fields */
  86 #define          ESR_DIZ       (1<<11) /* Zone Protection */
  87 #define          ESR_S         (1<<10) /* Store instruction */
  88
  89 #define          ESR_ESS_FSL_OFFSET     5
  90
  91 #define          ESR_EC_FSL             0
  92 #define          ESR_EC_UNALIGNED_DATA  1
  93 #define          ESR_EC_ILLEGAL_OP      2
  94 #define          ESR_EC_INSN_BUS        3
  95 #define          ESR_EC_DATA_BUS        4
  96 #define          ESR_EC_DIVZERO         5
  97 #define          ESR_EC_FPU             6
  98 #define          ESR_EC_PRIVINSN        7
  99 #define          ESR_EC_STACKPROT       7  /* Same as PRIVINSN.  */
 100 #define          ESR_EC_DATA_STORAGE    8
 101 #define          ESR_EC_INSN_STORAGE    9
 102 #define          ESR_EC_DATA_TLB        10
 103 #define          ESR_EC_INSN_TLB        11
 104 #define          ESR_EC_MASK            31
 105
 106 /* Floating Point Status Register (FSR) Bits */
 107 #define FSR_IO          (1<<4) /* Invalid operation */
 108 #define FSR_DZ          (1<<3) /* Divide-by-zero */
 109 #define FSR_OF          (1<<2) /* Overflow */
 110 #define FSR_UF          (1<<1) /* Underflow */
 111 #define FSR_DO          (1<<0) /* Denormalized operand error */
 112
 113 /* Version reg.  */
 114 /* Basic PVR mask */
 115 #define PVR0_PVR_FULL_MASK              0x80000000
 116 #define PVR0_USE_BARREL_MASK            0x40000000
 117 #define PVR0_USE_DIV_MASK               0x20000000
 118 #define PVR0_USE_HW_MUL_MASK            0x10000000
 119 #define PVR0_USE_FPU_MASK               0x08000000
 120 #define PVR0_USE_EXC_MASK               0x04000000
 121 #define PVR0_USE_ICACHE_MASK            0x02000000
 122 #define PVR0_USE_DCACHE_MASK            0x01000000
 123 #define PVR0_USE_MMU                    0x00800000      /* new */
 124 #define PVR0_USE_BTC                    0x00400000
 125 #define PVR0_ENDI                       0x00200000
 126 #define PVR0_FAULT                      0x00100000
 127 #define PVR0_VERSION_MASK               0x0000FF00
 128 #define PVR0_USER1_MASK                 0x000000FF
 129
 130 /* User 2 PVR mask */
 131 #define PVR1_USER2_MASK                 0xFFFFFFFF
 132
 133 /* Configuration PVR masks */
 134 #define PVR2_D_OPB_MASK                 0x80000000
 135 #define PVR2_D_LMB_MASK                 0x40000000
 136 #define PVR2_I_OPB_MASK                 0x20000000
 137 #define PVR2_I_LMB_MASK                 0x10000000
 138 #define PVR2_INTERRUPT_IS_EDGE_MASK     0x08000000
 139 #define PVR2_EDGE_IS_POSITIVE_MASK      0x04000000
 140 #define PVR2_D_PLB_MASK                 0x02000000      /* new */
 141 #define PVR2_I_PLB_MASK                 0x01000000      /* new */
 142 #define PVR2_INTERCONNECT               0x00800000      /* new */
 143 #define PVR2_USE_EXTEND_FSL             0x00080000      /* new */
 144 #define PVR2_USE_FSL_EXC                0x00040000      /* new */
 145 #define PVR2_USE_MSR_INSTR              0x00020000
 146 #define PVR2_USE_PCMP_INSTR             0x00010000
 147 #define PVR2_AREA_OPTIMISED             0x00008000
 148 #define PVR2_USE_BARREL_MASK            0x00004000
 149 #define PVR2_USE_DIV_MASK               0x00002000
 150 #define PVR2_USE_HW_MUL_MASK            0x00001000
 151 #define PVR2_USE_FPU_MASK               0x00000800
 152 #define PVR2_USE_MUL64_MASK             0x00000400
 153 #define PVR2_USE_FPU2_MASK              0x00000200      /* new */
 154 #define PVR2_USE_IPLBEXC                0x00000100
 155 #define PVR2_USE_DPLBEXC                0x00000080
 156 #define PVR2_OPCODE_0x0_ILL_MASK        0x00000040
 157 #define PVR2_UNALIGNED_EXC_MASK         0x00000020
 158 #define PVR2_ILL_OPCODE_EXC_MASK        0x00000010
 159 #define PVR2_IOPB_BUS_EXC_MASK          0x00000008
 160 #define PVR2_DOPB_BUS_EXC_MASK          0x00000004
 161 #define PVR2_DIV_ZERO_EXC_MASK          0x00000002
 162 #define PVR2_FPU_EXC_MASK               0x00000001
 163
 164 /* Debug and exception PVR masks */
 165 #define PVR3_DEBUG_ENABLED_MASK         0x80000000
 166 #define PVR3_NUMBER_OF_PC_BRK_MASK      0x1E000000
 167 #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
 168 #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
 169 #define PVR3_FSL_LINKS_MASK             0x00000380
 170
 171 /* ICache config PVR masks */
 172 #define PVR4_USE_ICACHE_MASK            0x80000000
 173 #define PVR4_ICACHE_ADDR_TAG_BITS_MASK  0x7C000000
 174 #define PVR4_ICACHE_USE_FSL_MASK        0x02000000
 175 #define PVR4_ICACHE_ALLOW_WR_MASK       0x01000000
 176 #define PVR4_ICACHE_LINE_LEN_MASK       0x00E00000
 177 #define PVR4_ICACHE_BYTE_SIZE_MASK      0x001F0000
 178
 179 /* DCache config PVR masks */
 180 #define PVR5_USE_DCACHE_MASK            0x80000000
 181 #define PVR5_DCACHE_ADDR_TAG_BITS_MASK  0x7C000000
 182 #define PVR5_DCACHE_USE_FSL_MASK        0x02000000
 183 #define PVR5_DCACHE_ALLOW_WR_MASK       0x01000000
 184 #define PVR5_DCACHE_LINE_LEN_MASK       0x00E00000
 185 #define PVR5_DCACHE_BYTE_SIZE_MASK      0x001F0000
 186 #define PVR5_DCACHE_WRITEBACK_MASK      0x00004000
 187
 188 /* ICache base address PVR mask */
 189 #define PVR6_ICACHE_BASEADDR_MASK       0xFFFFFFFF
 190
 191 /* ICache high address PVR mask */
 192 #define PVR7_ICACHE_HIGHADDR_MASK       0xFFFFFFFF
 193
 194 /* DCache base address PVR mask */
 195 #define PVR8_DCACHE_BASEADDR_MASK       0xFFFFFFFF
 196
 197 /* DCache high address PVR mask */
 198 #define PVR9_DCACHE_HIGHADDR_MASK       0xFFFFFFFF
 199
 200 /* Target family PVR mask */
 201 #define PVR10_TARGET_FAMILY_MASK        0xFF000000
 202
 203 /* MMU descrtiption */
 204 #define PVR11_USE_MMU                   0xC0000000
 205 #define PVR11_MMU_ITLB_SIZE             0x38000000
 206 #define PVR11_MMU_DTLB_SIZE             0x07000000
 207 #define PVR11_MMU_TLB_ACCESS            0x00C00000
 208 #define PVR11_MMU_ZONES                 0x003E0000
 209 /* MSR Reset value PVR mask */
 210 #define PVR11_MSR_RESET_VALUE_MASK      0x000007FF
 211
 212
 213
 214 /* CPU flags.  */
 215
 216 /* Condition codes.  */
 217 #define CC_GE  5
 218 #define CC_GT  4
 219 #define CC_LE  3
 220 #define CC_LT  2
 221 #define CC_NE  1
 222 #define CC_EQ  0
 223
 224 #define NB_MMU_MODES    3
 225
 226 #define STREAM_EXCEPTION (1 << 0)
 227 #define STREAM_ATOMIC    (1 << 1)
 228 #define STREAM_TEST      (1 << 2)
 229 #define STREAM_CONTROL   (1 << 3)
 230 #define STREAM_NONBLOCK  (1 << 4)
 231
 232 typedef struct CPUMBState {
 233     uint32_t debug;
 234     uint32_t btaken;
 235     uint32_t btarget;
 236     uint32_t bimm;
 237
 238     uint32_t imm;
 239     uint32_t regs[33];
 240     uint32_t sregs[24];
 241     float_status fp_status;
 242     /* Stack protectors. Yes, it's a hw feature.  */
 243     uint32_t slr, shr;
 244
 245     /* Internal flags.  */
 246 #define IMM_FLAG        4
 247 #define MSR_EE_FLAG     (1 << 8)
 248 #define DRTI_FLAG       (1 << 16)
 249 #define DRTE_FLAG       (1 << 17)
 250 #define DRTB_FLAG       (1 << 18)
 251 #define D_FLAG          (1 << 19)  /* Bit in ESR.  */
 252 /* TB dependent CPUState.  */
 253 #define IFLAGS_TB_MASK  (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
 254     uint32_t iflags;
 255
 256     struct {
 257         uint32_t regs[16];
 258     } pvr;
 259
 260 #if !defined(CONFIG_USER_ONLY)
 261     /* Unified MMU.  */
 262     struct microblaze_mmu mmu;
 263 #endif
 264
 265     CPU_COMMON
 266 } CPUMBState;
 267
 268 CPUState *cpu_mb_init(const char *cpu_model);
 269 int cpu_mb_exec(CPUState *s);
 270 void cpu_mb_close(CPUState *s);
 271 void do_interrupt(CPUState *env);
 272 /* you can call this signal handler from your SIGBUS and SIGSEGV
 273    signal handlers to inform the virtual CPU of exceptions. non zero
 274    is returned if the signal was handled by the virtual CPU.  */
 275 int cpu_mb_signal_handler(int host_signum, void *pinfo,
 276                           void *puc);
 277
 278 enum {
 279     CC_OP_DYNAMIC, /* Use env->cc_op  */
 280     CC_OP_FLAGS,
 281     CC_OP_CMP,
 282 };
 283
 284 /* FIXME: MB uses variable pages down to 1K but linux only uses 4k.  */
 285 #define TARGET_PAGE_BITS 12
 286 #define MMAP_SHIFT TARGET_PAGE_BITS
 287
 288 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 289 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 290
 291 #define cpu_init cpu_mb_init
 292 #define cpu_exec cpu_mb_exec
 293 #define cpu_gen_code cpu_mb_gen_code
 294 #define cpu_signal_handler cpu_mb_signal_handler
 295
 296 #define CPU_SAVE_VERSION 1
 297
 298 /* MMU modes definitions */
 299 #define MMU_MODE0_SUFFIX _nommu
 300 #define MMU_MODE1_SUFFIX _kernel
 301 #define MMU_MODE2_SUFFIX _user
 302 #define MMU_NOMMU_IDX   0
 303 #define MMU_KERNEL_IDX  1
 304 #define MMU_USER_IDX    2
 305 /* See NB_MMU_MODES further up the file.  */
 306
 307 static inline int cpu_mmu_index (CPUState *env)
 308 {
 309         /* Are we in nommu mode?.  */
 310         if (!(env->sregs[SR_MSR] & MSR_VM))
 311             return MMU_NOMMU_IDX;
 312
 313         if (env->sregs[SR_MSR] & MSR_UM)
 314             return MMU_USER_IDX;
 315         return MMU_KERNEL_IDX;
 316 }
 317
 318 int cpu_mb_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
 319                             int mmu_idx);
 320 #define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault
 321
 322 #if defined(CONFIG_USER_ONLY)
 323 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 324 {
 325     if (newsp)
 326         env->regs[R_SP] = newsp;
 327     env->regs[3] = 0;
 328 }
 329 #endif
 330
 331 static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
 332 {
 333 }
 334
 335 static inline int cpu_interrupts_enabled(CPUState *env)
 336 {
 337     return env->sregs[SR_MSR] & MSR_IE;
 338 }
 339
 340 #include "cpu-all.h"
 341
 342 static inline target_ulong cpu_get_pc(CPUState *env)
 343 {
 344     return env->sregs[SR_PC];
 345 }
 346
 347 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 348                                         target_ulong *cs_base, int *flags)
 349 {
 350     *pc = env->sregs[SR_PC];
 351     *cs_base = 0;
 352     *flags = (env->iflags & IFLAGS_TB_MASK) |
 353                  (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
 354 }
 355
 356 #if !defined(CONFIG_USER_ONLY)
 357 void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
 358                            int is_write, int is_exec, int is_asi, int size);
 359 #endif
 360
 361 static inline bool cpu_has_work(CPUState *env)
 362 {
 363     return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
 364 }
 365
 366 #include "exec-all.h"
 367
 368 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 369 {
 370     env->sregs[SR_PC] = tb->pc;
 371 }
 372
 373 #endif