hw/char/parallel.c

   1 /*
   2  * QEMU Parallel PORT emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  * Copyright (c) 2007 Marko Kohtala
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "qemu/osdep.h"
  26 #include "hw/hw.h"
  27 #include "sysemu/char.h"
  28 #include "hw/isa/isa.h"
  29 #include "hw/i386/pc.h"
  30 #include "sysemu/sysemu.h"
  31
  32 //#define DEBUG_PARALLEL
  33
  34 #ifdef DEBUG_PARALLEL
  35 #define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__)
  36 #else
  37 #define pdebug(fmt, ...) ((void)0)
  38 #endif
  39
  40 #define PARA_REG_DATA 0
  41 #define PARA_REG_STS 1
  42 #define PARA_REG_CTR 2
  43 #define PARA_REG_EPP_ADDR 3
  44 #define PARA_REG_EPP_DATA 4
  45
  46 /*
  47  * These are the definitions for the Printer Status Register
  48  */
  49 #define PARA_STS_BUSY   0x80    /* Busy complement */
  50 #define PARA_STS_ACK    0x40    /* Acknowledge */
  51 #define PARA_STS_PAPER  0x20    /* Out of paper */
  52 #define PARA_STS_ONLINE 0x10    /* Online */
  53 #define PARA_STS_ERROR  0x08    /* Error complement */
  54 #define PARA_STS_TMOUT  0x01    /* EPP timeout */
  55
  56 /*
  57  * These are the definitions for the Printer Control Register
  58  */
  59 #define PARA_CTR_DIR    0x20    /* Direction (1=read, 0=write) */
  60 #define PARA_CTR_INTEN  0x10    /* IRQ Enable */
  61 #define PARA_CTR_SELECT 0x08    /* Select In complement */
  62 #define PARA_CTR_INIT   0x04    /* Initialize Printer complement */
  63 #define PARA_CTR_AUTOLF 0x02    /* Auto linefeed complement */
  64 #define PARA_CTR_STROBE 0x01    /* Strobe complement */
  65
  66 #define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)
  67
  68 typedef struct ParallelState {
  69     MemoryRegion iomem;
  70     uint8_t dataw;
  71     uint8_t datar;
  72     uint8_t status;
  73     uint8_t control;
  74     qemu_irq irq;
  75     int irq_pending;
  76     CharDriverState *chr;
  77     int hw_driver;
  78     int epp_timeout;
  79     uint32_t last_read_offset; /* For debugging */
  80     /* Memory-mapped interface */
  81     int it_shift;
  82 } ParallelState;
  83
  84 #define TYPE_ISA_PARALLEL "isa-parallel"
  85 #define ISA_PARALLEL(obj) \
  86     OBJECT_CHECK(ISAParallelState, (obj), TYPE_ISA_PARALLEL)
  87
  88 typedef struct ISAParallelState {
  89     ISADevice parent_obj;
  90
  91     uint32_t index;
  92     uint32_t iobase;
  93     uint32_t isairq;
  94     ParallelState state;
  95 } ISAParallelState;
  96
  97 static void parallel_update_irq(ParallelState *s)
  98 {
  99     if (s->irq_pending)
 100         qemu_irq_raise(s->irq);
 101     else
 102         qemu_irq_lower(s->irq);
 103 }
 104
 105 static void
 106 parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
 107 {
 108     ParallelState *s = opaque;
 109
 110     pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
 111
 112     addr &= 7;
 113     switch(addr) {
 114     case PARA_REG_DATA:
 115         s->dataw = val;
 116         parallel_update_irq(s);
 117         break;
 118     case PARA_REG_CTR:
 119         val |= 0xc0;
 120         if ((val & PARA_CTR_INIT) == 0 ) {
 121             s->status = PARA_STS_BUSY;
 122             s->status |= PARA_STS_ACK;
 123             s->status |= PARA_STS_ONLINE;
 124             s->status |= PARA_STS_ERROR;
 125         }
 126         else if (val & PARA_CTR_SELECT) {
 127             if (val & PARA_CTR_STROBE) {
 128                 s->status &= ~PARA_STS_BUSY;
 129                 if ((s->control & PARA_CTR_STROBE) == 0)
 130                     qemu_chr_fe_write(s->chr, &s->dataw, 1);
 131             } else {
 132                 if (s->control & PARA_CTR_INTEN) {
 133                     s->irq_pending = 1;
 134                 }
 135             }
 136         }
 137         parallel_update_irq(s);
 138         s->control = val;
 139         break;
 140     }
 141 }
 142
 143 static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
 144 {
 145     ParallelState *s = opaque;
 146     uint8_t parm = val;
 147     int dir;
 148
 149     /* Sometimes programs do several writes for timing purposes on old
 150        HW. Take care not to waste time on writes that do nothing. */
 151
 152     s->last_read_offset = ~0U;
 153
 154     addr &= 7;
 155     switch(addr) {
 156     case PARA_REG_DATA:
 157         if (s->dataw == val)
 158             return;
 159         pdebug("wd%02x\n", val);
 160         qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
 161         s->dataw = val;
 162         break;
 163     case PARA_REG_STS:
 164         pdebug("ws%02x\n", val);
 165         if (val & PARA_STS_TMOUT)
 166             s->epp_timeout = 0;
 167         break;
 168     case PARA_REG_CTR:
 169         val |= 0xc0;
 170         if (s->control == val)
 171             return;
 172         pdebug("wc%02x\n", val);
 173
 174         if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
 175             if (val & PARA_CTR_DIR) {
 176                 dir = 1;
 177             } else {
 178                 dir = 0;
 179             }
 180             qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
 181             parm &= ~PARA_CTR_DIR;
 182         }
 183
 184         qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
 185         s->control = val;
 186         break;
 187     case PARA_REG_EPP_ADDR:
 188         if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
 189             /* Controls not correct for EPP address cycle, so do nothing */
 190             pdebug("wa%02x s\n", val);
 191         else {
 192             struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
 193             if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
 194                 s->epp_timeout = 1;
 195                 pdebug("wa%02x t\n", val);
 196             }
 197             else
 198                 pdebug("wa%02x\n", val);
 199         }
 200         break;
 201     case PARA_REG_EPP_DATA:
 202         if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
 203             /* Controls not correct for EPP data cycle, so do nothing */
 204             pdebug("we%02x s\n", val);
 205         else {
 206             struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
 207             if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
 208                 s->epp_timeout = 1;
 209                 pdebug("we%02x t\n", val);
 210             }
 211             else
 212                 pdebug("we%02x\n", val);
 213         }
 214         break;
 215     }
 216 }
 217
 218 static void
 219 parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
 220 {
 221     ParallelState *s = opaque;
 222     uint16_t eppdata = cpu_to_le16(val);
 223     int err;
 224     struct ParallelIOArg ioarg = {
 225         .buffer = &eppdata, .count = sizeof(eppdata)
 226     };
 227     if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
 228         /* Controls not correct for EPP data cycle, so do nothing */
 229         pdebug("we%04x s\n", val);
 230         return;
 231     }
 232     err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
 233     if (err) {
 234         s->epp_timeout = 1;
 235         pdebug("we%04x t\n", val);
 236     }
 237     else
 238         pdebug("we%04x\n", val);
 239 }
 240
 241 static void
 242 parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
 243 {
 244     ParallelState *s = opaque;
 245     uint32_t eppdata = cpu_to_le32(val);
 246     int err;
 247     struct ParallelIOArg ioarg = {
 248         .buffer = &eppdata, .count = sizeof(eppdata)
 249     };
 250     if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
 251         /* Controls not correct for EPP data cycle, so do nothing */
 252         pdebug("we%08x s\n", val);
 253         return;
 254     }
 255     err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
 256     if (err) {
 257         s->epp_timeout = 1;
 258         pdebug("we%08x t\n", val);
 259     }
 260     else
 261         pdebug("we%08x\n", val);
 262 }
 263
 264 static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
 265 {
 266     ParallelState *s = opaque;
 267     uint32_t ret = 0xff;
 268
 269     addr &= 7;
 270     switch(addr) {
 271     case PARA_REG_DATA:
 272         if (s->control & PARA_CTR_DIR)
 273             ret = s->datar;
 274         else
 275             ret = s->dataw;
 276         break;
 277     case PARA_REG_STS:
 278         ret = s->status;
 279         s->irq_pending = 0;
 280         if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
 281             /* XXX Fixme: wait 5 microseconds */
 282             if (s->status & PARA_STS_ACK)
 283                 s->status &= ~PARA_STS_ACK;
 284             else {
 285                 /* XXX Fixme: wait 5 microseconds */
 286                 s->status |= PARA_STS_ACK;
 287                 s->status |= PARA_STS_BUSY;
 288             }
 289         }
 290         parallel_update_irq(s);
 291         break;
 292     case PARA_REG_CTR:
 293         ret = s->control;
 294         break;
 295     }
 296     pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
 297     return ret;
 298 }
 299
 300 static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
 301 {
 302     ParallelState *s = opaque;
 303     uint8_t ret = 0xff;
 304     addr &= 7;
 305     switch(addr) {
 306     case PARA_REG_DATA:
 307         qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
 308         if (s->last_read_offset != addr || s->datar != ret)
 309             pdebug("rd%02x\n", ret);
 310         s->datar = ret;
 311         break;
 312     case PARA_REG_STS:
 313         qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
 314         ret &= ~PARA_STS_TMOUT;
 315         if (s->epp_timeout)
 316             ret |= PARA_STS_TMOUT;
 317         if (s->last_read_offset != addr || s->status != ret)
 318             pdebug("rs%02x\n", ret);
 319         s->status = ret;
 320         break;
 321     case PARA_REG_CTR:
 322         /* s->control has some bits fixed to 1. It is zero only when
 323            it has not been yet written to.  */
 324         if (s->control == 0) {
 325             qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
 326             if (s->last_read_offset != addr)
 327                 pdebug("rc%02x\n", ret);
 328             s->control = ret;
 329         }
 330         else {
 331             ret = s->control;
 332             if (s->last_read_offset != addr)
 333                 pdebug("rc%02x\n", ret);
 334         }
 335         break;
 336     case PARA_REG_EPP_ADDR:
 337         if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
 338             /* Controls not correct for EPP addr cycle, so do nothing */
 339             pdebug("ra%02x s\n", ret);
 340         else {
 341             struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
 342             if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
 343                 s->epp_timeout = 1;
 344                 pdebug("ra%02x t\n", ret);
 345             }
 346             else
 347                 pdebug("ra%02x\n", ret);
 348         }
 349         break;
 350     case PARA_REG_EPP_DATA:
 351         if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
 352             /* Controls not correct for EPP data cycle, so do nothing */
 353             pdebug("re%02x s\n", ret);
 354         else {
 355             struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
 356             if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
 357                 s->epp_timeout = 1;
 358                 pdebug("re%02x t\n", ret);
 359             }
 360             else
 361                 pdebug("re%02x\n", ret);
 362         }
 363         break;
 364     }
 365     s->last_read_offset = addr;
 366     return ret;
 367 }
 368
 369 static uint32_t
 370 parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
 371 {
 372     ParallelState *s = opaque;
 373     uint32_t ret;
 374     uint16_t eppdata = ~0;
 375     int err;
 376     struct ParallelIOArg ioarg = {
 377         .buffer = &eppdata, .count = sizeof(eppdata)
 378     };
 379     if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
 380         /* Controls not correct for EPP data cycle, so do nothing */
 381         pdebug("re%04x s\n", eppdata);
 382         return eppdata;
 383     }
 384     err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
 385     ret = le16_to_cpu(eppdata);
 386
 387     if (err) {
 388         s->epp_timeout = 1;
 389         pdebug("re%04x t\n", ret);
 390     }
 391     else
 392         pdebug("re%04x\n", ret);
 393     return ret;
 394 }
 395
 396 static uint32_t
 397 parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
 398 {
 399     ParallelState *s = opaque;
 400     uint32_t ret;
 401     uint32_t eppdata = ~0U;
 402     int err;
 403     struct ParallelIOArg ioarg = {
 404         .buffer = &eppdata, .count = sizeof(eppdata)
 405     };
 406     if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
 407         /* Controls not correct for EPP data cycle, so do nothing */
 408         pdebug("re%08x s\n", eppdata);
 409         return eppdata;
 410     }
 411     err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
 412     ret = le32_to_cpu(eppdata);
 413
 414     if (err) {
 415         s->epp_timeout = 1;
 416         pdebug("re%08x t\n", ret);
 417     }
 418     else
 419         pdebug("re%08x\n", ret);
 420     return ret;
 421 }
 422
 423 static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
 424 {
 425     pdebug("wecp%d=%02x\n", addr & 7, val);
 426 }
 427
 428 static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
 429 {
 430     uint8_t ret = 0xff;
 431
 432     pdebug("recp%d:%02x\n", addr & 7, ret);
 433     return ret;
 434 }
 435
 436 static void parallel_reset(void *opaque)
 437 {
 438     ParallelState *s = opaque;
 439
 440     s->datar = ~0;
 441     s->dataw = ~0;
 442     s->status = PARA_STS_BUSY;
 443     s->status |= PARA_STS_ACK;
 444     s->status |= PARA_STS_ONLINE;
 445     s->status |= PARA_STS_ERROR;
 446     s->status |= PARA_STS_TMOUT;
 447     s->control = PARA_CTR_SELECT;
 448     s->control |= PARA_CTR_INIT;
 449     s->control |= 0xc0;
 450     s->irq_pending = 0;
 451     s->hw_driver = 0;
 452     s->epp_timeout = 0;
 453     s->last_read_offset = ~0U;
 454 }
 455
 456 static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 457
 458 static const MemoryRegionPortio isa_parallel_portio_hw_list[] = {
 459     { 0, 8, 1,
 460       .read = parallel_ioport_read_hw,
 461       .write = parallel_ioport_write_hw },
 462     { 4, 1, 2,
 463       .read = parallel_ioport_eppdata_read_hw2,
 464       .write = parallel_ioport_eppdata_write_hw2 },
 465     { 4, 1, 4,
 466       .read = parallel_ioport_eppdata_read_hw4,
 467       .write = parallel_ioport_eppdata_write_hw4 },
 468     { 0x400, 8, 1,
 469       .read = parallel_ioport_ecp_read,
 470       .write = parallel_ioport_ecp_write },
 471     PORTIO_END_OF_LIST(),
 472 };
 473
 474 static const MemoryRegionPortio isa_parallel_portio_sw_list[] = {
 475     { 0, 8, 1,
 476       .read = parallel_ioport_read_sw,
 477       .write = parallel_ioport_write_sw },
 478     PORTIO_END_OF_LIST(),
 479 };
 480
 481
 482 static const VMStateDescription vmstate_parallel_isa = {
 483     .name = "parallel_isa",
 484     .version_id = 1,
 485     .minimum_version_id = 1,
 486     .fields      = (VMStateField[]) {
 487         VMSTATE_UINT8(state.dataw, ISAParallelState),
 488         VMSTATE_UINT8(state.datar, ISAParallelState),
 489         VMSTATE_UINT8(state.status, ISAParallelState),
 490         VMSTATE_UINT8(state.control, ISAParallelState),
 491         VMSTATE_INT32(state.irq_pending, ISAParallelState),
 492         VMSTATE_INT32(state.epp_timeout, ISAParallelState),
 493         VMSTATE_END_OF_LIST()
 494     }
 495 };
 496
 497
 498 static void parallel_isa_realizefn(DeviceState *dev, Error **errp)
 499 {
 500     static int index;
 501     ISADevice *isadev = ISA_DEVICE(dev);
 502     ISAParallelState *isa = ISA_PARALLEL(dev);
 503     ParallelState *s = &isa->state;
 504     int base;
 505     uint8_t dummy;
 506
 507     if (!s->chr) {
 508         error_setg(errp, "Can't create parallel device, empty char device");
 509         return;
 510     }
 511
 512     if (isa->index == -1) {
 513         isa->index = index;
 514     }
 515     if (isa->index >= MAX_PARALLEL_PORTS) {
 516         error_setg(errp, "Max. supported number of parallel ports is %d.",
 517                    MAX_PARALLEL_PORTS);
 518         return;
 519     }
 520     if (isa->iobase == -1) {
 521         isa->iobase = isa_parallel_io[isa->index];
 522     }
 523     index++;
 524
 525     base = isa->iobase;
 526     isa_init_irq(isadev, &s->irq, isa->isairq);
 527     qemu_register_reset(parallel_reset, s);
 528
 529     if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
 530         s->hw_driver = 1;
 531         s->status = dummy;
 532     }
 533
 534     isa_register_portio_list(isadev, base,
 535                              (s->hw_driver
 536                               ? &isa_parallel_portio_hw_list[0]
 537                               : &isa_parallel_portio_sw_list[0]),
 538                              s, "parallel");
 539 }
 540
 541 /* Memory mapped interface */
 542 static uint32_t parallel_mm_readb (void *opaque, hwaddr addr)
 543 {
 544     ParallelState *s = opaque;
 545
 546     return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF;
 547 }
 548
 549 static void parallel_mm_writeb (void *opaque,
 550                                 hwaddr addr, uint32_t value)
 551 {
 552     ParallelState *s = opaque;
 553
 554     parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
 555 }
 556
 557 static uint32_t parallel_mm_readw (void *opaque, hwaddr addr)
 558 {
 559     ParallelState *s = opaque;
 560
 561     return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF;
 562 }
 563
 564 static void parallel_mm_writew (void *opaque,
 565                                 hwaddr addr, uint32_t value)
 566 {
 567     ParallelState *s = opaque;
 568
 569     parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
 570 }
 571
 572 static uint32_t parallel_mm_readl (void *opaque, hwaddr addr)
 573 {
 574     ParallelState *s = opaque;
 575
 576     return parallel_ioport_read_sw(s, addr >> s->it_shift);
 577 }
 578
 579 static void parallel_mm_writel (void *opaque,
 580                                 hwaddr addr, uint32_t value)
 581 {
 582     ParallelState *s = opaque;
 583
 584     parallel_ioport_write_sw(s, addr >> s->it_shift, value);
 585 }
 586
 587 static const MemoryRegionOps parallel_mm_ops = {
 588     .old_mmio = {
 589         .read = { parallel_mm_readb, parallel_mm_readw, parallel_mm_readl },
 590         .write = { parallel_mm_writeb, parallel_mm_writew, parallel_mm_writel },
 591     },
 592     .endianness = DEVICE_NATIVE_ENDIAN,
 593 };
 594
 595 /* If fd is zero, it means that the parallel device uses the console */
 596 bool parallel_mm_init(MemoryRegion *address_space,
 597                       hwaddr base, int it_shift, qemu_irq irq,
 598                       CharDriverState *chr)
 599 {
 600     ParallelState *s;
 601
 602     s = g_malloc0(sizeof(ParallelState));
 603     s->irq = irq;
 604     s->chr = chr;
 605     s->it_shift = it_shift;
 606     qemu_register_reset(parallel_reset, s);
 607
 608     memory_region_init_io(&s->iomem, NULL, &parallel_mm_ops, s,
 609                           "parallel", 8 << it_shift);
 610     memory_region_add_subregion(address_space, base, &s->iomem);
 611     return true;
 612 }
 613
 614 static Property parallel_isa_properties[] = {
 615     DEFINE_PROP_UINT32("index", ISAParallelState, index,   -1),
 616     DEFINE_PROP_UINT32("iobase", ISAParallelState, iobase,  -1),
 617     DEFINE_PROP_UINT32("irq",   ISAParallelState, isairq,  7),
 618     DEFINE_PROP_CHR("chardev",  ISAParallelState, state.chr),
 619     DEFINE_PROP_END_OF_LIST(),
 620 };
 621
 622 static void parallel_isa_class_initfn(ObjectClass *klass, void *data)
 623 {
 624     DeviceClass *dc = DEVICE_CLASS(klass);
 625
 626     dc->realize = parallel_isa_realizefn;
 627     dc->vmsd = &vmstate_parallel_isa;
 628     dc->props = parallel_isa_properties;
 629     set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
 630 }
 631
 632 static const TypeInfo parallel_isa_info = {
 633     .name          = TYPE_ISA_PARALLEL,
 634     .parent        = TYPE_ISA_DEVICE,
 635     .instance_size = sizeof(ISAParallelState),
 636     .class_init    = parallel_isa_class_initfn,
 637 };
 638
 639 static void parallel_register_types(void)
 640 {
 641     type_register_static(&parallel_isa_info);
 642 }
 643
 644 type_init(parallel_register_types)