4 #include "sysemu/dma.h"
6 #include "hw/ppc/xics.h"
7 #include "hw/ppc/spapr_drc.h"
8 #include "hw/mem/pc-dimm.h"
9 #include "hw/ppc/spapr_ovec.h"
14 typedef struct sPAPREventLogEntry sPAPREventLogEntry
;
15 typedef struct sPAPREventSource sPAPREventSource
;
16 typedef struct sPAPRPendingHPT sPAPRPendingHPT
;
18 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL
19 #define SPAPR_ENTRY_POINT 0x100
21 #define SPAPR_TIMEBASE_FREQ 512000000ULL
23 #define TYPE_SPAPR_RTC "spapr-rtc"
25 #define SPAPR_RTC(obj) \
26 OBJECT_CHECK(sPAPRRTCState, (obj), TYPE_SPAPR_RTC)
28 typedef struct sPAPRRTCState sPAPRRTCState
;
29 struct sPAPRRTCState
{
31 DeviceState parent_obj
;
35 typedef struct sPAPRDIMMState sPAPRDIMMState
;
36 typedef struct sPAPRMachineClass sPAPRMachineClass
;
38 #define TYPE_SPAPR_MACHINE "spapr-machine"
39 #define SPAPR_MACHINE(obj) \
40 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE)
41 #define SPAPR_MACHINE_GET_CLASS(obj) \
42 OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE)
43 #define SPAPR_MACHINE_CLASS(klass) \
44 OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE)
47 SPAPR_RESIZE_HPT_DEFAULT
= 0,
48 SPAPR_RESIZE_HPT_DISABLED
,
49 SPAPR_RESIZE_HPT_ENABLED
,
50 SPAPR_RESIZE_HPT_REQUIRED
,
57 /* Hardware Transactional Memory */
58 #define SPAPR_CAP_HTM 0x00
59 /* Vector Scalar Extensions */
60 #define SPAPR_CAP_VSX 0x01
61 /* Decimal Floating Point */
62 #define SPAPR_CAP_DFP 0x02
63 /* Cache Flush on Privilege Change */
64 #define SPAPR_CAP_CFPC 0x03
65 /* Speculation Barrier Bounds Checking */
66 #define SPAPR_CAP_SBBC 0x04
67 /* Indirect Branch Serialisation */
68 #define SPAPR_CAP_IBS 0x05
70 #define SPAPR_CAP_NUM (SPAPR_CAP_IBS + 1)
76 #define SPAPR_CAP_OFF 0x00
77 #define SPAPR_CAP_ON 0x01
78 /* Broken | Workaround | Fixed Caps */
79 #define SPAPR_CAP_BROKEN 0x00
80 #define SPAPR_CAP_WORKAROUND 0x01
81 #define SPAPR_CAP_FIXED 0x02
83 typedef struct sPAPRCapabilities sPAPRCapabilities
;
84 struct sPAPRCapabilities
{
85 uint8_t caps
[SPAPR_CAP_NUM
];
91 struct sPAPRMachineClass
{
93 MachineClass parent_class
;
96 bool dr_lmb_enabled
; /* enable dynamic-reconfig/hotplug of LMBs */
97 bool use_ohci_by_default
; /* use USB-OHCI instead of XHCI */
98 bool pre_2_10_has_unused_icps
;
99 void (*phb_placement
)(sPAPRMachineState
*spapr
, uint32_t index
,
100 uint64_t *buid
, hwaddr
*pio
,
101 hwaddr
*mmio32
, hwaddr
*mmio64
,
102 unsigned n_dma
, uint32_t *liobns
, Error
**errp
);
103 sPAPRResizeHPT resize_hpt_default
;
104 sPAPRCapabilities default_caps
;
110 struct sPAPRMachineState
{
112 MachineState parent_obj
;
114 struct VIOsPAPRBus
*vio_bus
;
115 QLIST_HEAD(, sPAPRPHBState
) phbs
;
116 struct sPAPRNVRAM
*nvram
;
120 sPAPRResizeHPT resize_hpt
;
123 uint64_t patb_entry
; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */
124 sPAPRPendingHPT
*pending_hpt
; /* in-progress resize */
132 uint32_t initrd_base
;
134 uint64_t rtc_offset
; /* Now used only during incoming migration */
135 struct PPCTimebase tb
;
137 uint32_t vsmt
; /* Virtual SMT mode (KVM's "core stride") */
139 Notifier epow_notifier
;
140 QTAILQ_HEAD(, sPAPREventLogEntry
) pending_events
;
141 bool use_hotplug_event_source
;
142 sPAPREventSource
*event_sources
;
144 /* ibm,client-architecture-support option negotiation */
146 bool cas_legacy_guest_workaround
;
147 sPAPROptionVector
*ov5
; /* QEMU-supported option vectors */
148 sPAPROptionVector
*ov5_cas
; /* negotiated (via CAS) option vectors */
149 uint32_t max_compat_pvr
;
151 /* Migration state */
153 bool htab_first_pass
;
156 /* Pending DIMM unplug cache. It is populated when a LMB
157 * unplug starts. It can be regenerated if a migration
158 * occurs during the unplug process. */
159 QTAILQ_HEAD(, sPAPRDIMMState
) pending_dimm_unplugs
;
163 MemoryHotplugState hotplug_memory
;
165 const char *icp_type
;
167 bool cmd_line_caps
[SPAPR_CAP_NUM
];
168 sPAPRCapabilities def
, eff
, mig
;
172 #define H_BUSY 1 /* Hardware busy -- retry later */
173 #define H_CLOSED 2 /* Resource closed */
174 #define H_NOT_AVAILABLE 3
175 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */
177 #define H_IN_PROGRESS 14 /* Kind of like busy */
178 #define H_PAGE_REGISTERED 15
179 #define H_PARTIAL_STORE 16
180 #define H_PENDING 17 /* returned from H_POLL_PENDING */
181 #define H_CONTINUE 18 /* Returned from H_Join on success */
182 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */
183 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \
184 is a good time to retry */
185 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \
186 is a good time to retry */
187 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \
188 is a good time to retry */
189 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \
190 is a good time to retry */
191 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \
192 is a good time to retry */
193 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \
194 is a good time to retry */
195 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */
196 #define H_HARDWARE -1 /* Hardware error */
197 #define H_FUNCTION -2 /* Function not supported */
198 #define H_PRIVILEGE -3 /* Caller not privileged */
199 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
200 #define H_BAD_MODE -5 /* Illegal msr value */
201 #define H_PTEG_FULL -6 /* PTEG is full */
202 #define H_NOT_FOUND -7 /* PTE was not found" */
203 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */
205 #define H_AUTHORITY -10
206 #define H_PERMISSION -11
207 #define H_DROPPED -12
208 #define H_SOURCE_PARM -13
209 #define H_DEST_PARM -14
210 #define H_REMOTE_PARM -15
211 #define H_RESOURCE -16
212 #define H_ADAPTER_PARM -17
213 #define H_RH_PARM -18
214 #define H_RCQ_PARM -19
215 #define H_SCQ_PARM -20
216 #define H_EQ_PARM -21
217 #define H_RT_PARM -22
218 #define H_ST_PARM -23
219 #define H_SIGT_PARM -24
220 #define H_TOKEN_PARM -25
221 #define H_MLENGTH_PARM -27
222 #define H_MEM_PARM -28
223 #define H_MEM_ACCESS_PARM -29
224 #define H_ATTR_PARM -30
225 #define H_PORT_PARM -31
226 #define H_MCG_PARM -32
227 #define H_VL_PARM -33
228 #define H_TSIZE_PARM -34
229 #define H_TRACE_PARM -35
231 #define H_MASK_PARM -37
232 #define H_MCG_FULL -38
233 #define H_ALIAS_EXIST -39
234 #define H_P_COUNTER -40
235 #define H_TABLE_FULL -41
236 #define H_ALT_TABLE -42
237 #define H_MR_CONDITION -43
238 #define H_NOT_ENOUGH_RESOURCES -44
239 #define H_R_STATE -45
240 #define H_RESCINDEND -46
249 #define H_UNSUPPORTED_FLAG -256
250 #define H_MULTI_THREADS_ACTIVE -9005
253 /* Long Busy is a condition that can be returned by the firmware
254 * when a call cannot be completed now, but the identical call
255 * should be retried later. This prevents calls blocking in the
256 * firmware for long periods of time. Annoyingly the firmware can return
257 * a range of return codes, hinting at how long we should wait before
258 * retrying. If you don't care for the hint, the macro below is a good
259 * way to check for the long_busy return codes
261 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \
262 && (x <= H_LONG_BUSY_END_RANGE))
265 #define H_LARGE_PAGE (1ULL<<(63-16))
266 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */
267 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */
268 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */
269 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
270 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30)))
271 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
272 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
273 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
274 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */
275 #define H_ANDCOND (1ULL<<(63-33))
276 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */
277 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */
278 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */
279 #define H_COPY_PAGE (1ULL<<(63-49))
280 #define H_N (1ULL<<(63-61))
281 #define H_PP1 (1ULL<<(63-62))
282 #define H_PP2 (1ULL<<(63-63))
284 /* Values for 2nd argument to H_SET_MODE */
285 #define H_SET_MODE_RESOURCE_SET_CIABR 1
286 #define H_SET_MODE_RESOURCE_SET_DAWR 2
287 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3
288 #define H_SET_MODE_RESOURCE_LE 4
290 /* Flags for H_SET_MODE_RESOURCE_LE */
291 #define H_SET_MODE_ENDIAN_BIG 0
292 #define H_SET_MODE_ENDIAN_LITTLE 1
295 #define H_VASI_INVALID 0
296 #define H_VASI_ENABLED 1
297 #define H_VASI_ABORTED 2
298 #define H_VASI_SUSPENDING 3
299 #define H_VASI_SUSPENDED 4
300 #define H_VASI_RESUMED 5
301 #define H_VASI_COMPLETED 6
304 #define H_DABRX_HYPERVISOR (1ULL<<(63-61))
305 #define H_DABRX_KERNEL (1ULL<<(63-62))
306 #define H_DABRX_USER (1ULL<<(63-63))
308 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */
309 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0)
310 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1)
311 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2)
312 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3)
313 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4)
314 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5)
315 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6)
316 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0)
317 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1)
318 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2)
320 /* Each control block has to be on a 4K boundary */
321 #define H_CB_ALIGNMENT 4096
323 /* pSeries hypervisor opcodes */
324 #define H_REMOVE 0x04
327 #define H_CLEAR_MOD 0x10
328 #define H_CLEAR_REF 0x14
329 #define H_PROTECT 0x18
330 #define H_GET_TCE 0x1c
331 #define H_PUT_TCE 0x20
332 #define H_SET_SPRG0 0x24
333 #define H_SET_DABR 0x28
334 #define H_PAGE_INIT 0x2c
335 #define H_SET_ASR 0x30
336 #define H_ASR_ON 0x34
337 #define H_ASR_OFF 0x38
338 #define H_LOGICAL_CI_LOAD 0x3c
339 #define H_LOGICAL_CI_STORE 0x40
340 #define H_LOGICAL_CACHE_LOAD 0x44
341 #define H_LOGICAL_CACHE_STORE 0x48
342 #define H_LOGICAL_ICBI 0x4c
343 #define H_LOGICAL_DCBF 0x50
344 #define H_GET_TERM_CHAR 0x54
345 #define H_PUT_TERM_CHAR 0x58
346 #define H_REAL_TO_LOGICAL 0x5c
347 #define H_HYPERVISOR_DATA 0x60
353 #define H_PERFMON 0x7c
354 #define H_MIGRATE_DMA 0x78
355 #define H_REGISTER_VPA 0xDC
357 #define H_CONFER 0xE4
359 #define H_GET_PPP 0xEC
360 #define H_SET_PPP 0xF0
363 #define H_REG_CRQ 0xFC
364 #define H_FREE_CRQ 0x100
365 #define H_VIO_SIGNAL 0x104
366 #define H_SEND_CRQ 0x108
367 #define H_COPY_RDMA 0x110
368 #define H_REGISTER_LOGICAL_LAN 0x114
369 #define H_FREE_LOGICAL_LAN 0x118
370 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C
371 #define H_SEND_LOGICAL_LAN 0x120
372 #define H_BULK_REMOVE 0x124
373 #define H_MULTICAST_CTRL 0x130
374 #define H_SET_XDABR 0x134
375 #define H_STUFF_TCE 0x138
376 #define H_PUT_TCE_INDIRECT 0x13C
377 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C
378 #define H_VTERM_PARTNER_INFO 0x150
379 #define H_REGISTER_VTERM 0x154
380 #define H_FREE_VTERM 0x158
381 #define H_RESET_EVENTS 0x15C
382 #define H_ALLOC_RESOURCE 0x160
383 #define H_FREE_RESOURCE 0x164
384 #define H_MODIFY_QP 0x168
385 #define H_QUERY_QP 0x16C
386 #define H_REREGISTER_PMR 0x170
387 #define H_REGISTER_SMR 0x174
388 #define H_QUERY_MR 0x178
389 #define H_QUERY_MW 0x17C
390 #define H_QUERY_HCA 0x180
391 #define H_QUERY_PORT 0x184
392 #define H_MODIFY_PORT 0x188
393 #define H_DEFINE_AQP1 0x18C
394 #define H_GET_TRACE_BUFFER 0x190
395 #define H_DEFINE_AQP0 0x194
396 #define H_RESIZE_MR 0x198
397 #define H_ATTACH_MCQP 0x19C
398 #define H_DETACH_MCQP 0x1A0
399 #define H_CREATE_RPT 0x1A4
400 #define H_REMOVE_RPT 0x1A8
401 #define H_REGISTER_RPAGES 0x1AC
402 #define H_DISABLE_AND_GETC 0x1B0
403 #define H_ERROR_DATA 0x1B4
404 #define H_GET_HCA_INFO 0x1B8
405 #define H_GET_PERF_COUNT 0x1BC
406 #define H_MANAGE_TRACE 0x1C0
407 #define H_GET_CPU_CHARACTERISTICS 0x1C8
408 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
409 #define H_QUERY_INT_STATE 0x1E4
410 #define H_POLL_PENDING 0x1D8
411 #define H_ILLAN_ATTRIBUTES 0x244
412 #define H_MODIFY_HEA_QP 0x250
413 #define H_QUERY_HEA_QP 0x254
414 #define H_QUERY_HEA 0x258
415 #define H_QUERY_HEA_PORT 0x25C
416 #define H_MODIFY_HEA_PORT 0x260
417 #define H_REG_BCMC 0x264
418 #define H_DEREG_BCMC 0x268
419 #define H_REGISTER_HEA_RPAGES 0x26C
420 #define H_DISABLE_AND_GET_HEA 0x270
421 #define H_GET_HEA_INFO 0x274
422 #define H_ALLOC_HEA_RESOURCE 0x278
423 #define H_ADD_CONN 0x284
424 #define H_DEL_CONN 0x288
426 #define H_VASI_STATE 0x2A4
427 #define H_ENABLE_CRQ 0x2B0
428 #define H_GET_EM_PARMS 0x2B8
429 #define H_SET_MPP 0x2D0
430 #define H_GET_MPP 0x2D4
431 #define H_XIRR_X 0x2FC
432 #define H_RANDOM 0x300
433 #define H_SET_MODE 0x31C
434 #define H_RESIZE_HPT_PREPARE 0x36C
435 #define H_RESIZE_HPT_COMMIT 0x370
436 #define H_CLEAN_SLB 0x374
437 #define H_INVALIDATE_PID 0x378
438 #define H_REGISTER_PROC_TBL 0x37C
439 #define H_SIGNAL_SYS_RESET 0x380
440 #define MAX_HCALL_OPCODE H_SIGNAL_SYS_RESET
442 /* The hcalls above are standardized in PAPR and implemented by pHyp
445 * We also need some hcalls which are specific to qemu / KVM-on-POWER.
446 * We put those into the 0xf000-0xfffc range which is reserved by PAPR
447 * for "platform-specific" hcalls.
449 #define KVMPPC_HCALL_BASE 0xf000
450 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
451 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1)
452 /* Client Architecture support */
453 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2)
454 #define KVMPPC_HCALL_MAX KVMPPC_H_CAS
456 typedef struct sPAPRDeviceTreeUpdateHeader
{
458 } sPAPRDeviceTreeUpdateHeader
;
460 #define hcall_dprintf(fmt, ...) \
462 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
465 typedef target_ulong (*spapr_hcall_fn
)(PowerPCCPU
*cpu
, sPAPRMachineState
*sm
,
469 void spapr_register_hypercall(target_ulong opcode
, spapr_hcall_fn fn
);
470 target_ulong
spapr_hypercall(PowerPCCPU
*cpu
, target_ulong opcode
,
473 /* ibm,set-eeh-option */
474 #define RTAS_EEH_DISABLE 0
475 #define RTAS_EEH_ENABLE 1
476 #define RTAS_EEH_THAW_IO 2
477 #define RTAS_EEH_THAW_DMA 3
479 /* ibm,get-config-addr-info2 */
480 #define RTAS_GET_PE_ADDR 0
481 #define RTAS_GET_PE_MODE 1
482 #define RTAS_PE_MODE_NONE 0
483 #define RTAS_PE_MODE_NOT_SHARED 1
484 #define RTAS_PE_MODE_SHARED 2
486 /* ibm,read-slot-reset-state2 */
487 #define RTAS_EEH_PE_STATE_NORMAL 0
488 #define RTAS_EEH_PE_STATE_RESET 1
489 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
490 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4
491 #define RTAS_EEH_PE_STATE_UNAVAIL 5
492 #define RTAS_EEH_NOT_SUPPORT 0
493 #define RTAS_EEH_SUPPORT 1
494 #define RTAS_EEH_PE_UNAVAIL_INFO 1000
495 #define RTAS_EEH_PE_RECOVER_INFO 0
497 /* ibm,set-slot-reset */
498 #define RTAS_SLOT_RESET_DEACTIVATE 0
499 #define RTAS_SLOT_RESET_HOT 1
500 #define RTAS_SLOT_RESET_FUNDAMENTAL 3
502 /* ibm,slot-error-detail */
503 #define RTAS_SLOT_TEMP_ERR_LOG 1
504 #define RTAS_SLOT_PERM_ERR_LOG 2
506 /* RTAS return codes */
507 #define RTAS_OUT_SUCCESS 0
508 #define RTAS_OUT_NO_ERRORS_FOUND 1
509 #define RTAS_OUT_HW_ERROR -1
510 #define RTAS_OUT_BUSY -2
511 #define RTAS_OUT_PARAM_ERROR -3
512 #define RTAS_OUT_NOT_SUPPORTED -3
513 #define RTAS_OUT_NO_SUCH_INDICATOR -3
514 #define RTAS_OUT_NOT_AUTHORIZED -9002
515 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999
517 /* DDW pagesize mask values from ibm,query-pe-dma-window */
518 #define RTAS_DDW_PGSIZE_4K 0x01
519 #define RTAS_DDW_PGSIZE_64K 0x02
520 #define RTAS_DDW_PGSIZE_16M 0x04
521 #define RTAS_DDW_PGSIZE_32M 0x08
522 #define RTAS_DDW_PGSIZE_64M 0x10
523 #define RTAS_DDW_PGSIZE_128M 0x20
524 #define RTAS_DDW_PGSIZE_256M 0x40
525 #define RTAS_DDW_PGSIZE_16G 0x80
528 #define RTAS_TOKEN_BASE 0x2000
530 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00)
531 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01)
532 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02)
533 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03)
534 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04)
535 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05)
536 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06)
537 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07)
538 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08)
539 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09)
540 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A)
541 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B)
542 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C)
543 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D)
544 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E)
545 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F)
546 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10)
547 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11)
548 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12)
549 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13)
550 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14)
551 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15)
552 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16)
553 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17)
554 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18)
555 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19)
556 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A)
557 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B)
558 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C)
559 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D)
560 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E)
561 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F)
562 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20)
563 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21)
564 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22)
565 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23)
566 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24)
567 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25)
568 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26)
569 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27)
570 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28)
571 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29)
573 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A)
575 /* RTAS ibm,get-system-parameter token values */
576 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20
577 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42
578 #define RTAS_SYSPARM_UUID 48
580 /* RTAS indicator/sensor types
582 * as defined by PAPR+ 2.7 7.3.5.4, Table 41
584 * NOTE: currently only DR-related sensors are implemented here
586 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001
587 #define RTAS_SENSOR_TYPE_DR 9002
588 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003
589 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
591 /* Possible values for the platform-processor-diagnostics-run-mode parameter
592 * of the RTAS ibm,get-system-parameter call.
594 #define DIAGNOSTICS_RUN_MODE_DISABLED 0
595 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1
596 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
597 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3
599 static inline uint64_t ppc64_phys_to_real(uint64_t addr
)
601 return addr
& ~0xF000000000000000ULL
;
604 static inline uint32_t rtas_ld(target_ulong phys
, int n
)
606 return ldl_be_phys(&address_space_memory
, ppc64_phys_to_real(phys
+ 4*n
));
609 static inline uint64_t rtas_ldq(target_ulong phys
, int n
)
611 return (uint64_t)rtas_ld(phys
, n
) << 32 | rtas_ld(phys
, n
+ 1);
614 static inline void rtas_st(target_ulong phys
, int n
, uint32_t val
)
616 stl_be_phys(&address_space_memory
, ppc64_phys_to_real(phys
+ 4*n
), val
);
619 typedef void (*spapr_rtas_fn
)(PowerPCCPU
*cpu
, sPAPRMachineState
*sm
,
621 uint32_t nargs
, target_ulong args
,
622 uint32_t nret
, target_ulong rets
);
623 void spapr_rtas_register(int token
, const char *name
, spapr_rtas_fn fn
);
624 target_ulong
spapr_rtas_call(PowerPCCPU
*cpu
, sPAPRMachineState
*sm
,
625 uint32_t token
, uint32_t nargs
, target_ulong args
,
626 uint32_t nret
, target_ulong rets
);
627 void spapr_dt_rtas_tokens(void *fdt
, int rtas
);
628 void spapr_load_rtas(sPAPRMachineState
*spapr
, void *fdt
, hwaddr addr
);
630 #define SPAPR_TCE_PAGE_SHIFT 12
631 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT)
632 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1)
634 #define SPAPR_VIO_BASE_LIOBN 0x00000000
635 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg))
636 #define SPAPR_PCI_LIOBN(phb_index, window_num) \
637 (0x80000000 | ((phb_index) << 8) | (window_num))
638 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000))
639 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
641 #define RTAS_ERROR_LOG_MAX 2048
643 #define RTAS_EVENT_SCAN_RATE 1
645 /* This helper should be used to encode interrupt specifiers when the related
646 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie,
647 * VIO devices, RTAS event sources and PHBs).
649 static inline void spapr_dt_xics_irq(uint32_t *intspec
, int irq
, bool is_lsi
)
651 intspec
[0] = cpu_to_be32(irq
);
652 intspec
[1] = is_lsi
? cpu_to_be32(1) : 0;
655 typedef struct sPAPRTCETable sPAPRTCETable
;
657 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
658 #define SPAPR_TCE_TABLE(obj) \
659 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE)
661 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region"
662 #define SPAPR_IOMMU_MEMORY_REGION(obj) \
663 OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION)
665 struct sPAPRTCETable
{
672 uint32_t mig_nb_table
;
678 IOMMUMemoryRegion iommu
;
679 struct VIOsPAPRDevice
*vdev
; /* for @bypass migration compatibility only */
680 QLIST_ENTRY(sPAPRTCETable
) list
;
683 sPAPRTCETable
*spapr_tce_find_by_liobn(target_ulong liobn
);
685 struct sPAPREventLogEntry
{
687 uint32_t extended_length
;
689 QTAILQ_ENTRY(sPAPREventLogEntry
) next
;
692 void spapr_events_init(sPAPRMachineState
*sm
);
693 void spapr_dt_events(sPAPRMachineState
*sm
, void *fdt
);
694 int spapr_h_cas_compose_response(sPAPRMachineState
*sm
,
695 target_ulong addr
, target_ulong size
,
696 sPAPROptionVector
*ov5_updates
);
697 void close_htab_fd(sPAPRMachineState
*spapr
);
698 void spapr_setup_hpt_and_vrma(sPAPRMachineState
*spapr
);
699 void spapr_free_hpt(sPAPRMachineState
*spapr
);
700 sPAPRTCETable
*spapr_tce_new_table(DeviceState
*owner
, uint32_t liobn
);
701 void spapr_tce_table_enable(sPAPRTCETable
*tcet
,
702 uint32_t page_shift
, uint64_t bus_offset
,
704 void spapr_tce_table_disable(sPAPRTCETable
*tcet
);
705 void spapr_tce_set_need_vfio(sPAPRTCETable
*tcet
, bool need_vfio
);
707 MemoryRegion
*spapr_tce_get_iommu(sPAPRTCETable
*tcet
);
708 int spapr_dma_dt(void *fdt
, int node_off
, const char *propname
,
709 uint32_t liobn
, uint64_t window
, uint32_t size
);
710 int spapr_tcet_dma_dt(void *fdt
, int node_off
, const char *propname
,
711 sPAPRTCETable
*tcet
);
712 void spapr_pci_switch_vga(bool big_endian
);
713 void spapr_hotplug_req_add_by_index(sPAPRDRConnector
*drc
);
714 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector
*drc
);
715 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type
,
717 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type
,
719 void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type
,
720 uint32_t count
, uint32_t index
);
721 void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type
,
722 uint32_t count
, uint32_t index
);
723 int spapr_hpt_shift_for_ramsize(uint64_t ramsize
);
724 void spapr_reallocate_hpt(sPAPRMachineState
*spapr
, int shift
,
726 void spapr_clear_pending_events(sPAPRMachineState
*spapr
);
728 /* CPU and LMB DRC release callbacks. */
729 void spapr_core_release(DeviceState
*dev
);
730 void spapr_lmb_release(DeviceState
*dev
);
732 void spapr_rtc_read(sPAPRRTCState
*rtc
, struct tm
*tm
, uint32_t *ns
);
733 int spapr_rtc_import_offset(sPAPRRTCState
*rtc
, int64_t legacy_offset
);
735 #define TYPE_SPAPR_RNG "spapr-rng"
737 int spapr_rng_populate_dt(void *fdt
);
739 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */
742 * This defines the maximum number of DIMM slots we can have for sPAPR
743 * guest. This is not defined by sPAPR but we are defining it to 32 slots
744 * based on default number of slots provided by PowerPC kernel.
746 #define SPAPR_MAX_RAM_SLOTS 32
748 /* 1GB alignment for hotplug memory region */
749 #define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30)
752 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory
753 * property under ibm,dynamic-reconfiguration-memory node.
755 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
758 * Defines for flag value in ibm,dynamic-memory property under
759 * ibm,dynamic-reconfiguration-memory node.
761 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
762 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
763 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080
765 void spapr_do_system_reset_on_cpu(CPUState
*cs
, run_on_cpu_data arg
);
767 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
769 int spapr_get_vcpu_id(PowerPCCPU
*cpu
);
770 void spapr_set_vcpu_id(PowerPCCPU
*cpu
, int cpu_index
, Error
**errp
);
771 PowerPCCPU
*spapr_find_cpu(int vcpu_id
);
773 int spapr_irq_alloc(sPAPRMachineState
*spapr
, int irq_hint
, bool lsi
,
775 int spapr_irq_alloc_block(sPAPRMachineState
*spapr
, int num
, bool lsi
,
776 bool align
, Error
**errp
);
777 void spapr_irq_free(sPAPRMachineState
*spapr
, int irq
, int num
);
778 qemu_irq
spapr_qirq(sPAPRMachineState
*spapr
, int irq
);
781 int spapr_caps_pre_load(void *opaque
);
782 int spapr_caps_pre_save(void *opaque
);
785 * Handling of optional capabilities
787 extern const VMStateDescription vmstate_spapr_cap_htm
;
788 extern const VMStateDescription vmstate_spapr_cap_vsx
;
789 extern const VMStateDescription vmstate_spapr_cap_dfp
;
790 extern const VMStateDescription vmstate_spapr_cap_cfpc
;
791 extern const VMStateDescription vmstate_spapr_cap_sbbc
;
792 extern const VMStateDescription vmstate_spapr_cap_ibs
;
794 static inline uint8_t spapr_get_cap(sPAPRMachineState
*spapr
, int cap
)
796 return spapr
->eff
.caps
[cap
];
799 void spapr_caps_reset(sPAPRMachineState
*spapr
);
800 void spapr_caps_add_properties(sPAPRMachineClass
*smc
, Error
**errp
);
801 int spapr_caps_post_migration(sPAPRMachineState
*spapr
);
803 #endif /* HW_SPAPR_H */