2 * PowerPC CPU routines for qemu.
4 * Copyright (c) 2017 Nikunj A Dadhania, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "cpu-models.h"
25 #include "fpu/softfloat-helpers.h"
26 #include "mmu-hash64.h"
27 #include "helper_regs.h"
28 #include "sysemu/tcg.h"
30 target_ulong
cpu_read_xer(CPUPPCState
*env
)
33 return env
->xer
| (env
->so
<< XER_SO
) |
34 (env
->ov
<< XER_OV
) | (env
->ca
<< XER_CA
) |
35 (env
->ov32
<< XER_OV32
) | (env
->ca32
<< XER_CA32
);
38 return env
->xer
| (env
->so
<< XER_SO
) | (env
->ov
<< XER_OV
) |
42 void cpu_write_xer(CPUPPCState
*env
, target_ulong xer
)
44 env
->so
= (xer
>> XER_SO
) & 1;
45 env
->ov
= (xer
>> XER_OV
) & 1;
46 env
->ca
= (xer
>> XER_CA
) & 1;
47 /* write all the flags, while reading back check of isa300 */
48 env
->ov32
= (xer
>> XER_OV32
) & 1;
49 env
->ca32
= (xer
>> XER_CA32
) & 1;
50 env
->xer
= xer
& ~((1ul << XER_SO
) |
51 (1ul << XER_OV
) | (1ul << XER_CA
) |
52 (1ul << XER_OV32
) | (1ul << XER_CA32
));
55 void ppc_store_vscr(CPUPPCState
*env
, uint32_t vscr
)
57 env
->vscr
= vscr
& ~(1u << VSCR_SAT
);
58 /* Which bit we set is completely arbitrary, but clear the rest. */
59 env
->vscr_sat
.u64
[0] = vscr
& (1u << VSCR_SAT
);
60 env
->vscr_sat
.u64
[1] = 0;
61 set_flush_to_zero((vscr
>> VSCR_NJ
) & 1, &env
->vec_status
);
64 uint32_t ppc_get_vscr(CPUPPCState
*env
)
66 uint32_t sat
= (env
->vscr_sat
.u64
[0] | env
->vscr_sat
.u64
[1]) != 0;
67 return env
->vscr
| (sat
<< VSCR_SAT
);
71 void ppc_store_sdr1(CPUPPCState
*env
, target_ulong value
)
73 PowerPCCPU
*cpu
= env_archcpu(env
);
74 qemu_log_mask(CPU_LOG_MMU
, "%s: " TARGET_FMT_lx
"\n", __func__
, value
);
76 #if defined(TARGET_PPC64)
77 if (mmu_is_64bit(env
->mmu_model
)) {
78 target_ulong sdr_mask
= SDR_64_HTABORG
| SDR_64_HTABSIZE
;
79 target_ulong htabsize
= value
& SDR_64_HTABSIZE
;
81 if (value
& ~sdr_mask
) {
82 qemu_log_mask(LOG_GUEST_ERROR
, "Invalid bits 0x"TARGET_FMT_lx
83 " set in SDR1", value
& ~sdr_mask
);
87 qemu_log_mask(LOG_GUEST_ERROR
, "Invalid HTABSIZE 0x" TARGET_FMT_lx
88 " stored in SDR1", htabsize
);
92 #endif /* defined(TARGET_PPC64) */
93 /* FIXME: Should check for valid HTABMASK values in 32-bit case */
94 env
->spr
[SPR_SDR1
] = value
;
96 #endif /* CONFIG_SOFTMMU */
98 /* GDBstub can read and write MSR... */
99 void ppc_store_msr(CPUPPCState
*env
, target_ulong value
)
101 hreg_store_msr(env
, value
, 0);
104 void ppc_store_lpcr(PowerPCCPU
*cpu
, target_ulong val
)
106 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
107 CPUPPCState
*env
= &cpu
->env
;
109 env
->spr
[SPR_LPCR
] = val
& pcc
->lpcr_mask
;
110 /* The gtse bit affects hflags */
111 hreg_compute_hflags(env
);
114 static inline void fpscr_set_rounding_mode(CPUPPCState
*env
)
118 /* Set rounding mode */
121 /* Best approximation (round to nearest) */
122 rnd_type
= float_round_nearest_even
;
125 /* Smaller magnitude (round toward zero) */
126 rnd_type
= float_round_to_zero
;
129 /* Round toward +infinite */
130 rnd_type
= float_round_up
;
134 /* Round toward -infinite */
135 rnd_type
= float_round_down
;
138 set_float_rounding_mode(rnd_type
, &env
->fp_status
);
141 void ppc_store_fpscr(CPUPPCState
*env
, target_ulong val
)
143 val
&= ~(FP_VX
| FP_FEX
);
144 if (val
& FPSCR_IX
) {
147 if ((val
>> FPSCR_XX
) & (val
>> FPSCR_XE
) & 0x1f) {
152 fpscr_set_rounding_mode(env
);