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target/mips: Fix space-related format issues in msa_helper.c
[qemu/kevin.git] / target / mips / msa_helper.c
blobeacb5a4cf511fedf0a5aa0a7796e62c853bd4934
1 /*
2 * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU.
3 *
4 * Copyright (c) 2014 Imagination Technologies
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "internal.h"
23 #include "exec/exec-all.h"
24 #include "exec/helper-proto.h"
25
26 /* Data format min and max values */
27 #define DF_BITS(df) (1 << ((df) + 3))
28
29 #define DF_MAX_INT(df) (int64_t)((1LL << (DF_BITS(df) - 1)) - 1)
30 #define M_MAX_INT(m) (int64_t)((1LL << ((m) - 1)) - 1)
31
32 #define DF_MIN_INT(df) (int64_t)(-(1LL << (DF_BITS(df) - 1)))
33 #define M_MIN_INT(m) (int64_t)(-(1LL << ((m) - 1)))
34
35 #define DF_MAX_UINT(df) (uint64_t)(-1ULL >> (64 - DF_BITS(df)))
36 #define M_MAX_UINT(m) (uint64_t)(-1ULL >> (64 - (m)))
37
38 #define UNSIGNED(x, df) ((x) & DF_MAX_UINT(df))
39 #define SIGNED(x, df) \
40 ((((int64_t)x) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)))
41
42 /* Element-by-element access macros */
43 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
44
45 static inline void msa_move_v(wr_t *pwd, wr_t *pws)
46 {
47 uint32_t i;
48
49 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
50 pwd->d[i] = pws->d[i];
51 }
52 }
53
54 #define MSA_FN_IMM8(FUNC, DEST, OPERATION) \
55 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
56 uint32_t i8) \
57 { \
58 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
59 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
60 uint32_t i; \
61 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
62 DEST = OPERATION; \
63 } \
64 }
65
66 MSA_FN_IMM8(andi_b, pwd->b[i], pws->b[i] & i8)
67 MSA_FN_IMM8(ori_b, pwd->b[i], pws->b[i] | i8)
68 MSA_FN_IMM8(nori_b, pwd->b[i], ~(pws->b[i] | i8))
69 MSA_FN_IMM8(xori_b, pwd->b[i], pws->b[i] ^ i8)
70
71 #define BIT_MOVE_IF_NOT_ZERO(dest, arg1, arg2, df) \
72 UNSIGNED(((dest & (~arg2)) | (arg1 & arg2)), df)
73 MSA_FN_IMM8(bmnzi_b, pwd->b[i],
74 BIT_MOVE_IF_NOT_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
75
76 #define BIT_MOVE_IF_ZERO(dest, arg1, arg2, df) \
77 UNSIGNED((dest & arg2) | (arg1 & (~arg2)), df)
78 MSA_FN_IMM8(bmzi_b, pwd->b[i],
79 BIT_MOVE_IF_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
80
81 #define BIT_SELECT(dest, arg1, arg2, df) \
82 UNSIGNED((arg1 & (~dest)) | (arg2 & dest), df)
83 MSA_FN_IMM8(bseli_b, pwd->b[i],
84 BIT_SELECT(pwd->b[i], pws->b[i], i8, DF_BYTE))
85
86 #undef MSA_FN_IMM8
87
88 #define SHF_POS(i, imm) (((i) & 0xfc) + (((imm) >> (2 * ((i) & 0x03))) & 0x03))
89
90 void helper_msa_shf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
91 uint32_t ws, uint32_t imm)
92 {
93 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
94 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
95 wr_t wx, *pwx = &wx;
96 uint32_t i;
97
98 switch (df) {
99 case DF_BYTE:
100 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
101 pwx->b[i] = pws->b[SHF_POS(i, imm)];
102 }
103 break;
104 case DF_HALF:
105 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
106 pwx->h[i] = pws->h[SHF_POS(i, imm)];
107 }
108 break;
109 case DF_WORD:
110 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
111 pwx->w[i] = pws->w[SHF_POS(i, imm)];
112 }
113 break;
114 default:
115 assert(0);
116 }
117 msa_move_v(pwd, pwx);
118 }
119
120 #define MSA_FN_VECTOR(FUNC, DEST, OPERATION) \
121 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
122 uint32_t wt) \
123 { \
124 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
125 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
126 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
127 uint32_t i; \
128 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
129 DEST = OPERATION; \
130 } \
131 }
132
133 MSA_FN_VECTOR(and_v, pwd->d[i], pws->d[i] & pwt->d[i])
134 MSA_FN_VECTOR(or_v, pwd->d[i], pws->d[i] | pwt->d[i])
135 MSA_FN_VECTOR(nor_v, pwd->d[i], ~(pws->d[i] | pwt->d[i]))
136 MSA_FN_VECTOR(xor_v, pwd->d[i], pws->d[i] ^ pwt->d[i])
137 MSA_FN_VECTOR(bmnz_v, pwd->d[i],
138 BIT_MOVE_IF_NOT_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
139 MSA_FN_VECTOR(bmz_v, pwd->d[i],
140 BIT_MOVE_IF_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
141 MSA_FN_VECTOR(bsel_v, pwd->d[i],
142 BIT_SELECT(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
143 #undef BIT_MOVE_IF_NOT_ZERO
144 #undef BIT_MOVE_IF_ZERO
145 #undef BIT_SELECT
146 #undef MSA_FN_VECTOR
147
148 static inline int64_t msa_addv_df(uint32_t df, int64_t arg1, int64_t arg2)
149 {
150 return arg1 + arg2;
151 }
152
153 static inline int64_t msa_subv_df(uint32_t df, int64_t arg1, int64_t arg2)
154 {
155 return arg1 - arg2;
156 }
157
158 static inline int64_t msa_ceq_df(uint32_t df, int64_t arg1, int64_t arg2)
159 {
160 return arg1 == arg2 ? -1 : 0;
161 }
162
163 static inline int64_t msa_cle_s_df(uint32_t df, int64_t arg1, int64_t arg2)
164 {
165 return arg1 <= arg2 ? -1 : 0;
166 }
167
168 static inline int64_t msa_cle_u_df(uint32_t df, int64_t arg1, int64_t arg2)
169 {
170 uint64_t u_arg1 = UNSIGNED(arg1, df);
171 uint64_t u_arg2 = UNSIGNED(arg2, df);
172 return u_arg1 <= u_arg2 ? -1 : 0;
173 }
174
175 static inline int64_t msa_clt_s_df(uint32_t df, int64_t arg1, int64_t arg2)
176 {
177 return arg1 < arg2 ? -1 : 0;
178 }
179
180 static inline int64_t msa_clt_u_df(uint32_t df, int64_t arg1, int64_t arg2)
181 {
182 uint64_t u_arg1 = UNSIGNED(arg1, df);
183 uint64_t u_arg2 = UNSIGNED(arg2, df);
184 return u_arg1 < u_arg2 ? -1 : 0;
185 }
186
187 static inline int64_t msa_max_s_df(uint32_t df, int64_t arg1, int64_t arg2)
188 {
189 return arg1 > arg2 ? arg1 : arg2;
190 }
191
192 static inline int64_t msa_max_u_df(uint32_t df, int64_t arg1, int64_t arg2)
193 {
194 uint64_t u_arg1 = UNSIGNED(arg1, df);
195 uint64_t u_arg2 = UNSIGNED(arg2, df);
196 return u_arg1 > u_arg2 ? arg1 : arg2;
197 }
198
199 static inline int64_t msa_min_s_df(uint32_t df, int64_t arg1, int64_t arg2)
200 {
201 return arg1 < arg2 ? arg1 : arg2;
202 }
203
204 static inline int64_t msa_min_u_df(uint32_t df, int64_t arg1, int64_t arg2)
205 {
206 uint64_t u_arg1 = UNSIGNED(arg1, df);
207 uint64_t u_arg2 = UNSIGNED(arg2, df);
208 return u_arg1 < u_arg2 ? arg1 : arg2;
209 }
210
211 #define MSA_BINOP_IMM_DF(helper, func) \
212 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
213 uint32_t wd, uint32_t ws, int32_t u5) \
214 { \
215 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
216 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
217 uint32_t i; \
218 \
219 switch (df) { \
220 case DF_BYTE: \
221 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
222 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
223 } \
224 break; \
225 case DF_HALF: \
226 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
227 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
228 } \
229 break; \
230 case DF_WORD: \
231 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
232 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
233 } \
234 break; \
235 case DF_DOUBLE: \
236 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
237 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
238 } \
239 break; \
240 default: \
241 assert(0); \
242 } \
243 }
244
245 MSA_BINOP_IMM_DF(addvi, addv)
246 MSA_BINOP_IMM_DF(subvi, subv)
247 MSA_BINOP_IMM_DF(ceqi, ceq)
248 MSA_BINOP_IMM_DF(clei_s, cle_s)
249 MSA_BINOP_IMM_DF(clei_u, cle_u)
250 MSA_BINOP_IMM_DF(clti_s, clt_s)
251 MSA_BINOP_IMM_DF(clti_u, clt_u)
252 MSA_BINOP_IMM_DF(maxi_s, max_s)
253 MSA_BINOP_IMM_DF(maxi_u, max_u)
254 MSA_BINOP_IMM_DF(mini_s, min_s)
255 MSA_BINOP_IMM_DF(mini_u, min_u)
256 #undef MSA_BINOP_IMM_DF
257
258 void helper_msa_ldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
259 int32_t s10)
260 {
261 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
262 uint32_t i;
263
264 switch (df) {
265 case DF_BYTE:
266 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
267 pwd->b[i] = (int8_t)s10;
268 }
269 break;
270 case DF_HALF:
271 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
272 pwd->h[i] = (int16_t)s10;
273 }
274 break;
275 case DF_WORD:
276 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
277 pwd->w[i] = (int32_t)s10;
278 }
279 break;
280 case DF_DOUBLE:
281 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
282 pwd->d[i] = (int64_t)s10;
283 }
284 break;
285 default:
286 assert(0);
287 }
288 }
289
290 /* Data format bit position and unsigned values */
291 #define BIT_POSITION(x, df) ((uint64_t)(x) % DF_BITS(df))
292
293 static inline int64_t msa_sll_df(uint32_t df, int64_t arg1, int64_t arg2)
294 {
295 int32_t b_arg2 = BIT_POSITION(arg2, df);
296 return arg1 << b_arg2;
297 }
298
299 static inline int64_t msa_sra_df(uint32_t df, int64_t arg1, int64_t arg2)
300 {
301 int32_t b_arg2 = BIT_POSITION(arg2, df);
302 return arg1 >> b_arg2;
303 }
304
305 static inline int64_t msa_srl_df(uint32_t df, int64_t arg1, int64_t arg2)
306 {
307 uint64_t u_arg1 = UNSIGNED(arg1, df);
308 int32_t b_arg2 = BIT_POSITION(arg2, df);
309 return u_arg1 >> b_arg2;
310 }
311
312 static inline int64_t msa_bclr_df(uint32_t df, int64_t arg1, int64_t arg2)
313 {
314 int32_t b_arg2 = BIT_POSITION(arg2, df);
315 return UNSIGNED(arg1 & (~(1LL << b_arg2)), df);
316 }
317
318 static inline int64_t msa_bset_df(uint32_t df, int64_t arg1,
319 int64_t arg2)
320 {
321 int32_t b_arg2 = BIT_POSITION(arg2, df);
322 return UNSIGNED(arg1 | (1LL << b_arg2), df);
323 }
324
325 static inline int64_t msa_bneg_df(uint32_t df, int64_t arg1, int64_t arg2)
326 {
327 int32_t b_arg2 = BIT_POSITION(arg2, df);
328 return UNSIGNED(arg1 ^ (1LL << b_arg2), df);
329 }
330
331 static inline int64_t msa_binsl_df(uint32_t df, int64_t dest, int64_t arg1,
332 int64_t arg2)
333 {
334 uint64_t u_arg1 = UNSIGNED(arg1, df);
335 uint64_t u_dest = UNSIGNED(dest, df);
336 int32_t sh_d = BIT_POSITION(arg2, df) + 1;
337 int32_t sh_a = DF_BITS(df) - sh_d;
338 if (sh_d == DF_BITS(df)) {
339 return u_arg1;
340 } else {
341 return UNSIGNED(UNSIGNED(u_dest << sh_d, df) >> sh_d, df) |
342 UNSIGNED(UNSIGNED(u_arg1 >> sh_a, df) << sh_a, df);
343 }
344 }
345
346 static inline int64_t msa_binsr_df(uint32_t df, int64_t dest, int64_t arg1,
347 int64_t arg2)
348 {
349 uint64_t u_arg1 = UNSIGNED(arg1, df);
350 uint64_t u_dest = UNSIGNED(dest, df);
351 int32_t sh_d = BIT_POSITION(arg2, df) + 1;
352 int32_t sh_a = DF_BITS(df) - sh_d;
353 if (sh_d == DF_BITS(df)) {
354 return u_arg1;
355 } else {
356 return UNSIGNED(UNSIGNED(u_dest >> sh_d, df) << sh_d, df) |
357 UNSIGNED(UNSIGNED(u_arg1 << sh_a, df) >> sh_a, df);
358 }
359 }
360
361 static inline int64_t msa_sat_s_df(uint32_t df, int64_t arg, uint32_t m)
362 {
363 return arg < M_MIN_INT(m + 1) ? M_MIN_INT(m + 1) :
364 arg > M_MAX_INT(m + 1) ? M_MAX_INT(m + 1) :
365 arg;
366 }
367
368 static inline int64_t msa_sat_u_df(uint32_t df, int64_t arg, uint32_t m)
369 {
370 uint64_t u_arg = UNSIGNED(arg, df);
371 return u_arg < M_MAX_UINT(m + 1) ? u_arg :
372 M_MAX_UINT(m + 1);
373 }
374
375 static inline int64_t msa_srar_df(uint32_t df, int64_t arg1, int64_t arg2)
376 {
377 int32_t b_arg2 = BIT_POSITION(arg2, df);
378 if (b_arg2 == 0) {
379 return arg1;
380 } else {
381 int64_t r_bit = (arg1 >> (b_arg2 - 1)) & 1;
382 return (arg1 >> b_arg2) + r_bit;
383 }
384 }
385
386 static inline int64_t msa_srlr_df(uint32_t df, int64_t arg1, int64_t arg2)
387 {
388 uint64_t u_arg1 = UNSIGNED(arg1, df);
389 int32_t b_arg2 = BIT_POSITION(arg2, df);
390 if (b_arg2 == 0) {
391 return u_arg1;
392 } else {
393 uint64_t r_bit = (u_arg1 >> (b_arg2 - 1)) & 1;
394 return (u_arg1 >> b_arg2) + r_bit;
395 }
396 }
397
398 #define MSA_BINOP_IMMU_DF(helper, func) \
399 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
400 uint32_t ws, uint32_t u5) \
401 { \
402 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
403 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
404 uint32_t i; \
405 \
406 switch (df) { \
407 case DF_BYTE: \
408 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
409 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
410 } \
411 break; \
412 case DF_HALF: \
413 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
414 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
415 } \
416 break; \
417 case DF_WORD: \
418 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
419 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
420 } \
421 break; \
422 case DF_DOUBLE: \
423 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
424 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
425 } \
426 break; \
427 default: \
428 assert(0); \
429 } \
430 }
431
432 MSA_BINOP_IMMU_DF(slli, sll)
433 MSA_BINOP_IMMU_DF(srai, sra)
434 MSA_BINOP_IMMU_DF(srli, srl)
435 MSA_BINOP_IMMU_DF(bclri, bclr)
436 MSA_BINOP_IMMU_DF(bseti, bset)
437 MSA_BINOP_IMMU_DF(bnegi, bneg)
438 MSA_BINOP_IMMU_DF(sat_s, sat_s)
439 MSA_BINOP_IMMU_DF(sat_u, sat_u)
440 MSA_BINOP_IMMU_DF(srari, srar)
441 MSA_BINOP_IMMU_DF(srlri, srlr)
442 #undef MSA_BINOP_IMMU_DF
443
444 #define MSA_TEROP_IMMU_DF(helper, func) \
445 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
446 uint32_t wd, uint32_t ws, uint32_t u5) \
447 { \
448 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
449 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
450 uint32_t i; \
451 \
452 switch (df) { \
453 case DF_BYTE: \
454 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
455 pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \
456 u5); \
457 } \
458 break; \
459 case DF_HALF: \
460 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
461 pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \
462 u5); \
463 } \
464 break; \
465 case DF_WORD: \
466 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
467 pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \
468 u5); \
469 } \
470 break; \
471 case DF_DOUBLE: \
472 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
473 pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \
474 u5); \
475 } \
476 break; \
477 default: \
478 assert(0); \
479 } \
480 }
481
482 MSA_TEROP_IMMU_DF(binsli, binsl)
483 MSA_TEROP_IMMU_DF(binsri, binsr)
484 #undef MSA_TEROP_IMMU_DF
485
486 static inline int64_t msa_max_a_df(uint32_t df, int64_t arg1, int64_t arg2)
487 {
488 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
489 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
490 return abs_arg1 > abs_arg2 ? arg1 : arg2;
491 }
492
493 static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2)
494 {
495 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
496 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
497 return abs_arg1 < abs_arg2 ? arg1 : arg2;
498 }
499
500 static inline int64_t msa_add_a_df(uint32_t df, int64_t arg1, int64_t arg2)
501 {
502 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
503 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
504 return abs_arg1 + abs_arg2;
505 }
506
507 static inline int64_t msa_adds_a_df(uint32_t df, int64_t arg1, int64_t arg2)
508 {
509 uint64_t max_int = (uint64_t)DF_MAX_INT(df);
510 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
511 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
512 if (abs_arg1 > max_int || abs_arg2 > max_int) {
513 return (int64_t)max_int;
514 } else {
515 return (abs_arg1 < max_int - abs_arg2) ? abs_arg1 + abs_arg2 : max_int;
516 }
517 }
518
519 static inline int64_t msa_adds_s_df(uint32_t df, int64_t arg1, int64_t arg2)
520 {
521 int64_t max_int = DF_MAX_INT(df);
522 int64_t min_int = DF_MIN_INT(df);
523 if (arg1 < 0) {
524 return (min_int - arg1 < arg2) ? arg1 + arg2 : min_int;
525 } else {
526 return (arg2 < max_int - arg1) ? arg1 + arg2 : max_int;
527 }
528 }
529
530 static inline uint64_t msa_adds_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
531 {
532 uint64_t max_uint = DF_MAX_UINT(df);
533 uint64_t u_arg1 = UNSIGNED(arg1, df);
534 uint64_t u_arg2 = UNSIGNED(arg2, df);
535 return (u_arg1 < max_uint - u_arg2) ? u_arg1 + u_arg2 : max_uint;
536 }
537
538 static inline int64_t msa_ave_s_df(uint32_t df, int64_t arg1, int64_t arg2)
539 {
540 /* signed shift */
541 return (arg1 >> 1) + (arg2 >> 1) + (arg1 & arg2 & 1);
542 }
543
544 static inline uint64_t msa_ave_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
545 {
546 uint64_t u_arg1 = UNSIGNED(arg1, df);
547 uint64_t u_arg2 = UNSIGNED(arg2, df);
548 /* unsigned shift */
549 return (u_arg1 >> 1) + (u_arg2 >> 1) + (u_arg1 & u_arg2 & 1);
550 }
551
552 static inline int64_t msa_aver_s_df(uint32_t df, int64_t arg1, int64_t arg2)
553 {
554 /* signed shift */
555 return (arg1 >> 1) + (arg2 >> 1) + ((arg1 | arg2) & 1);
556 }
557
558 static inline uint64_t msa_aver_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
559 {
560 uint64_t u_arg1 = UNSIGNED(arg1, df);
561 uint64_t u_arg2 = UNSIGNED(arg2, df);
562 /* unsigned shift */
563 return (u_arg1 >> 1) + (u_arg2 >> 1) + ((u_arg1 | u_arg2) & 1);
564 }
565
566 static inline int64_t msa_subs_s_df(uint32_t df, int64_t arg1, int64_t arg2)
567 {
568 int64_t max_int = DF_MAX_INT(df);
569 int64_t min_int = DF_MIN_INT(df);
570 if (arg2 > 0) {
571 return (min_int + arg2 < arg1) ? arg1 - arg2 : min_int;
572 } else {
573 return (arg1 < max_int + arg2) ? arg1 - arg2 : max_int;
574 }
575 }
576
577 static inline int64_t msa_subs_u_df(uint32_t df, int64_t arg1, int64_t arg2)
578 {
579 uint64_t u_arg1 = UNSIGNED(arg1, df);
580 uint64_t u_arg2 = UNSIGNED(arg2, df);
581 return (u_arg1 > u_arg2) ? u_arg1 - u_arg2 : 0;
582 }
583
584 static inline int64_t msa_subsus_u_df(uint32_t df, int64_t arg1, int64_t arg2)
585 {
586 uint64_t u_arg1 = UNSIGNED(arg1, df);
587 uint64_t max_uint = DF_MAX_UINT(df);
588 if (arg2 >= 0) {
589 uint64_t u_arg2 = (uint64_t)arg2;
590 return (u_arg1 > u_arg2) ?
591 (int64_t)(u_arg1 - u_arg2) :
592 0;
593 } else {
594 uint64_t u_arg2 = (uint64_t)(-arg2);
595 return (u_arg1 < max_uint - u_arg2) ?
596 (int64_t)(u_arg1 + u_arg2) :
597 (int64_t)max_uint;
598 }
599 }
600
601 static inline int64_t msa_subsuu_s_df(uint32_t df, int64_t arg1, int64_t arg2)
602 {
603 uint64_t u_arg1 = UNSIGNED(arg1, df);
604 uint64_t u_arg2 = UNSIGNED(arg2, df);
605 int64_t max_int = DF_MAX_INT(df);
606 int64_t min_int = DF_MIN_INT(df);
607 if (u_arg1 > u_arg2) {
608 return u_arg1 - u_arg2 < (uint64_t)max_int ?
609 (int64_t)(u_arg1 - u_arg2) :
610 max_int;
611 } else {
612 return u_arg2 - u_arg1 < (uint64_t)(-min_int) ?
613 (int64_t)(u_arg1 - u_arg2) :
614 min_int;
615 }
616 }
617
618 static inline int64_t msa_asub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
619 {
620 /* signed compare */
621 return (arg1 < arg2) ?
622 (uint64_t)(arg2 - arg1) : (uint64_t)(arg1 - arg2);
623 }
624
625 static inline uint64_t msa_asub_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
626 {
627 uint64_t u_arg1 = UNSIGNED(arg1, df);
628 uint64_t u_arg2 = UNSIGNED(arg2, df);
629 /* unsigned compare */
630 return (u_arg1 < u_arg2) ?
631 (uint64_t)(u_arg2 - u_arg1) : (uint64_t)(u_arg1 - u_arg2);
632 }
633
634 static inline int64_t msa_mulv_df(uint32_t df, int64_t arg1, int64_t arg2)
635 {
636 return arg1 * arg2;
637 }
638
639 static inline int64_t msa_div_s_df(uint32_t df, int64_t arg1, int64_t arg2)
640 {
641 if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
642 return DF_MIN_INT(df);
643 }
644 return arg2 ? arg1 / arg2
645 : arg1 >= 0 ? -1 : 1;
646 }
647
648 static inline int64_t msa_div_u_df(uint32_t df, int64_t arg1, int64_t arg2)
649 {
650 uint64_t u_arg1 = UNSIGNED(arg1, df);
651 uint64_t u_arg2 = UNSIGNED(arg2, df);
652 return arg2 ? u_arg1 / u_arg2 : -1;
653 }
654
655 static inline int64_t msa_mod_s_df(uint32_t df, int64_t arg1, int64_t arg2)
656 {
657 if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
658 return 0;
659 }
660 return arg2 ? arg1 % arg2 : arg1;
661 }
662
663 static inline int64_t msa_mod_u_df(uint32_t df, int64_t arg1, int64_t arg2)
664 {
665 uint64_t u_arg1 = UNSIGNED(arg1, df);
666 uint64_t u_arg2 = UNSIGNED(arg2, df);
667 return u_arg2 ? u_arg1 % u_arg2 : u_arg1;
668 }
669
670 #define SIGNED_EVEN(a, df) \
671 ((((int64_t)(a)) << (64 - DF_BITS(df) / 2)) >> (64 - DF_BITS(df) / 2))
672
673 #define UNSIGNED_EVEN(a, df) \
674 ((((uint64_t)(a)) << (64 - DF_BITS(df) / 2)) >> (64 - DF_BITS(df) / 2))
675
676 #define SIGNED_ODD(a, df) \
677 ((((int64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df) / 2))
678
679 #define UNSIGNED_ODD(a, df) \
680 ((((uint64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df) / 2))
681
682 #define SIGNED_EXTRACT(e, o, a, df) \
683 do { \
684 e = SIGNED_EVEN(a, df); \
685 o = SIGNED_ODD(a, df); \
686 } while (0)
687
688 #define UNSIGNED_EXTRACT(e, o, a, df) \
689 do { \
690 e = UNSIGNED_EVEN(a, df); \
691 o = UNSIGNED_ODD(a, df); \
692 } while (0)
693
694 static inline int64_t msa_dotp_s_df(uint32_t df, int64_t arg1, int64_t arg2)
695 {
696 int64_t even_arg1;
697 int64_t even_arg2;
698 int64_t odd_arg1;
699 int64_t odd_arg2;
700 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
701 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
702 return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
703 }
704
705 static inline int64_t msa_dotp_u_df(uint32_t df, int64_t arg1, int64_t arg2)
706 {
707 int64_t even_arg1;
708 int64_t even_arg2;
709 int64_t odd_arg1;
710 int64_t odd_arg2;
711 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
712 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
713 return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
714 }
715
716 #define CONCATENATE_AND_SLIDE(s, k) \
717 do { \
718 for (i = 0; i < s; i++) { \
719 v[i] = pws->b[s * k + i]; \
720 v[i + s] = pwd->b[s * k + i]; \
721 } \
722 for (i = 0; i < s; i++) { \
723 pwd->b[s * k + i] = v[i + n]; \
724 } \
725 } while (0)
726
727 static inline void msa_sld_df(uint32_t df, wr_t *pwd,
728 wr_t *pws, target_ulong rt)
729 {
730 uint32_t n = rt % DF_ELEMENTS(df);
731 uint8_t v[64];
732 uint32_t i, k;
733
734 switch (df) {
735 case DF_BYTE:
736 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_BYTE), 0);
737 break;
738 case DF_HALF:
739 for (k = 0; k < 2; k++) {
740 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_HALF), k);
741 }
742 break;
743 case DF_WORD:
744 for (k = 0; k < 4; k++) {
745 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_WORD), k);
746 }
747 break;
748 case DF_DOUBLE:
749 for (k = 0; k < 8; k++) {
750 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_DOUBLE), k);
751 }
752 break;
753 default:
754 assert(0);
755 }
756 }
757
758 static inline int64_t msa_hadd_s_df(uint32_t df, int64_t arg1, int64_t arg2)
759 {
760 return SIGNED_ODD(arg1, df) + SIGNED_EVEN(arg2, df);
761 }
762
763 static inline int64_t msa_hadd_u_df(uint32_t df, int64_t arg1, int64_t arg2)
764 {
765 return UNSIGNED_ODD(arg1, df) + UNSIGNED_EVEN(arg2, df);
766 }
767
768 static inline int64_t msa_hsub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
769 {
770 return SIGNED_ODD(arg1, df) - SIGNED_EVEN(arg2, df);
771 }
772
773 static inline int64_t msa_hsub_u_df(uint32_t df, int64_t arg1, int64_t arg2)
774 {
775 return UNSIGNED_ODD(arg1, df) - UNSIGNED_EVEN(arg2, df);
776 }
777
778 static inline int64_t msa_mul_q_df(uint32_t df, int64_t arg1, int64_t arg2)
779 {
780 int64_t q_min = DF_MIN_INT(df);
781 int64_t q_max = DF_MAX_INT(df);
782
783 if (arg1 == q_min && arg2 == q_min) {
784 return q_max;
785 }
786 return (arg1 * arg2) >> (DF_BITS(df) - 1);
787 }
788
789 static inline int64_t msa_mulr_q_df(uint32_t df, int64_t arg1, int64_t arg2)
790 {
791 int64_t q_min = DF_MIN_INT(df);
792 int64_t q_max = DF_MAX_INT(df);
793 int64_t r_bit = 1 << (DF_BITS(df) - 2);
794
795 if (arg1 == q_min && arg2 == q_min) {
796 return q_max;
797 }
798 return (arg1 * arg2 + r_bit) >> (DF_BITS(df) - 1);
799 }
800
801 #define MSA_BINOP_DF(func) \
802 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
803 uint32_t wd, uint32_t ws, uint32_t wt) \
804 { \
805 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
806 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
807 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
808 \
809 switch (df) { \
810 case DF_BYTE: \
811 pwd->b[0] = msa_ ## func ## _df(df, pws->b[0], pwt->b[0]); \
812 pwd->b[1] = msa_ ## func ## _df(df, pws->b[1], pwt->b[1]); \
813 pwd->b[2] = msa_ ## func ## _df(df, pws->b[2], pwt->b[2]); \
814 pwd->b[3] = msa_ ## func ## _df(df, pws->b[3], pwt->b[3]); \
815 pwd->b[4] = msa_ ## func ## _df(df, pws->b[4], pwt->b[4]); \
816 pwd->b[5] = msa_ ## func ## _df(df, pws->b[5], pwt->b[5]); \
817 pwd->b[6] = msa_ ## func ## _df(df, pws->b[6], pwt->b[6]); \
818 pwd->b[7] = msa_ ## func ## _df(df, pws->b[7], pwt->b[7]); \
819 pwd->b[8] = msa_ ## func ## _df(df, pws->b[8], pwt->b[8]); \
820 pwd->b[9] = msa_ ## func ## _df(df, pws->b[9], pwt->b[9]); \
821 pwd->b[10] = msa_ ## func ## _df(df, pws->b[10], pwt->b[10]); \
822 pwd->b[11] = msa_ ## func ## _df(df, pws->b[11], pwt->b[11]); \
823 pwd->b[12] = msa_ ## func ## _df(df, pws->b[12], pwt->b[12]); \
824 pwd->b[13] = msa_ ## func ## _df(df, pws->b[13], pwt->b[13]); \
825 pwd->b[14] = msa_ ## func ## _df(df, pws->b[14], pwt->b[14]); \
826 pwd->b[15] = msa_ ## func ## _df(df, pws->b[15], pwt->b[15]); \
827 break; \
828 case DF_HALF: \
829 pwd->h[0] = msa_ ## func ## _df(df, pws->h[0], pwt->h[0]); \
830 pwd->h[1] = msa_ ## func ## _df(df, pws->h[1], pwt->h[1]); \
831 pwd->h[2] = msa_ ## func ## _df(df, pws->h[2], pwt->h[2]); \
832 pwd->h[3] = msa_ ## func ## _df(df, pws->h[3], pwt->h[3]); \
833 pwd->h[4] = msa_ ## func ## _df(df, pws->h[4], pwt->h[4]); \
834 pwd->h[5] = msa_ ## func ## _df(df, pws->h[5], pwt->h[5]); \
835 pwd->h[6] = msa_ ## func ## _df(df, pws->h[6], pwt->h[6]); \
836 pwd->h[7] = msa_ ## func ## _df(df, pws->h[7], pwt->h[7]); \
837 break; \
838 case DF_WORD: \
839 pwd->w[0] = msa_ ## func ## _df(df, pws->w[0], pwt->w[0]); \
840 pwd->w[1] = msa_ ## func ## _df(df, pws->w[1], pwt->w[1]); \
841 pwd->w[2] = msa_ ## func ## _df(df, pws->w[2], pwt->w[2]); \
842 pwd->w[3] = msa_ ## func ## _df(df, pws->w[3], pwt->w[3]); \
843 break; \
844 case DF_DOUBLE: \
845 pwd->d[0] = msa_ ## func ## _df(df, pws->d[0], pwt->d[0]); \
846 pwd->d[1] = msa_ ## func ## _df(df, pws->d[1], pwt->d[1]); \
847 break; \
848 default: \
849 assert(0); \
850 } \
851 }
852
853 MSA_BINOP_DF(sll)
854 MSA_BINOP_DF(sra)
855 MSA_BINOP_DF(srl)
856 MSA_BINOP_DF(bclr)
857 MSA_BINOP_DF(bset)
858 MSA_BINOP_DF(bneg)
859 MSA_BINOP_DF(addv)
860 MSA_BINOP_DF(subv)
861 MSA_BINOP_DF(max_s)
862 MSA_BINOP_DF(max_u)
863 MSA_BINOP_DF(min_s)
864 MSA_BINOP_DF(min_u)
865 MSA_BINOP_DF(max_a)
866 MSA_BINOP_DF(min_a)
867 MSA_BINOP_DF(ceq)
868 MSA_BINOP_DF(clt_s)
869 MSA_BINOP_DF(clt_u)
870 MSA_BINOP_DF(cle_s)
871 MSA_BINOP_DF(cle_u)
872 MSA_BINOP_DF(add_a)
873 MSA_BINOP_DF(adds_a)
874 MSA_BINOP_DF(adds_s)
875 MSA_BINOP_DF(adds_u)
876 MSA_BINOP_DF(ave_s)
877 MSA_BINOP_DF(ave_u)
878 MSA_BINOP_DF(aver_s)
879 MSA_BINOP_DF(aver_u)
880 MSA_BINOP_DF(subs_s)
881 MSA_BINOP_DF(subs_u)
882 MSA_BINOP_DF(subsus_u)
883 MSA_BINOP_DF(subsuu_s)
884 MSA_BINOP_DF(asub_s)
885 MSA_BINOP_DF(asub_u)
886 MSA_BINOP_DF(mulv)
887 MSA_BINOP_DF(div_s)
888 MSA_BINOP_DF(div_u)
889 MSA_BINOP_DF(mod_s)
890 MSA_BINOP_DF(mod_u)
891 MSA_BINOP_DF(dotp_s)
892 MSA_BINOP_DF(dotp_u)
893 MSA_BINOP_DF(srar)
894 MSA_BINOP_DF(srlr)
895 MSA_BINOP_DF(hadd_s)
896 MSA_BINOP_DF(hadd_u)
897 MSA_BINOP_DF(hsub_s)
898 MSA_BINOP_DF(hsub_u)
899
900 MSA_BINOP_DF(mul_q)
901 MSA_BINOP_DF(mulr_q)
902 #undef MSA_BINOP_DF
903
904 void helper_msa_sld_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
905 uint32_t ws, uint32_t rt)
906 {
907 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
908 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
909
910 msa_sld_df(df, pwd, pws, env->active_tc.gpr[rt]);
911 }
912
913 static inline int64_t msa_maddv_df(uint32_t df, int64_t dest, int64_t arg1,
914 int64_t arg2)
915 {
916 return dest + arg1 * arg2;
917 }
918
919 static inline int64_t msa_msubv_df(uint32_t df, int64_t dest, int64_t arg1,
920 int64_t arg2)
921 {
922 return dest - arg1 * arg2;
923 }
924
925 static inline int64_t msa_dpadd_s_df(uint32_t df, int64_t dest, int64_t arg1,
926 int64_t arg2)
927 {
928 int64_t even_arg1;
929 int64_t even_arg2;
930 int64_t odd_arg1;
931 int64_t odd_arg2;
932 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
933 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
934 return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
935 }
936
937 static inline int64_t msa_dpadd_u_df(uint32_t df, int64_t dest, int64_t arg1,
938 int64_t arg2)
939 {
940 int64_t even_arg1;
941 int64_t even_arg2;
942 int64_t odd_arg1;
943 int64_t odd_arg2;
944 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
945 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
946 return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
947 }
948
949 static inline int64_t msa_dpsub_s_df(uint32_t df, int64_t dest, int64_t arg1,
950 int64_t arg2)
951 {
952 int64_t even_arg1;
953 int64_t even_arg2;
954 int64_t odd_arg1;
955 int64_t odd_arg2;
956 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
957 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
958 return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
959 }
960
961 static inline int64_t msa_dpsub_u_df(uint32_t df, int64_t dest, int64_t arg1,
962 int64_t arg2)
963 {
964 int64_t even_arg1;
965 int64_t even_arg2;
966 int64_t odd_arg1;
967 int64_t odd_arg2;
968 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
969 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
970 return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
971 }
972
973 static inline int64_t msa_madd_q_df(uint32_t df, int64_t dest, int64_t arg1,
974 int64_t arg2)
975 {
976 int64_t q_prod, q_ret;
977
978 int64_t q_max = DF_MAX_INT(df);
979 int64_t q_min = DF_MIN_INT(df);
980
981 q_prod = arg1 * arg2;
982 q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod) >> (DF_BITS(df) - 1);
983
984 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
985 }
986
987 static inline int64_t msa_msub_q_df(uint32_t df, int64_t dest, int64_t arg1,
988 int64_t arg2)
989 {
990 int64_t q_prod, q_ret;
991
992 int64_t q_max = DF_MAX_INT(df);
993 int64_t q_min = DF_MIN_INT(df);
994
995 q_prod = arg1 * arg2;
996 q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod) >> (DF_BITS(df) - 1);
997
998 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
999 }
1000
1001 static inline int64_t msa_maddr_q_df(uint32_t df, int64_t dest, int64_t arg1,
1002 int64_t arg2)
1003 {
1004 int64_t q_prod, q_ret;
1005
1006 int64_t q_max = DF_MAX_INT(df);
1007 int64_t q_min = DF_MIN_INT(df);
1008 int64_t r_bit = 1 << (DF_BITS(df) - 2);
1009
1010 q_prod = arg1 * arg2;
1011 q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod + r_bit) >> (DF_BITS(df) - 1);
1012
1013 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
1014 }
1015
1016 static inline int64_t msa_msubr_q_df(uint32_t df, int64_t dest, int64_t arg1,
1017 int64_t arg2)
1018 {
1019 int64_t q_prod, q_ret;
1020
1021 int64_t q_max = DF_MAX_INT(df);
1022 int64_t q_min = DF_MIN_INT(df);
1023 int64_t r_bit = 1 << (DF_BITS(df) - 2);
1024
1025 q_prod = arg1 * arg2;
1026 q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod + r_bit) >> (DF_BITS(df) - 1);
1027
1028 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
1029 }
1030
1031 #define MSA_TEROP_DF(func) \
1032 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
1033 uint32_t ws, uint32_t wt) \
1034 { \
1035 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1036 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1037 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1038 \
1039 switch (df) { \
1040 case DF_BYTE: \
1041 pwd->b[0] = msa_ ## func ## _df(df, pwd->b[0], pws->b[0], \
1042 pwt->b[0]); \
1043 pwd->b[1] = msa_ ## func ## _df(df, pwd->b[1], pws->b[1], \
1044 pwt->b[1]); \
1045 pwd->b[2] = msa_ ## func ## _df(df, pwd->b[2], pws->b[2], \
1046 pwt->b[2]); \
1047 pwd->b[3] = msa_ ## func ## _df(df, pwd->b[3], pws->b[3], \
1048 pwt->b[3]); \
1049 pwd->b[4] = msa_ ## func ## _df(df, pwd->b[4], pws->b[4], \
1050 pwt->b[4]); \
1051 pwd->b[5] = msa_ ## func ## _df(df, pwd->b[5], pws->b[5], \
1052 pwt->b[5]); \
1053 pwd->b[6] = msa_ ## func ## _df(df, pwd->b[6], pws->b[6], \
1054 pwt->b[6]); \
1055 pwd->b[7] = msa_ ## func ## _df(df, pwd->b[7], pws->b[7], \
1056 pwt->b[7]); \
1057 pwd->b[8] = msa_ ## func ## _df(df, pwd->b[8], pws->b[8], \
1058 pwt->b[8]); \
1059 pwd->b[9] = msa_ ## func ## _df(df, pwd->b[9], pws->b[9], \
1060 pwt->b[9]); \
1061 pwd->b[10] = msa_ ## func ## _df(df, pwd->b[10], pws->b[10], \
1062 pwt->b[10]); \
1063 pwd->b[11] = msa_ ## func ## _df(df, pwd->b[11], pws->b[11], \
1064 pwt->b[11]); \
1065 pwd->b[12] = msa_ ## func ## _df(df, pwd->b[12], pws->b[12], \
1066 pwt->b[12]); \
1067 pwd->b[13] = msa_ ## func ## _df(df, pwd->b[13], pws->b[13], \
1068 pwt->b[13]); \
1069 pwd->b[14] = msa_ ## func ## _df(df, pwd->b[14], pws->b[14], \
1070 pwt->b[14]); \
1071 pwd->b[15] = msa_ ## func ## _df(df, pwd->b[15], pws->b[15], \
1072 pwt->b[15]); \
1073 break; \
1074 case DF_HALF: \
1075 pwd->h[0] = msa_ ## func ## _df(df, pwd->h[0], pws->h[0], pwt->h[0]); \
1076 pwd->h[1] = msa_ ## func ## _df(df, pwd->h[1], pws->h[1], pwt->h[1]); \
1077 pwd->h[2] = msa_ ## func ## _df(df, pwd->h[2], pws->h[2], pwt->h[2]); \
1078 pwd->h[3] = msa_ ## func ## _df(df, pwd->h[3], pws->h[3], pwt->h[3]); \
1079 pwd->h[4] = msa_ ## func ## _df(df, pwd->h[4], pws->h[4], pwt->h[4]); \
1080 pwd->h[5] = msa_ ## func ## _df(df, pwd->h[5], pws->h[5], pwt->h[5]); \
1081 pwd->h[6] = msa_ ## func ## _df(df, pwd->h[6], pws->h[6], pwt->h[6]); \
1082 pwd->h[7] = msa_ ## func ## _df(df, pwd->h[7], pws->h[7], pwt->h[7]); \
1083 break; \
1084 case DF_WORD: \
1085 pwd->w[0] = msa_ ## func ## _df(df, pwd->w[0], pws->w[0], pwt->w[0]); \
1086 pwd->w[1] = msa_ ## func ## _df(df, pwd->w[1], pws->w[1], pwt->w[1]); \
1087 pwd->w[2] = msa_ ## func ## _df(df, pwd->w[2], pws->w[2], pwt->w[2]); \
1088 pwd->w[3] = msa_ ## func ## _df(df, pwd->w[3], pws->w[3], pwt->w[3]); \
1089 break; \
1090 case DF_DOUBLE: \
1091 pwd->d[0] = msa_ ## func ## _df(df, pwd->d[0], pws->d[0], pwt->d[0]); \
1092 pwd->d[1] = msa_ ## func ## _df(df, pwd->d[1], pws->d[1], pwt->d[1]); \
1093 break; \
1094 default: \
1095 assert(0); \
1096 } \
1097 }
1098
1099 MSA_TEROP_DF(maddv)
1100 MSA_TEROP_DF(msubv)
1101 MSA_TEROP_DF(dpadd_s)
1102 MSA_TEROP_DF(dpadd_u)
1103 MSA_TEROP_DF(dpsub_s)
1104 MSA_TEROP_DF(dpsub_u)
1105 MSA_TEROP_DF(binsl)
1106 MSA_TEROP_DF(binsr)
1107 MSA_TEROP_DF(madd_q)
1108 MSA_TEROP_DF(msub_q)
1109 MSA_TEROP_DF(maddr_q)
1110 MSA_TEROP_DF(msubr_q)
1111 #undef MSA_TEROP_DF
1112
1113 static inline void msa_splat_df(uint32_t df, wr_t *pwd,
1114 wr_t *pws, target_ulong rt)
1115 {
1116 uint32_t n = rt % DF_ELEMENTS(df);
1117 uint32_t i;
1118
1119 switch (df) {
1120 case DF_BYTE:
1121 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
1122 pwd->b[i] = pws->b[n];
1123 }
1124 break;
1125 case DF_HALF:
1126 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
1127 pwd->h[i] = pws->h[n];
1128 }
1129 break;
1130 case DF_WORD:
1131 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1132 pwd->w[i] = pws->w[n];
1133 }
1134 break;
1135 case DF_DOUBLE:
1136 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1137 pwd->d[i] = pws->d[n];
1138 }
1139 break;
1140 default:
1141 assert(0);
1142 }
1143 }
1144
1145 void helper_msa_splat_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1146 uint32_t ws, uint32_t rt)
1147 {
1148 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1149 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1150
1151 msa_splat_df(df, pwd, pws, env->active_tc.gpr[rt]);
1152 }
1153
1154 #define MSA_DO_B MSA_DO(b)
1155 #define MSA_DO_H MSA_DO(h)
1156 #define MSA_DO_W MSA_DO(w)
1157 #define MSA_DO_D MSA_DO(d)
1158
1159 #define MSA_LOOP_B MSA_LOOP(B)
1160 #define MSA_LOOP_H MSA_LOOP(H)
1161 #define MSA_LOOP_W MSA_LOOP(W)
1162 #define MSA_LOOP_D MSA_LOOP(D)
1163
1164 #define MSA_LOOP_COND_B MSA_LOOP_COND(DF_BYTE)
1165 #define MSA_LOOP_COND_H MSA_LOOP_COND(DF_HALF)
1166 #define MSA_LOOP_COND_W MSA_LOOP_COND(DF_WORD)
1167 #define MSA_LOOP_COND_D MSA_LOOP_COND(DF_DOUBLE)
1168
1169 #define MSA_LOOP(DF) \
1170 do { \
1171 for (i = 0; i < (MSA_LOOP_COND_ ## DF) ; i++) { \
1172 MSA_DO_ ## DF; \
1173 } \
1174 } while (0)
1175
1176 #define MSA_FN_DF(FUNC) \
1177 void helper_msa_##FUNC(CPUMIPSState *env, uint32_t df, uint32_t wd, \
1178 uint32_t ws, uint32_t wt) \
1179 { \
1180 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1181 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1182 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1183 wr_t wx, *pwx = &wx; \
1184 uint32_t i; \
1185 switch (df) { \
1186 case DF_BYTE: \
1187 MSA_LOOP_B; \
1188 break; \
1189 case DF_HALF: \
1190 MSA_LOOP_H; \
1191 break; \
1192 case DF_WORD: \
1193 MSA_LOOP_W; \
1194 break; \
1195 case DF_DOUBLE: \
1196 MSA_LOOP_D; \
1197 break; \
1198 default: \
1199 assert(0); \
1200 } \
1201 msa_move_v(pwd, pwx); \
1202 }
1203
1204 #define MSA_LOOP_COND(DF) \
1205 (DF_ELEMENTS(DF) / 2)
1206
1207 #define Rb(pwr, i) (pwr->b[i])
1208 #define Lb(pwr, i) (pwr->b[i + DF_ELEMENTS(DF_BYTE) / 2])
1209 #define Rh(pwr, i) (pwr->h[i])
1210 #define Lh(pwr, i) (pwr->h[i + DF_ELEMENTS(DF_HALF) / 2])
1211 #define Rw(pwr, i) (pwr->w[i])
1212 #define Lw(pwr, i) (pwr->w[i + DF_ELEMENTS(DF_WORD) / 2])
1213 #define Rd(pwr, i) (pwr->d[i])
1214 #define Ld(pwr, i) (pwr->d[i + DF_ELEMENTS(DF_DOUBLE) / 2])
1215
1216 #undef MSA_LOOP_COND
1217
1218 #define MSA_LOOP_COND(DF) \
1219 (DF_ELEMENTS(DF))
1220
1221 #define MSA_DO(DF) \
1222 do { \
1223 uint32_t n = DF_ELEMENTS(df); \
1224 uint32_t k = (pwd->DF[i] & 0x3f) % (2 * n); \
1225 pwx->DF[i] = \
1226 (pwd->DF[i] & 0xc0) ? 0 : k < n ? pwt->DF[k] : pws->DF[k - n]; \
1227 } while (0)
1228 MSA_FN_DF(vshf_df)
1229 #undef MSA_DO
1230 #undef MSA_LOOP_COND
1231 #undef MSA_FN_DF
1232
1233
1234 void helper_msa_ilvev_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1235 uint32_t ws, uint32_t wt)
1236 {
1237 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1238 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1239 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1240
1241 switch (df) {
1242 case DF_BYTE:
1243 pwd->b[15] = pws->b[14];
1244 pwd->b[14] = pwt->b[14];
1245 pwd->b[13] = pws->b[12];
1246 pwd->b[12] = pwt->b[12];
1247 pwd->b[11] = pws->b[10];
1248 pwd->b[10] = pwt->b[10];
1249 pwd->b[9] = pws->b[8];
1250 pwd->b[8] = pwt->b[8];
1251 pwd->b[7] = pws->b[6];
1252 pwd->b[6] = pwt->b[6];
1253 pwd->b[5] = pws->b[4];
1254 pwd->b[4] = pwt->b[4];
1255 pwd->b[3] = pws->b[2];
1256 pwd->b[2] = pwt->b[2];
1257 pwd->b[1] = pws->b[0];
1258 pwd->b[0] = pwt->b[0];
1259 break;
1260 case DF_HALF:
1261 pwd->h[7] = pws->h[6];
1262 pwd->h[6] = pwt->h[6];
1263 pwd->h[5] = pws->h[4];
1264 pwd->h[4] = pwt->h[4];
1265 pwd->h[3] = pws->h[2];
1266 pwd->h[2] = pwt->h[2];
1267 pwd->h[1] = pws->h[0];
1268 pwd->h[0] = pwt->h[0];
1269 break;
1270 case DF_WORD:
1271 pwd->w[3] = pws->w[2];
1272 pwd->w[2] = pwt->w[2];
1273 pwd->w[1] = pws->w[0];
1274 pwd->w[0] = pwt->w[0];
1275 break;
1276 case DF_DOUBLE:
1277 pwd->d[1] = pws->d[0];
1278 pwd->d[0] = pwt->d[0];
1279 break;
1280 default:
1281 assert(0);
1282 }
1283 }
1284
1285 void helper_msa_ilvod_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1286 uint32_t ws, uint32_t wt)
1287 {
1288 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1289 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1290 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1291
1292 switch (df) {
1293 case DF_BYTE:
1294 pwd->b[0] = pwt->b[1];
1295 pwd->b[1] = pws->b[1];
1296 pwd->b[2] = pwt->b[3];
1297 pwd->b[3] = pws->b[3];
1298 pwd->b[4] = pwt->b[5];
1299 pwd->b[5] = pws->b[5];
1300 pwd->b[6] = pwt->b[7];
1301 pwd->b[7] = pws->b[7];
1302 pwd->b[8] = pwt->b[9];
1303 pwd->b[9] = pws->b[9];
1304 pwd->b[10] = pwt->b[11];
1305 pwd->b[11] = pws->b[11];
1306 pwd->b[12] = pwt->b[13];
1307 pwd->b[13] = pws->b[13];
1308 pwd->b[14] = pwt->b[15];
1309 pwd->b[15] = pws->b[15];
1310 break;
1311 case DF_HALF:
1312 pwd->h[0] = pwt->h[1];
1313 pwd->h[1] = pws->h[1];
1314 pwd->h[2] = pwt->h[3];
1315 pwd->h[3] = pws->h[3];
1316 pwd->h[4] = pwt->h[5];
1317 pwd->h[5] = pws->h[5];
1318 pwd->h[6] = pwt->h[7];
1319 pwd->h[7] = pws->h[7];
1320 break;
1321 case DF_WORD:
1322 pwd->w[0] = pwt->w[1];
1323 pwd->w[1] = pws->w[1];
1324 pwd->w[2] = pwt->w[3];
1325 pwd->w[3] = pws->w[3];
1326 break;
1327 case DF_DOUBLE:
1328 pwd->d[0] = pwt->d[1];
1329 pwd->d[1] = pws->d[1];
1330 break;
1331 default:
1332 assert(0);
1333 }
1334 }
1335
1336 void helper_msa_ilvl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1337 uint32_t ws, uint32_t wt)
1338 {
1339 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1340 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1341 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1342
1343 switch (df) {
1344 case DF_BYTE:
1345 pwd->b[0] = pwt->b[8];
1346 pwd->b[1] = pws->b[8];
1347 pwd->b[2] = pwt->b[9];
1348 pwd->b[3] = pws->b[9];
1349 pwd->b[4] = pwt->b[10];
1350 pwd->b[5] = pws->b[10];
1351 pwd->b[6] = pwt->b[11];
1352 pwd->b[7] = pws->b[11];
1353 pwd->b[8] = pwt->b[12];
1354 pwd->b[9] = pws->b[12];
1355 pwd->b[10] = pwt->b[13];
1356 pwd->b[11] = pws->b[13];
1357 pwd->b[12] = pwt->b[14];
1358 pwd->b[13] = pws->b[14];
1359 pwd->b[14] = pwt->b[15];
1360 pwd->b[15] = pws->b[15];
1361 break;
1362 case DF_HALF:
1363 pwd->h[0] = pwt->h[4];
1364 pwd->h[1] = pws->h[4];
1365 pwd->h[2] = pwt->h[5];
1366 pwd->h[3] = pws->h[5];
1367 pwd->h[4] = pwt->h[6];
1368 pwd->h[5] = pws->h[6];
1369 pwd->h[6] = pwt->h[7];
1370 pwd->h[7] = pws->h[7];
1371 break;
1372 case DF_WORD:
1373 pwd->w[0] = pwt->w[2];
1374 pwd->w[1] = pws->w[2];
1375 pwd->w[2] = pwt->w[3];
1376 pwd->w[3] = pws->w[3];
1377 break;
1378 case DF_DOUBLE:
1379 pwd->d[0] = pwt->d[1];
1380 pwd->d[1] = pws->d[1];
1381 break;
1382 default:
1383 assert(0);
1384 }
1385 }
1386
1387 void helper_msa_ilvr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1388 uint32_t ws, uint32_t wt)
1389 {
1390 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1391 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1392 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1393
1394 switch (df) {
1395 case DF_BYTE:
1396 pwd->b[15] = pws->b[7];
1397 pwd->b[14] = pwt->b[7];
1398 pwd->b[13] = pws->b[6];
1399 pwd->b[12] = pwt->b[6];
1400 pwd->b[11] = pws->b[5];
1401 pwd->b[10] = pwt->b[5];
1402 pwd->b[9] = pws->b[4];
1403 pwd->b[8] = pwt->b[4];
1404 pwd->b[7] = pws->b[3];
1405 pwd->b[6] = pwt->b[3];
1406 pwd->b[5] = pws->b[2];
1407 pwd->b[4] = pwt->b[2];
1408 pwd->b[3] = pws->b[1];
1409 pwd->b[2] = pwt->b[1];
1410 pwd->b[1] = pws->b[0];
1411 pwd->b[0] = pwt->b[0];
1412 break;
1413 case DF_HALF:
1414 pwd->h[7] = pws->h[3];
1415 pwd->h[6] = pwt->h[3];
1416 pwd->h[5] = pws->h[2];
1417 pwd->h[4] = pwt->h[2];
1418 pwd->h[3] = pws->h[1];
1419 pwd->h[2] = pwt->h[1];
1420 pwd->h[1] = pws->h[0];
1421 pwd->h[0] = pwt->h[0];
1422 break;
1423 case DF_WORD:
1424 pwd->w[3] = pws->w[1];
1425 pwd->w[2] = pwt->w[1];
1426 pwd->w[1] = pws->w[0];
1427 pwd->w[0] = pwt->w[0];
1428 break;
1429 case DF_DOUBLE:
1430 pwd->d[1] = pws->d[0];
1431 pwd->d[0] = pwt->d[0];
1432 break;
1433 default:
1434 assert(0);
1435 }
1436 }
1437
1438 void helper_msa_pckev_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1439 uint32_t ws, uint32_t wt)
1440 {
1441 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1442 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1443 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1444
1445 switch (df) {
1446 case DF_BYTE:
1447 pwd->b[15] = pws->b[14];
1448 pwd->b[13] = pws->b[10];
1449 pwd->b[11] = pws->b[6];
1450 pwd->b[9] = pws->b[2];
1451 pwd->b[7] = pwt->b[14];
1452 pwd->b[5] = pwt->b[10];
1453 pwd->b[3] = pwt->b[6];
1454 pwd->b[1] = pwt->b[2];
1455 pwd->b[14] = pws->b[12];
1456 pwd->b[10] = pws->b[4];
1457 pwd->b[6] = pwt->b[12];
1458 pwd->b[2] = pwt->b[4];
1459 pwd->b[12] = pws->b[8];
1460 pwd->b[4] = pwt->b[8];
1461 pwd->b[8] = pws->b[0];
1462 pwd->b[0] = pwt->b[0];
1463 break;
1464 case DF_HALF:
1465 pwd->h[7] = pws->h[6];
1466 pwd->h[5] = pws->h[2];
1467 pwd->h[3] = pwt->h[6];
1468 pwd->h[1] = pwt->h[2];
1469 pwd->h[6] = pws->h[4];
1470 pwd->h[2] = pwt->h[4];
1471 pwd->h[4] = pws->h[0];
1472 pwd->h[0] = pwt->h[0];
1473 break;
1474 case DF_WORD:
1475 pwd->w[3] = pws->w[2];
1476 pwd->w[1] = pwt->w[2];
1477 pwd->w[2] = pws->w[0];
1478 pwd->w[0] = pwt->w[0];
1479 break;
1480 case DF_DOUBLE:
1481 pwd->d[1] = pws->d[0];
1482 pwd->d[0] = pwt->d[0];
1483 break;
1484 default:
1485 assert(0);
1486 }
1487 }
1488
1489 void helper_msa_pckod_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1490 uint32_t ws, uint32_t wt)
1491 {
1492 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1493 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1494 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
1495
1496 switch (df) {
1497 case DF_BYTE:
1498 pwd->b[0] = pwt->b[1];
1499 pwd->b[2] = pwt->b[5];
1500 pwd->b[4] = pwt->b[9];
1501 pwd->b[6] = pwt->b[13];
1502 pwd->b[8] = pws->b[1];
1503 pwd->b[10] = pws->b[5];
1504 pwd->b[12] = pws->b[9];
1505 pwd->b[14] = pws->b[13];
1506 pwd->b[1] = pwt->b[3];
1507 pwd->b[5] = pwt->b[11];
1508 pwd->b[9] = pws->b[3];
1509 pwd->b[13] = pws->b[11];
1510 pwd->b[3] = pwt->b[7];
1511 pwd->b[11] = pws->b[7];
1512 pwd->b[7] = pwt->b[15];
1513 pwd->b[15] = pws->b[15];
1514 break;
1515 case DF_HALF:
1516 pwd->h[0] = pwt->h[1];
1517 pwd->h[2] = pwt->h[5];
1518 pwd->h[4] = pws->h[1];
1519 pwd->h[6] = pws->h[5];
1520 pwd->h[1] = pwt->h[3];
1521 pwd->h[5] = pws->h[3];
1522 pwd->h[3] = pwt->h[7];
1523 pwd->h[7] = pws->h[7];
1524 break;
1525 case DF_WORD:
1526 pwd->w[0] = pwt->w[1];
1527 pwd->w[2] = pws->w[1];
1528 pwd->w[1] = pwt->w[3];
1529 pwd->w[3] = pws->w[3];
1530 break;
1531 case DF_DOUBLE:
1532 pwd->d[0] = pwt->d[1];
1533 pwd->d[1] = pws->d[1];
1534 break;
1535 default:
1536 assert(0);
1537 }
1538 }
1539
1540
1541 void helper_msa_sldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1542 uint32_t ws, uint32_t n)
1543 {
1544 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1545 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1546
1547 msa_sld_df(df, pwd, pws, n);
1548 }
1549
1550 void helper_msa_splati_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1551 uint32_t ws, uint32_t n)
1552 {
1553 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1554 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1555
1556 msa_splat_df(df, pwd, pws, n);
1557 }
1558
1559 void helper_msa_copy_s_b(CPUMIPSState *env, uint32_t rd,
1560 uint32_t ws, uint32_t n)
1561 {
1562 n %= 16;
1563 #if defined(HOST_WORDS_BIGENDIAN)
1564 if (n < 8) {
1565 n = 8 - n - 1;
1566 } else {
1567 n = 24 - n - 1;
1568 }
1569 #endif
1570 env->active_tc.gpr[rd] = (int8_t)env->active_fpu.fpr[ws].wr.b[n];
1571 }
1572
1573 void helper_msa_copy_s_h(CPUMIPSState *env, uint32_t rd,
1574 uint32_t ws, uint32_t n)
1575 {
1576 n %= 8;
1577 #if defined(HOST_WORDS_BIGENDIAN)
1578 if (n < 4) {
1579 n = 4 - n - 1;
1580 } else {
1581 n = 12 - n - 1;
1582 }
1583 #endif
1584 env->active_tc.gpr[rd] = (int16_t)env->active_fpu.fpr[ws].wr.h[n];
1585 }
1586
1587 void helper_msa_copy_s_w(CPUMIPSState *env, uint32_t rd,
1588 uint32_t ws, uint32_t n)
1589 {
1590 n %= 4;
1591 #if defined(HOST_WORDS_BIGENDIAN)
1592 if (n < 2) {
1593 n = 2 - n - 1;
1594 } else {
1595 n = 6 - n - 1;
1596 }
1597 #endif
1598 env->active_tc.gpr[rd] = (int32_t)env->active_fpu.fpr[ws].wr.w[n];
1599 }
1600
1601 void helper_msa_copy_s_d(CPUMIPSState *env, uint32_t rd,
1602 uint32_t ws, uint32_t n)
1603 {
1604 n %= 2;
1605 env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n];
1606 }
1607
1608 void helper_msa_copy_u_b(CPUMIPSState *env, uint32_t rd,
1609 uint32_t ws, uint32_t n)
1610 {
1611 n %= 16;
1612 #if defined(HOST_WORDS_BIGENDIAN)
1613 if (n < 8) {
1614 n = 8 - n - 1;
1615 } else {
1616 n = 24 - n - 1;
1617 }
1618 #endif
1619 env->active_tc.gpr[rd] = (uint8_t)env->active_fpu.fpr[ws].wr.b[n];
1620 }
1621
1622 void helper_msa_copy_u_h(CPUMIPSState *env, uint32_t rd,
1623 uint32_t ws, uint32_t n)
1624 {
1625 n %= 8;
1626 #if defined(HOST_WORDS_BIGENDIAN)
1627 if (n < 4) {
1628 n = 4 - n - 1;
1629 } else {
1630 n = 12 - n - 1;
1631 }
1632 #endif
1633 env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n];
1634 }
1635
1636 void helper_msa_copy_u_w(CPUMIPSState *env, uint32_t rd,
1637 uint32_t ws, uint32_t n)
1638 {
1639 n %= 4;
1640 #if defined(HOST_WORDS_BIGENDIAN)
1641 if (n < 2) {
1642 n = 2 - n - 1;
1643 } else {
1644 n = 6 - n - 1;
1645 }
1646 #endif
1647 env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n];
1648 }
1649
1650 void helper_msa_insert_b(CPUMIPSState *env, uint32_t wd,
1651 uint32_t rs_num, uint32_t n)
1652 {
1653 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1654 target_ulong rs = env->active_tc.gpr[rs_num];
1655 n %= 16;
1656 #if defined(HOST_WORDS_BIGENDIAN)
1657 if (n < 8) {
1658 n = 8 - n - 1;
1659 } else {
1660 n = 24 - n - 1;
1661 }
1662 #endif
1663 pwd->b[n] = (int8_t)rs;
1664 }
1665
1666 void helper_msa_insert_h(CPUMIPSState *env, uint32_t wd,
1667 uint32_t rs_num, uint32_t n)
1668 {
1669 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1670 target_ulong rs = env->active_tc.gpr[rs_num];
1671 n %= 8;
1672 #if defined(HOST_WORDS_BIGENDIAN)
1673 if (n < 4) {
1674 n = 4 - n - 1;
1675 } else {
1676 n = 12 - n - 1;
1677 }
1678 #endif
1679 pwd->h[n] = (int16_t)rs;
1680 }
1681
1682 void helper_msa_insert_w(CPUMIPSState *env, uint32_t wd,
1683 uint32_t rs_num, uint32_t n)
1684 {
1685 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1686 target_ulong rs = env->active_tc.gpr[rs_num];
1687 n %= 4;
1688 #if defined(HOST_WORDS_BIGENDIAN)
1689 if (n < 2) {
1690 n = 2 - n - 1;
1691 } else {
1692 n = 6 - n - 1;
1693 }
1694 #endif
1695 pwd->w[n] = (int32_t)rs;
1696 }
1697
1698 void helper_msa_insert_d(CPUMIPSState *env, uint32_t wd,
1699 uint32_t rs_num, uint32_t n)
1700 {
1701 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1702 target_ulong rs = env->active_tc.gpr[rs_num];
1703 n %= 2;
1704 pwd->d[n] = (int64_t)rs;
1705 }
1706
1707 void helper_msa_insve_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1708 uint32_t ws, uint32_t n)
1709 {
1710 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1711 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1712
1713 switch (df) {
1714 case DF_BYTE:
1715 pwd->b[n] = (int8_t)pws->b[0];
1716 break;
1717 case DF_HALF:
1718 pwd->h[n] = (int16_t)pws->h[0];
1719 break;
1720 case DF_WORD:
1721 pwd->w[n] = (int32_t)pws->w[0];
1722 break;
1723 case DF_DOUBLE:
1724 pwd->d[n] = (int64_t)pws->d[0];
1725 break;
1726 default:
1727 assert(0);
1728 }
1729 }
1730
1731 void helper_msa_ctcmsa(CPUMIPSState *env, target_ulong elm, uint32_t cd)
1732 {
1733 switch (cd) {
1734 case 0:
1735 break;
1736 case 1:
1737 env->active_tc.msacsr = (int32_t)elm & MSACSR_MASK;
1738 restore_msa_fp_status(env);
1739 /* check exception */
1740 if ((GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED)
1741 & GET_FP_CAUSE(env->active_tc.msacsr)) {
1742 do_raise_exception(env, EXCP_MSAFPE, GETPC());
1743 }
1744 break;
1745 }
1746 }
1747
1748 target_ulong helper_msa_cfcmsa(CPUMIPSState *env, uint32_t cs)
1749 {
1750 switch (cs) {
1751 case 0:
1752 return env->msair;
1753 case 1:
1754 return env->active_tc.msacsr & MSACSR_MASK;
1755 }
1756 return 0;
1757 }
1758
1759 void helper_msa_move_v(CPUMIPSState *env, uint32_t wd, uint32_t ws)
1760 {
1761 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1762 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1763
1764 msa_move_v(pwd, pws);
1765 }
1766
1767 static inline int64_t msa_pcnt_df(uint32_t df, int64_t arg)
1768 {
1769 uint64_t x;
1770
1771 x = UNSIGNED(arg, df);
1772
1773 x = (x & 0x5555555555555555ULL) + ((x >> 1) & 0x5555555555555555ULL);
1774 x = (x & 0x3333333333333333ULL) + ((x >> 2) & 0x3333333333333333ULL);
1775 x = (x & 0x0F0F0F0F0F0F0F0FULL) + ((x >> 4) & 0x0F0F0F0F0F0F0F0FULL);
1776 x = (x & 0x00FF00FF00FF00FFULL) + ((x >> 8) & 0x00FF00FF00FF00FFULL);
1777 x = (x & 0x0000FFFF0000FFFFULL) + ((x >> 16) & 0x0000FFFF0000FFFFULL);
1778 x = (x & 0x00000000FFFFFFFFULL) + ((x >> 32));
1779
1780 return x;
1781 }
1782
1783 static inline int64_t msa_nlzc_df(uint32_t df, int64_t arg)
1784 {
1785 uint64_t x, y;
1786 int n, c;
1787
1788 x = UNSIGNED(arg, df);
1789 n = DF_BITS(df);
1790 c = DF_BITS(df) / 2;
1791
1792 do {
1793 y = x >> c;
1794 if (y != 0) {
1795 n = n - c;
1796 x = y;
1797 }
1798 c = c >> 1;
1799 } while (c != 0);
1800
1801 return n - x;
1802 }
1803
1804 static inline int64_t msa_nloc_df(uint32_t df, int64_t arg)
1805 {
1806 return msa_nlzc_df(df, UNSIGNED((~arg), df));
1807 }
1808
1809 void helper_msa_fill_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1810 uint32_t rs)
1811 {
1812 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1813 uint32_t i;
1814
1815 switch (df) {
1816 case DF_BYTE:
1817 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
1818 pwd->b[i] = (int8_t)env->active_tc.gpr[rs];
1819 }
1820 break;
1821 case DF_HALF:
1822 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
1823 pwd->h[i] = (int16_t)env->active_tc.gpr[rs];
1824 }
1825 break;
1826 case DF_WORD:
1827 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1828 pwd->w[i] = (int32_t)env->active_tc.gpr[rs];
1829 }
1830 break;
1831 case DF_DOUBLE:
1832 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1833 pwd->d[i] = (int64_t)env->active_tc.gpr[rs];
1834 }
1835 break;
1836 default:
1837 assert(0);
1838 }
1839 }
1840
1841 #define MSA_UNOP_DF(func) \
1842 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
1843 uint32_t wd, uint32_t ws) \
1844 { \
1845 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1846 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1847 \
1848 switch (df) { \
1849 case DF_BYTE: \
1850 pwd->b[0] = msa_ ## func ## _df(df, pws->b[0]); \
1851 pwd->b[1] = msa_ ## func ## _df(df, pws->b[1]); \
1852 pwd->b[2] = msa_ ## func ## _df(df, pws->b[2]); \
1853 pwd->b[3] = msa_ ## func ## _df(df, pws->b[3]); \
1854 pwd->b[4] = msa_ ## func ## _df(df, pws->b[4]); \
1855 pwd->b[5] = msa_ ## func ## _df(df, pws->b[5]); \
1856 pwd->b[6] = msa_ ## func ## _df(df, pws->b[6]); \
1857 pwd->b[7] = msa_ ## func ## _df(df, pws->b[7]); \
1858 pwd->b[8] = msa_ ## func ## _df(df, pws->b[8]); \
1859 pwd->b[9] = msa_ ## func ## _df(df, pws->b[9]); \
1860 pwd->b[10] = msa_ ## func ## _df(df, pws->b[10]); \
1861 pwd->b[11] = msa_ ## func ## _df(df, pws->b[11]); \
1862 pwd->b[12] = msa_ ## func ## _df(df, pws->b[12]); \
1863 pwd->b[13] = msa_ ## func ## _df(df, pws->b[13]); \
1864 pwd->b[14] = msa_ ## func ## _df(df, pws->b[14]); \
1865 pwd->b[15] = msa_ ## func ## _df(df, pws->b[15]); \
1866 break; \
1867 case DF_HALF: \
1868 pwd->h[0] = msa_ ## func ## _df(df, pws->h[0]); \
1869 pwd->h[1] = msa_ ## func ## _df(df, pws->h[1]); \
1870 pwd->h[2] = msa_ ## func ## _df(df, pws->h[2]); \
1871 pwd->h[3] = msa_ ## func ## _df(df, pws->h[3]); \
1872 pwd->h[4] = msa_ ## func ## _df(df, pws->h[4]); \
1873 pwd->h[5] = msa_ ## func ## _df(df, pws->h[5]); \
1874 pwd->h[6] = msa_ ## func ## _df(df, pws->h[6]); \
1875 pwd->h[7] = msa_ ## func ## _df(df, pws->h[7]); \
1876 break; \
1877 case DF_WORD: \
1878 pwd->w[0] = msa_ ## func ## _df(df, pws->w[0]); \
1879 pwd->w[1] = msa_ ## func ## _df(df, pws->w[1]); \
1880 pwd->w[2] = msa_ ## func ## _df(df, pws->w[2]); \
1881 pwd->w[3] = msa_ ## func ## _df(df, pws->w[3]); \
1882 break; \
1883 case DF_DOUBLE: \
1884 pwd->d[0] = msa_ ## func ## _df(df, pws->d[0]); \
1885 pwd->d[1] = msa_ ## func ## _df(df, pws->d[1]); \
1886 break; \
1887 default: \
1888 assert(0); \
1889 } \
1890 }
1891
1892 MSA_UNOP_DF(nlzc)
1893 MSA_UNOP_DF(nloc)
1894 MSA_UNOP_DF(pcnt)
1895 #undef MSA_UNOP_DF
1896
1897 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
1898 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
1899
1900 #define FLOAT_SNAN16(s) (float16_default_nan(s) ^ 0x0220)
1901 /* 0x7c20 */
1902 #define FLOAT_SNAN32(s) (float32_default_nan(s) ^ 0x00400020)
1903 /* 0x7f800020 */
1904 #define FLOAT_SNAN64(s) (float64_default_nan(s) ^ 0x0008000000000020ULL)
1905 /* 0x7ff0000000000020 */
1906
1907 static inline void clear_msacsr_cause(CPUMIPSState *env)
1908 {
1909 SET_FP_CAUSE(env->active_tc.msacsr, 0);
1910 }
1911
1912 static inline void check_msacsr_cause(CPUMIPSState *env, uintptr_t retaddr)
1913 {
1914 if ((GET_FP_CAUSE(env->active_tc.msacsr) &
1915 (GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED)) == 0) {
1916 UPDATE_FP_FLAGS(env->active_tc.msacsr,
1917 GET_FP_CAUSE(env->active_tc.msacsr));
1918 } else {
1919 do_raise_exception(env, EXCP_MSAFPE, retaddr);
1920 }
1921 }
1922
1923 /* Flush-to-zero use cases for update_msacsr() */
1924 #define CLEAR_FS_UNDERFLOW 1
1925 #define CLEAR_IS_INEXACT 2
1926 #define RECIPROCAL_INEXACT 4
1927
1928 static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
1929 {
1930 int ieee_ex;
1931
1932 int c;
1933 int cause;
1934 int enable;
1935
1936 ieee_ex = get_float_exception_flags(&env->active_tc.msa_fp_status);
1937
1938 /* QEMU softfloat does not signal all underflow cases */
1939 if (denormal) {
1940 ieee_ex |= float_flag_underflow;
1941 }
1942
1943 c = ieee_ex_to_mips(ieee_ex);
1944 enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
1945
1946 /* Set Inexact (I) when flushing inputs to zero */
1947 if ((ieee_ex & float_flag_input_denormal) &&
1948 (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
1949 if (action & CLEAR_IS_INEXACT) {
1950 c &= ~FP_INEXACT;
1951 } else {
1952 c |= FP_INEXACT;
1953 }
1954 }
1955
1956 /* Set Inexact (I) and Underflow (U) when flushing outputs to zero */
1957 if ((ieee_ex & float_flag_output_denormal) &&
1958 (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
1959 c |= FP_INEXACT;
1960 if (action & CLEAR_FS_UNDERFLOW) {
1961 c &= ~FP_UNDERFLOW;
1962 } else {
1963 c |= FP_UNDERFLOW;
1964 }
1965 }
1966
1967 /* Set Inexact (I) when Overflow (O) is not enabled */
1968 if ((c & FP_OVERFLOW) != 0 && (enable & FP_OVERFLOW) == 0) {
1969 c |= FP_INEXACT;
1970 }
1971
1972 /* Clear Exact Underflow when Underflow (U) is not enabled */
1973 if ((c & FP_UNDERFLOW) != 0 && (enable & FP_UNDERFLOW) == 0 &&
1974 (c & FP_INEXACT) == 0) {
1975 c &= ~FP_UNDERFLOW;
1976 }
1977
1978 /* Reciprocal operations set only Inexact when valid and not
1979 divide by zero */
1980 if ((action & RECIPROCAL_INEXACT) &&
1981 (c & (FP_INVALID | FP_DIV0)) == 0) {
1982 c = FP_INEXACT;
1983 }
1984
1985 cause = c & enable; /* all current enabled exceptions */
1986
1987 if (cause == 0) {
1988 /* No enabled exception, update the MSACSR Cause
1989 with all current exceptions */
1990 SET_FP_CAUSE(env->active_tc.msacsr,
1991 (GET_FP_CAUSE(env->active_tc.msacsr) | c));
1992 } else {
1993 /* Current exceptions are enabled */
1994 if ((env->active_tc.msacsr & MSACSR_NX_MASK) == 0) {
1995 /* Exception(s) will trap, update MSACSR Cause
1996 with all enabled exceptions */
1997 SET_FP_CAUSE(env->active_tc.msacsr,
1998 (GET_FP_CAUSE(env->active_tc.msacsr) | c));
1999 }
2000 }
2001
2002 return c;
2003 }
2004
2005 static inline int get_enabled_exceptions(const CPUMIPSState *env, int c)
2006 {
2007 int enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
2008 return c & enable;
2009 }
2010
2011 static inline float16 float16_from_float32(int32_t a, flag ieee,
2012 float_status *status)
2013 {
2014 float16 f_val;
2015
2016 f_val = float32_to_float16((float32)a, ieee, status);
2017
2018 return a < 0 ? (f_val | (1 << 15)) : f_val;
2019 }
2020
2021 static inline float32 float32_from_float64(int64_t a, float_status *status)
2022 {
2023 float32 f_val;
2024
2025 f_val = float64_to_float32((float64)a, status);
2026
2027 return a < 0 ? (f_val | (1 << 31)) : f_val;
2028 }
2029
2030 static inline float32 float32_from_float16(int16_t a, flag ieee,
2031 float_status *status)
2032 {
2033 float32 f_val;
2034
2035 f_val = float16_to_float32((float16)a, ieee, status);
2036
2037 return a < 0 ? (f_val | (1 << 31)) : f_val;
2038 }
2039
2040 static inline float64 float64_from_float32(int32_t a, float_status *status)
2041 {
2042 float64 f_val;
2043
2044 f_val = float32_to_float64((float64)a, status);
2045
2046 return a < 0 ? (f_val | (1ULL << 63)) : f_val;
2047 }
2048
2049 static inline float32 float32_from_q16(int16_t a, float_status *status)
2050 {
2051 float32 f_val;
2052
2053 /* conversion as integer and scaling */
2054 f_val = int32_to_float32(a, status);
2055 f_val = float32_scalbn(f_val, -15, status);
2056
2057 return f_val;
2058 }
2059
2060 static inline float64 float64_from_q32(int32_t a, float_status *status)
2061 {
2062 float64 f_val;
2063
2064 /* conversion as integer and scaling */
2065 f_val = int32_to_float64(a, status);
2066 f_val = float64_scalbn(f_val, -31, status);
2067
2068 return f_val;
2069 }
2070
2071 static inline int16_t float32_to_q16(float32 a, float_status *status)
2072 {
2073 int32_t q_val;
2074 int32_t q_min = 0xffff8000;
2075 int32_t q_max = 0x00007fff;
2076
2077 int ieee_ex;
2078
2079 if (float32_is_any_nan(a)) {
2080 float_raise(float_flag_invalid, status);
2081 return 0;
2082 }
2083
2084 /* scaling */
2085 a = float32_scalbn(a, 15, status);
2086
2087 ieee_ex = get_float_exception_flags(status);
2088 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
2089 , status);
2090
2091 if (ieee_ex & float_flag_overflow) {
2092 float_raise(float_flag_inexact, status);
2093 return (int32_t)a < 0 ? q_min : q_max;
2094 }
2095
2096 /* conversion to int */
2097 q_val = float32_to_int32(a, status);
2098
2099 ieee_ex = get_float_exception_flags(status);
2100 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
2101 , status);
2102
2103 if (ieee_ex & float_flag_invalid) {
2104 set_float_exception_flags(ieee_ex & (~float_flag_invalid)
2105 , status);
2106 float_raise(float_flag_overflow | float_flag_inexact, status);
2107 return (int32_t)a < 0 ? q_min : q_max;
2108 }
2109
2110 if (q_val < q_min) {
2111 float_raise(float_flag_overflow | float_flag_inexact, status);
2112 return (int16_t)q_min;
2113 }
2114
2115 if (q_max < q_val) {
2116 float_raise(float_flag_overflow | float_flag_inexact, status);
2117 return (int16_t)q_max;
2118 }
2119
2120 return (int16_t)q_val;
2121 }
2122
2123 static inline int32_t float64_to_q32(float64 a, float_status *status)
2124 {
2125 int64_t q_val;
2126 int64_t q_min = 0xffffffff80000000LL;
2127 int64_t q_max = 0x000000007fffffffLL;
2128
2129 int ieee_ex;
2130
2131 if (float64_is_any_nan(a)) {
2132 float_raise(float_flag_invalid, status);
2133 return 0;
2134 }
2135
2136 /* scaling */
2137 a = float64_scalbn(a, 31, status);
2138
2139 ieee_ex = get_float_exception_flags(status);
2140 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
2141 , status);
2142
2143 if (ieee_ex & float_flag_overflow) {
2144 float_raise(float_flag_inexact, status);
2145 return (int64_t)a < 0 ? q_min : q_max;
2146 }
2147
2148 /* conversion to integer */
2149 q_val = float64_to_int64(a, status);
2150
2151 ieee_ex = get_float_exception_flags(status);
2152 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
2153 , status);
2154
2155 if (ieee_ex & float_flag_invalid) {
2156 set_float_exception_flags(ieee_ex & (~float_flag_invalid)
2157 , status);
2158 float_raise(float_flag_overflow | float_flag_inexact, status);
2159 return (int64_t)a < 0 ? q_min : q_max;
2160 }
2161
2162 if (q_val < q_min) {
2163 float_raise(float_flag_overflow | float_flag_inexact, status);
2164 return (int32_t)q_min;
2165 }
2166
2167 if (q_max < q_val) {
2168 float_raise(float_flag_overflow | float_flag_inexact, status);
2169 return (int32_t)q_max;
2170 }
2171
2172 return (int32_t)q_val;
2173 }
2174
2175 #define MSA_FLOAT_COND(DEST, OP, ARG1, ARG2, BITS, QUIET) \
2176 do { \
2177 float_status *status = &env->active_tc.msa_fp_status; \
2178 int c; \
2179 int64_t cond; \
2180 set_float_exception_flags(0, status); \
2181 if (!QUIET) { \
2182 cond = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
2183 } else { \
2184 cond = float ## BITS ## _ ## OP ## _quiet(ARG1, ARG2, status); \
2185 } \
2186 DEST = cond ? M_MAX_UINT(BITS) : 0; \
2187 c = update_msacsr(env, CLEAR_IS_INEXACT, 0); \
2188 \
2189 if (get_enabled_exceptions(env, c)) { \
2190 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2191 } \
2192 } while (0)
2193
2194 #define MSA_FLOAT_AF(DEST, ARG1, ARG2, BITS, QUIET) \
2195 do { \
2196 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
2197 if ((DEST & M_MAX_UINT(BITS)) == M_MAX_UINT(BITS)) { \
2198 DEST = 0; \
2199 } \
2200 } while (0)
2201
2202 #define MSA_FLOAT_UEQ(DEST, ARG1, ARG2, BITS, QUIET) \
2203 do { \
2204 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
2205 if (DEST == 0) { \
2206 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
2207 } \
2208 } while (0)
2209
2210 #define MSA_FLOAT_NE(DEST, ARG1, ARG2, BITS, QUIET) \
2211 do { \
2212 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
2213 if (DEST == 0) { \
2214 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
2215 } \
2216 } while (0)
2217
2218 #define MSA_FLOAT_UNE(DEST, ARG1, ARG2, BITS, QUIET) \
2219 do { \
2220 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
2221 if (DEST == 0) { \
2222 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
2223 if (DEST == 0) { \
2224 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
2225 } \
2226 } \
2227 } while (0)
2228
2229 #define MSA_FLOAT_ULE(DEST, ARG1, ARG2, BITS, QUIET) \
2230 do { \
2231 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
2232 if (DEST == 0) { \
2233 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
2234 } \
2235 } while (0)
2236
2237 #define MSA_FLOAT_ULT(DEST, ARG1, ARG2, BITS, QUIET) \
2238 do { \
2239 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
2240 if (DEST == 0) { \
2241 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
2242 } \
2243 } while (0)
2244
2245 #define MSA_FLOAT_OR(DEST, ARG1, ARG2, BITS, QUIET) \
2246 do { \
2247 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
2248 if (DEST == 0) { \
2249 MSA_FLOAT_COND(DEST, le, ARG2, ARG1, BITS, QUIET); \
2250 } \
2251 } while (0)
2252
2253 static inline void compare_af(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2254 wr_t *pwt, uint32_t df, int quiet,
2255 uintptr_t retaddr)
2256 {
2257 wr_t wx, *pwx = &wx;
2258 uint32_t i;
2259
2260 clear_msacsr_cause(env);
2261
2262 switch (df) {
2263 case DF_WORD:
2264 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2265 MSA_FLOAT_AF(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2266 }
2267 break;
2268 case DF_DOUBLE:
2269 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2270 MSA_FLOAT_AF(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2271 }
2272 break;
2273 default:
2274 assert(0);
2275 }
2276
2277 check_msacsr_cause(env, retaddr);
2278
2279 msa_move_v(pwd, pwx);
2280 }
2281
2282 static inline void compare_un(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2283 wr_t *pwt, uint32_t df, int quiet,
2284 uintptr_t retaddr)
2285 {
2286 wr_t wx, *pwx = &wx;
2287 uint32_t i;
2288
2289 clear_msacsr_cause(env);
2290
2291 switch (df) {
2292 case DF_WORD:
2293 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2294 MSA_FLOAT_COND(pwx->w[i], unordered, pws->w[i], pwt->w[i], 32,
2295 quiet);
2296 }
2297 break;
2298 case DF_DOUBLE:
2299 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2300 MSA_FLOAT_COND(pwx->d[i], unordered, pws->d[i], pwt->d[i], 64,
2301 quiet);
2302 }
2303 break;
2304 default:
2305 assert(0);
2306 }
2307
2308 check_msacsr_cause(env, retaddr);
2309
2310 msa_move_v(pwd, pwx);
2311 }
2312
2313 static inline void compare_eq(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2314 wr_t *pwt, uint32_t df, int quiet,
2315 uintptr_t retaddr)
2316 {
2317 wr_t wx, *pwx = &wx;
2318 uint32_t i;
2319
2320 clear_msacsr_cause(env);
2321
2322 switch (df) {
2323 case DF_WORD:
2324 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2325 MSA_FLOAT_COND(pwx->w[i], eq, pws->w[i], pwt->w[i], 32, quiet);
2326 }
2327 break;
2328 case DF_DOUBLE:
2329 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2330 MSA_FLOAT_COND(pwx->d[i], eq, pws->d[i], pwt->d[i], 64, quiet);
2331 }
2332 break;
2333 default:
2334 assert(0);
2335 }
2336
2337 check_msacsr_cause(env, retaddr);
2338
2339 msa_move_v(pwd, pwx);
2340 }
2341
2342 static inline void compare_ueq(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2343 wr_t *pwt, uint32_t df, int quiet,
2344 uintptr_t retaddr)
2345 {
2346 wr_t wx, *pwx = &wx;
2347 uint32_t i;
2348
2349 clear_msacsr_cause(env);
2350
2351 switch (df) {
2352 case DF_WORD:
2353 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2354 MSA_FLOAT_UEQ(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2355 }
2356 break;
2357 case DF_DOUBLE:
2358 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2359 MSA_FLOAT_UEQ(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2360 }
2361 break;
2362 default:
2363 assert(0);
2364 }
2365
2366 check_msacsr_cause(env, retaddr);
2367
2368 msa_move_v(pwd, pwx);
2369 }
2370
2371 static inline void compare_lt(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2372 wr_t *pwt, uint32_t df, int quiet,
2373 uintptr_t retaddr)
2374 {
2375 wr_t wx, *pwx = &wx;
2376 uint32_t i;
2377
2378 clear_msacsr_cause(env);
2379
2380 switch (df) {
2381 case DF_WORD:
2382 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2383 MSA_FLOAT_COND(pwx->w[i], lt, pws->w[i], pwt->w[i], 32, quiet);
2384 }
2385 break;
2386 case DF_DOUBLE:
2387 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2388 MSA_FLOAT_COND(pwx->d[i], lt, pws->d[i], pwt->d[i], 64, quiet);
2389 }
2390 break;
2391 default:
2392 assert(0);
2393 }
2394
2395 check_msacsr_cause(env, retaddr);
2396
2397 msa_move_v(pwd, pwx);
2398 }
2399
2400 static inline void compare_ult(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2401 wr_t *pwt, uint32_t df, int quiet,
2402 uintptr_t retaddr)
2403 {
2404 wr_t wx, *pwx = &wx;
2405 uint32_t i;
2406
2407 clear_msacsr_cause(env);
2408
2409 switch (df) {
2410 case DF_WORD:
2411 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2412 MSA_FLOAT_ULT(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2413 }
2414 break;
2415 case DF_DOUBLE:
2416 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2417 MSA_FLOAT_ULT(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2418 }
2419 break;
2420 default:
2421 assert(0);
2422 }
2423
2424 check_msacsr_cause(env, retaddr);
2425
2426 msa_move_v(pwd, pwx);
2427 }
2428
2429 static inline void compare_le(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2430 wr_t *pwt, uint32_t df, int quiet,
2431 uintptr_t retaddr)
2432 {
2433 wr_t wx, *pwx = &wx;
2434 uint32_t i;
2435
2436 clear_msacsr_cause(env);
2437
2438 switch (df) {
2439 case DF_WORD:
2440 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2441 MSA_FLOAT_COND(pwx->w[i], le, pws->w[i], pwt->w[i], 32, quiet);
2442 }
2443 break;
2444 case DF_DOUBLE:
2445 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2446 MSA_FLOAT_COND(pwx->d[i], le, pws->d[i], pwt->d[i], 64, quiet);
2447 }
2448 break;
2449 default:
2450 assert(0);
2451 }
2452
2453 check_msacsr_cause(env, retaddr);
2454
2455 msa_move_v(pwd, pwx);
2456 }
2457
2458 static inline void compare_ule(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2459 wr_t *pwt, uint32_t df, int quiet,
2460 uintptr_t retaddr)
2461 {
2462 wr_t wx, *pwx = &wx;
2463 uint32_t i;
2464
2465 clear_msacsr_cause(env);
2466
2467 switch (df) {
2468 case DF_WORD:
2469 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2470 MSA_FLOAT_ULE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2471 }
2472 break;
2473 case DF_DOUBLE:
2474 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2475 MSA_FLOAT_ULE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2476 }
2477 break;
2478 default:
2479 assert(0);
2480 }
2481
2482 check_msacsr_cause(env, retaddr);
2483
2484 msa_move_v(pwd, pwx);
2485 }
2486
2487 static inline void compare_or(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2488 wr_t *pwt, uint32_t df, int quiet,
2489 uintptr_t retaddr)
2490 {
2491 wr_t wx, *pwx = &wx;
2492 uint32_t i;
2493
2494 clear_msacsr_cause(env);
2495
2496 switch (df) {
2497 case DF_WORD:
2498 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2499 MSA_FLOAT_OR(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2500 }
2501 break;
2502 case DF_DOUBLE:
2503 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2504 MSA_FLOAT_OR(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2505 }
2506 break;
2507 default:
2508 assert(0);
2509 }
2510
2511 check_msacsr_cause(env, retaddr);
2512
2513 msa_move_v(pwd, pwx);
2514 }
2515
2516 static inline void compare_une(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2517 wr_t *pwt, uint32_t df, int quiet,
2518 uintptr_t retaddr)
2519 {
2520 wr_t wx, *pwx = &wx;
2521 uint32_t i;
2522
2523 clear_msacsr_cause(env);
2524
2525 switch (df) {
2526 case DF_WORD:
2527 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2528 MSA_FLOAT_UNE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2529 }
2530 break;
2531 case DF_DOUBLE:
2532 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2533 MSA_FLOAT_UNE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2534 }
2535 break;
2536 default:
2537 assert(0);
2538 }
2539
2540 check_msacsr_cause(env, retaddr);
2541
2542 msa_move_v(pwd, pwx);
2543 }
2544
2545 static inline void compare_ne(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2546 wr_t *pwt, uint32_t df, int quiet,
2547 uintptr_t retaddr)
2548 {
2549 wr_t wx, *pwx = &wx;
2550 uint32_t i;
2551
2552 clear_msacsr_cause(env);
2553
2554 switch (df) {
2555 case DF_WORD:
2556 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2557 MSA_FLOAT_NE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2558 }
2559 break;
2560 case DF_DOUBLE:
2561 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2562 MSA_FLOAT_NE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2563 }
2564 break;
2565 default:
2566 assert(0);
2567 }
2568
2569 check_msacsr_cause(env, retaddr);
2570
2571 msa_move_v(pwd, pwx);
2572 }
2573
2574 void helper_msa_fcaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2575 uint32_t ws, uint32_t wt)
2576 {
2577 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2578 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2579 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2580 compare_af(env, pwd, pws, pwt, df, 1, GETPC());
2581 }
2582
2583 void helper_msa_fcun_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2584 uint32_t ws, uint32_t wt)
2585 {
2586 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2587 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2588 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2589 compare_un(env, pwd, pws, pwt, df, 1, GETPC());
2590 }
2591
2592 void helper_msa_fceq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2593 uint32_t ws, uint32_t wt)
2594 {
2595 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2596 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2597 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2598 compare_eq(env, pwd, pws, pwt, df, 1, GETPC());
2599 }
2600
2601 void helper_msa_fcueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2602 uint32_t ws, uint32_t wt)
2603 {
2604 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2605 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2606 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2607 compare_ueq(env, pwd, pws, pwt, df, 1, GETPC());
2608 }
2609
2610 void helper_msa_fclt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2611 uint32_t ws, uint32_t wt)
2612 {
2613 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2614 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2615 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2616 compare_lt(env, pwd, pws, pwt, df, 1, GETPC());
2617 }
2618
2619 void helper_msa_fcult_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2620 uint32_t ws, uint32_t wt)
2621 {
2622 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2623 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2624 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2625 compare_ult(env, pwd, pws, pwt, df, 1, GETPC());
2626 }
2627
2628 void helper_msa_fcle_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2629 uint32_t ws, uint32_t wt)
2630 {
2631 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2632 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2633 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2634 compare_le(env, pwd, pws, pwt, df, 1, GETPC());
2635 }
2636
2637 void helper_msa_fcule_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2638 uint32_t ws, uint32_t wt)
2639 {
2640 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2641 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2642 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2643 compare_ule(env, pwd, pws, pwt, df, 1, GETPC());
2644 }
2645
2646 void helper_msa_fsaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2647 uint32_t ws, uint32_t wt)
2648 {
2649 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2650 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2651 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2652 compare_af(env, pwd, pws, pwt, df, 0, GETPC());
2653 }
2654
2655 void helper_msa_fsun_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2656 uint32_t ws, uint32_t wt)
2657 {
2658 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2659 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2660 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2661 compare_un(env, pwd, pws, pwt, df, 0, GETPC());
2662 }
2663
2664 void helper_msa_fseq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2665 uint32_t ws, uint32_t wt)
2666 {
2667 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2668 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2669 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2670 compare_eq(env, pwd, pws, pwt, df, 0, GETPC());
2671 }
2672
2673 void helper_msa_fsueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2674 uint32_t ws, uint32_t wt)
2675 {
2676 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2677 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2678 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2679 compare_ueq(env, pwd, pws, pwt, df, 0, GETPC());
2680 }
2681
2682 void helper_msa_fslt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2683 uint32_t ws, uint32_t wt)
2684 {
2685 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2686 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2687 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2688 compare_lt(env, pwd, pws, pwt, df, 0, GETPC());
2689 }
2690
2691 void helper_msa_fsult_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2692 uint32_t ws, uint32_t wt)
2693 {
2694 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2695 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2696 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2697 compare_ult(env, pwd, pws, pwt, df, 0, GETPC());
2698 }
2699
2700 void helper_msa_fsle_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2701 uint32_t ws, uint32_t wt)
2702 {
2703 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2704 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2705 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2706 compare_le(env, pwd, pws, pwt, df, 0, GETPC());
2707 }
2708
2709 void helper_msa_fsule_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2710 uint32_t ws, uint32_t wt)
2711 {
2712 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2713 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2714 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2715 compare_ule(env, pwd, pws, pwt, df, 0, GETPC());
2716 }
2717
2718 void helper_msa_fcor_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2719 uint32_t ws, uint32_t wt)
2720 {
2721 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2722 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2723 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2724 compare_or(env, pwd, pws, pwt, df, 1, GETPC());
2725 }
2726
2727 void helper_msa_fcune_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2728 uint32_t ws, uint32_t wt)
2729 {
2730 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2731 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2732 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2733 compare_une(env, pwd, pws, pwt, df, 1, GETPC());
2734 }
2735
2736 void helper_msa_fcne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2737 uint32_t ws, uint32_t wt)
2738 {
2739 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2740 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2741 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2742 compare_ne(env, pwd, pws, pwt, df, 1, GETPC());
2743 }
2744
2745 void helper_msa_fsor_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2746 uint32_t ws, uint32_t wt)
2747 {
2748 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2749 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2750 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2751 compare_or(env, pwd, pws, pwt, df, 0, GETPC());
2752 }
2753
2754 void helper_msa_fsune_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2755 uint32_t ws, uint32_t wt)
2756 {
2757 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2758 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2759 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2760 compare_une(env, pwd, pws, pwt, df, 0, GETPC());
2761 }
2762
2763 void helper_msa_fsne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2764 uint32_t ws, uint32_t wt)
2765 {
2766 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2767 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2768 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2769 compare_ne(env, pwd, pws, pwt, df, 0, GETPC());
2770 }
2771
2772 #define float16_is_zero(ARG) 0
2773 #define float16_is_zero_or_denormal(ARG) 0
2774
2775 #define IS_DENORMAL(ARG, BITS) \
2776 (!float ## BITS ## _is_zero(ARG) \
2777 && float ## BITS ## _is_zero_or_denormal(ARG))
2778
2779 #define MSA_FLOAT_BINOP(DEST, OP, ARG1, ARG2, BITS) \
2780 do { \
2781 float_status *status = &env->active_tc.msa_fp_status; \
2782 int c; \
2783 \
2784 set_float_exception_flags(0, status); \
2785 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
2786 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2787 \
2788 if (get_enabled_exceptions(env, c)) { \
2789 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2790 } \
2791 } while (0)
2792
2793 void helper_msa_fadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2794 uint32_t ws, uint32_t wt)
2795 {
2796 wr_t wx, *pwx = &wx;
2797 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2798 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2799 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2800 uint32_t i;
2801
2802 clear_msacsr_cause(env);
2803
2804 switch (df) {
2805 case DF_WORD:
2806 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2807 MSA_FLOAT_BINOP(pwx->w[i], add, pws->w[i], pwt->w[i], 32);
2808 }
2809 break;
2810 case DF_DOUBLE:
2811 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2812 MSA_FLOAT_BINOP(pwx->d[i], add, pws->d[i], pwt->d[i], 64);
2813 }
2814 break;
2815 default:
2816 assert(0);
2817 }
2818
2819 check_msacsr_cause(env, GETPC());
2820 msa_move_v(pwd, pwx);
2821 }
2822
2823 void helper_msa_fsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2824 uint32_t ws, uint32_t wt)
2825 {
2826 wr_t wx, *pwx = &wx;
2827 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2828 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2829 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2830 uint32_t i;
2831
2832 clear_msacsr_cause(env);
2833
2834 switch (df) {
2835 case DF_WORD:
2836 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2837 MSA_FLOAT_BINOP(pwx->w[i], sub, pws->w[i], pwt->w[i], 32);
2838 }
2839 break;
2840 case DF_DOUBLE:
2841 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2842 MSA_FLOAT_BINOP(pwx->d[i], sub, pws->d[i], pwt->d[i], 64);
2843 }
2844 break;
2845 default:
2846 assert(0);
2847 }
2848
2849 check_msacsr_cause(env, GETPC());
2850 msa_move_v(pwd, pwx);
2851 }
2852
2853 void helper_msa_fmul_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2854 uint32_t ws, uint32_t wt)
2855 {
2856 wr_t wx, *pwx = &wx;
2857 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2858 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2859 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2860 uint32_t i;
2861
2862 clear_msacsr_cause(env);
2863
2864 switch (df) {
2865 case DF_WORD:
2866 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2867 MSA_FLOAT_BINOP(pwx->w[i], mul, pws->w[i], pwt->w[i], 32);
2868 }
2869 break;
2870 case DF_DOUBLE:
2871 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2872 MSA_FLOAT_BINOP(pwx->d[i], mul, pws->d[i], pwt->d[i], 64);
2873 }
2874 break;
2875 default:
2876 assert(0);
2877 }
2878
2879 check_msacsr_cause(env, GETPC());
2880
2881 msa_move_v(pwd, pwx);
2882 }
2883
2884 void helper_msa_fdiv_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2885 uint32_t ws, uint32_t wt)
2886 {
2887 wr_t wx, *pwx = &wx;
2888 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2889 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2890 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2891 uint32_t i;
2892
2893 clear_msacsr_cause(env);
2894
2895 switch (df) {
2896 case DF_WORD:
2897 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2898 MSA_FLOAT_BINOP(pwx->w[i], div, pws->w[i], pwt->w[i], 32);
2899 }
2900 break;
2901 case DF_DOUBLE:
2902 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2903 MSA_FLOAT_BINOP(pwx->d[i], div, pws->d[i], pwt->d[i], 64);
2904 }
2905 break;
2906 default:
2907 assert(0);
2908 }
2909
2910 check_msacsr_cause(env, GETPC());
2911
2912 msa_move_v(pwd, pwx);
2913 }
2914
2915 #define MSA_FLOAT_MULADD(DEST, ARG1, ARG2, ARG3, NEGATE, BITS) \
2916 do { \
2917 float_status *status = &env->active_tc.msa_fp_status; \
2918 int c; \
2919 \
2920 set_float_exception_flags(0, status); \
2921 DEST = float ## BITS ## _muladd(ARG2, ARG3, ARG1, NEGATE, status); \
2922 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2923 \
2924 if (get_enabled_exceptions(env, c)) { \
2925 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
2926 } \
2927 } while (0)
2928
2929 void helper_msa_fmadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2930 uint32_t ws, uint32_t wt)
2931 {
2932 wr_t wx, *pwx = &wx;
2933 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2934 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2935 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2936 uint32_t i;
2937
2938 clear_msacsr_cause(env);
2939
2940 switch (df) {
2941 case DF_WORD:
2942 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2943 MSA_FLOAT_MULADD(pwx->w[i], pwd->w[i],
2944 pws->w[i], pwt->w[i], 0, 32);
2945 }
2946 break;
2947 case DF_DOUBLE:
2948 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2949 MSA_FLOAT_MULADD(pwx->d[i], pwd->d[i],
2950 pws->d[i], pwt->d[i], 0, 64);
2951 }
2952 break;
2953 default:
2954 assert(0);
2955 }
2956
2957 check_msacsr_cause(env, GETPC());
2958
2959 msa_move_v(pwd, pwx);
2960 }
2961
2962 void helper_msa_fmsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2963 uint32_t ws, uint32_t wt)
2964 {
2965 wr_t wx, *pwx = &wx;
2966 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2967 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2968 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2969 uint32_t i;
2970
2971 clear_msacsr_cause(env);
2972
2973 switch (df) {
2974 case DF_WORD:
2975 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2976 MSA_FLOAT_MULADD(pwx->w[i], pwd->w[i],
2977 pws->w[i], pwt->w[i],
2978 float_muladd_negate_product, 32);
2979 }
2980 break;
2981 case DF_DOUBLE:
2982 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2983 MSA_FLOAT_MULADD(pwx->d[i], pwd->d[i],
2984 pws->d[i], pwt->d[i],
2985 float_muladd_negate_product, 64);
2986 }
2987 break;
2988 default:
2989 assert(0);
2990 }
2991
2992 check_msacsr_cause(env, GETPC());
2993
2994 msa_move_v(pwd, pwx);
2995 }
2996
2997 void helper_msa_fexp2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2998 uint32_t ws, uint32_t wt)
2999 {
3000 wr_t wx, *pwx = &wx;
3001 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3002 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3003 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3004 uint32_t i;
3005
3006 clear_msacsr_cause(env);
3007
3008 switch (df) {
3009 case DF_WORD:
3010 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3011 MSA_FLOAT_BINOP(pwx->w[i], scalbn, pws->w[i],
3012 pwt->w[i] > 0x200 ? 0x200 :
3013 pwt->w[i] < -0x200 ? -0x200 : pwt->w[i],
3014 32);
3015 }
3016 break;
3017 case DF_DOUBLE:
3018 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3019 MSA_FLOAT_BINOP(pwx->d[i], scalbn, pws->d[i],
3020 pwt->d[i] > 0x1000 ? 0x1000 :
3021 pwt->d[i] < -0x1000 ? -0x1000 : pwt->d[i],
3022 64);
3023 }
3024 break;
3025 default:
3026 assert(0);
3027 }
3028
3029 check_msacsr_cause(env, GETPC());
3030
3031 msa_move_v(pwd, pwx);
3032 }
3033
3034 #define MSA_FLOAT_UNOP(DEST, OP, ARG, BITS) \
3035 do { \
3036 float_status *status = &env->active_tc.msa_fp_status; \
3037 int c; \
3038 \
3039 set_float_exception_flags(0, status); \
3040 DEST = float ## BITS ## _ ## OP(ARG, status); \
3041 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
3042 \
3043 if (get_enabled_exceptions(env, c)) { \
3044 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
3045 } \
3046 } while (0)
3047
3048 void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3049 uint32_t ws, uint32_t wt)
3050 {
3051 wr_t wx, *pwx = &wx;
3052 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3053 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3054 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3055 uint32_t i;
3056
3057 clear_msacsr_cause(env);
3058
3059 switch (df) {
3060 case DF_WORD:
3061 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3062 /* Half precision floats come in two formats: standard
3063 IEEE and "ARM" format. The latter gains extra exponent
3064 range by omitting the NaN/Inf encodings. */
3065 flag ieee = 1;
3066
3067 MSA_FLOAT_BINOP(Lh(pwx, i), from_float32, pws->w[i], ieee, 16);
3068 MSA_FLOAT_BINOP(Rh(pwx, i), from_float32, pwt->w[i], ieee, 16);
3069 }
3070 break;
3071 case DF_DOUBLE:
3072 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3073 MSA_FLOAT_UNOP(Lw(pwx, i), from_float64, pws->d[i], 32);
3074 MSA_FLOAT_UNOP(Rw(pwx, i), from_float64, pwt->d[i], 32);
3075 }
3076 break;
3077 default:
3078 assert(0);
3079 }
3080
3081 check_msacsr_cause(env, GETPC());
3082 msa_move_v(pwd, pwx);
3083 }
3084
3085 #define MSA_FLOAT_UNOP_XD(DEST, OP, ARG, BITS, XBITS) \
3086 do { \
3087 float_status *status = &env->active_tc.msa_fp_status; \
3088 int c; \
3089 \
3090 set_float_exception_flags(0, status); \
3091 DEST = float ## BITS ## _ ## OP(ARG, status); \
3092 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
3093 \
3094 if (get_enabled_exceptions(env, c)) { \
3095 DEST = ((FLOAT_SNAN ## XBITS(status) >> 6) << 6) | c; \
3096 } \
3097 } while (0)
3098
3099 void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3100 uint32_t ws, uint32_t wt)
3101 {
3102 wr_t wx, *pwx = &wx;
3103 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3104 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3105 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3106 uint32_t i;
3107
3108 clear_msacsr_cause(env);
3109
3110 switch (df) {
3111 case DF_WORD:
3112 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3113 MSA_FLOAT_UNOP_XD(Lh(pwx, i), to_q16, pws->w[i], 32, 16);
3114 MSA_FLOAT_UNOP_XD(Rh(pwx, i), to_q16, pwt->w[i], 32, 16);
3115 }
3116 break;
3117 case DF_DOUBLE:
3118 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3119 MSA_FLOAT_UNOP_XD(Lw(pwx, i), to_q32, pws->d[i], 64, 32);
3120 MSA_FLOAT_UNOP_XD(Rw(pwx, i), to_q32, pwt->d[i], 64, 32);
3121 }
3122 break;
3123 default:
3124 assert(0);
3125 }
3126
3127 check_msacsr_cause(env, GETPC());
3128
3129 msa_move_v(pwd, pwx);
3130 }
3131
3132 #define NUMBER_QNAN_PAIR(ARG1, ARG2, BITS, STATUS) \
3133 !float ## BITS ## _is_any_nan(ARG1) \
3134 && float ## BITS ## _is_quiet_nan(ARG2, STATUS)
3135
3136 #define MSA_FLOAT_MAXOP(DEST, OP, ARG1, ARG2, BITS) \
3137 do { \
3138 float_status *status = &env->active_tc.msa_fp_status; \
3139 int c; \
3140 \
3141 set_float_exception_flags(0, status); \
3142 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
3143 c = update_msacsr(env, 0, 0); \
3144 \
3145 if (get_enabled_exceptions(env, c)) { \
3146 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
3147 } \
3148 } while (0)
3149
3150 #define FMAXMIN_A(F, G, X, _S, _T, BITS, STATUS) \
3151 do { \
3152 uint## BITS ##_t S = _S, T = _T; \
3153 uint## BITS ##_t as, at, xs, xt, xd; \
3154 if (NUMBER_QNAN_PAIR(S, T, BITS, STATUS)) { \
3155 T = S; \
3156 } \
3157 else if (NUMBER_QNAN_PAIR(T, S, BITS, STATUS)) { \
3158 S = T; \
3159 } \
3160 as = float## BITS ##_abs(S); \
3161 at = float## BITS ##_abs(T); \
3162 MSA_FLOAT_MAXOP(xs, F, S, T, BITS); \
3163 MSA_FLOAT_MAXOP(xt, G, S, T, BITS); \
3164 MSA_FLOAT_MAXOP(xd, F, as, at, BITS); \
3165 X = (as == at || xd == float## BITS ##_abs(xs)) ? xs : xt; \
3166 } while (0)
3167
3168 void helper_msa_fmin_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3169 uint32_t ws, uint32_t wt)
3170 {
3171 float_status *status = &env->active_tc.msa_fp_status;
3172 wr_t wx, *pwx = &wx;
3173 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3174 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3175 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3176 uint32_t i;
3177
3178 clear_msacsr_cause(env);
3179
3180 switch (df) {
3181 case DF_WORD:
3182 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3183 if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32, status)) {
3184 MSA_FLOAT_MAXOP(pwx->w[i], min, pws->w[i], pws->w[i], 32);
3185 } else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32, status)) {
3186 MSA_FLOAT_MAXOP(pwx->w[i], min, pwt->w[i], pwt->w[i], 32);
3187 } else {
3188 MSA_FLOAT_MAXOP(pwx->w[i], min, pws->w[i], pwt->w[i], 32);
3189 }
3190 }
3191 break;
3192 case DF_DOUBLE:
3193 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3194 if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64, status)) {
3195 MSA_FLOAT_MAXOP(pwx->d[i], min, pws->d[i], pws->d[i], 64);
3196 } else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64, status)) {
3197 MSA_FLOAT_MAXOP(pwx->d[i], min, pwt->d[i], pwt->d[i], 64);
3198 } else {
3199 MSA_FLOAT_MAXOP(pwx->d[i], min, pws->d[i], pwt->d[i], 64);
3200 }
3201 }
3202 break;
3203 default:
3204 assert(0);
3205 }
3206
3207 check_msacsr_cause(env, GETPC());
3208
3209 msa_move_v(pwd, pwx);
3210 }
3211
3212 void helper_msa_fmin_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3213 uint32_t ws, uint32_t wt)
3214 {
3215 float_status *status = &env->active_tc.msa_fp_status;
3216 wr_t wx, *pwx = &wx;
3217 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3218 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3219 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3220 uint32_t i;
3221
3222 clear_msacsr_cause(env);
3223
3224 switch (df) {
3225 case DF_WORD:
3226 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3227 FMAXMIN_A(min, max, pwx->w[i], pws->w[i], pwt->w[i], 32, status);
3228 }
3229 break;
3230 case DF_DOUBLE:
3231 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3232 FMAXMIN_A(min, max, pwx->d[i], pws->d[i], pwt->d[i], 64, status);
3233 }
3234 break;
3235 default:
3236 assert(0);
3237 }
3238
3239 check_msacsr_cause(env, GETPC());
3240
3241 msa_move_v(pwd, pwx);
3242 }
3243
3244 void helper_msa_fmax_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3245 uint32_t ws, uint32_t wt)
3246 {
3247 float_status *status = &env->active_tc.msa_fp_status;
3248 wr_t wx, *pwx = &wx;
3249 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3250 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3251 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3252 uint32_t i;
3253
3254 clear_msacsr_cause(env);
3255
3256 switch (df) {
3257 case DF_WORD:
3258 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3259 if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32, status)) {
3260 MSA_FLOAT_MAXOP(pwx->w[i], max, pws->w[i], pws->w[i], 32);
3261 } else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32, status)) {
3262 MSA_FLOAT_MAXOP(pwx->w[i], max, pwt->w[i], pwt->w[i], 32);
3263 } else {
3264 MSA_FLOAT_MAXOP(pwx->w[i], max, pws->w[i], pwt->w[i], 32);
3265 }
3266 }
3267 break;
3268 case DF_DOUBLE:
3269 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3270 if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64, status)) {
3271 MSA_FLOAT_MAXOP(pwx->d[i], max, pws->d[i], pws->d[i], 64);
3272 } else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64, status)) {
3273 MSA_FLOAT_MAXOP(pwx->d[i], max, pwt->d[i], pwt->d[i], 64);
3274 } else {
3275 MSA_FLOAT_MAXOP(pwx->d[i], max, pws->d[i], pwt->d[i], 64);
3276 }
3277 }
3278 break;
3279 default:
3280 assert(0);
3281 }
3282
3283 check_msacsr_cause(env, GETPC());
3284
3285 msa_move_v(pwd, pwx);
3286 }
3287
3288 void helper_msa_fmax_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3289 uint32_t ws, uint32_t wt)
3290 {
3291 float_status *status = &env->active_tc.msa_fp_status;
3292 wr_t wx, *pwx = &wx;
3293 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3294 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3295 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
3296 uint32_t i;
3297
3298 clear_msacsr_cause(env);
3299
3300 switch (df) {
3301 case DF_WORD:
3302 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3303 FMAXMIN_A(max, min, pwx->w[i], pws->w[i], pwt->w[i], 32, status);
3304 }
3305 break;
3306 case DF_DOUBLE:
3307 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3308 FMAXMIN_A(max, min, pwx->d[i], pws->d[i], pwt->d[i], 64, status);
3309 }
3310 break;
3311 default:
3312 assert(0);
3313 }
3314
3315 check_msacsr_cause(env, GETPC());
3316
3317 msa_move_v(pwd, pwx);
3318 }
3319
3320 void helper_msa_fclass_df(CPUMIPSState *env, uint32_t df,
3321 uint32_t wd, uint32_t ws)
3322 {
3323 float_status *status = &env->active_tc.msa_fp_status;
3324
3325 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3326 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3327 if (df == DF_WORD) {
3328 pwd->w[0] = float_class_s(pws->w[0], status);
3329 pwd->w[1] = float_class_s(pws->w[1], status);
3330 pwd->w[2] = float_class_s(pws->w[2], status);
3331 pwd->w[3] = float_class_s(pws->w[3], status);
3332 } else {
3333 pwd->d[0] = float_class_d(pws->d[0], status);
3334 pwd->d[1] = float_class_d(pws->d[1], status);
3335 }
3336 }
3337
3338 #define MSA_FLOAT_UNOP0(DEST, OP, ARG, BITS) \
3339 do { \
3340 float_status *status = &env->active_tc.msa_fp_status; \
3341 int c; \
3342 \
3343 set_float_exception_flags(0, status); \
3344 DEST = float ## BITS ## _ ## OP(ARG, status); \
3345 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
3346 \
3347 if (get_enabled_exceptions(env, c)) { \
3348 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
3349 } else if (float ## BITS ## _is_any_nan(ARG)) { \
3350 DEST = 0; \
3351 } \
3352 } while (0)
3353
3354 void helper_msa_ftrunc_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3355 uint32_t ws)
3356 {
3357 wr_t wx, *pwx = &wx;
3358 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3359 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3360 uint32_t i;
3361
3362 clear_msacsr_cause(env);
3363
3364 switch (df) {
3365 case DF_WORD:
3366 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3367 MSA_FLOAT_UNOP0(pwx->w[i], to_int32_round_to_zero, pws->w[i], 32);
3368 }
3369 break;
3370 case DF_DOUBLE:
3371 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3372 MSA_FLOAT_UNOP0(pwx->d[i], to_int64_round_to_zero, pws->d[i], 64);
3373 }
3374 break;
3375 default:
3376 assert(0);
3377 }
3378
3379 check_msacsr_cause(env, GETPC());
3380
3381 msa_move_v(pwd, pwx);
3382 }
3383
3384 void helper_msa_ftrunc_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3385 uint32_t ws)
3386 {
3387 wr_t wx, *pwx = &wx;
3388 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3389 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3390 uint32_t i;
3391
3392 clear_msacsr_cause(env);
3393
3394 switch (df) {
3395 case DF_WORD:
3396 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3397 MSA_FLOAT_UNOP0(pwx->w[i], to_uint32_round_to_zero, pws->w[i], 32);
3398 }
3399 break;
3400 case DF_DOUBLE:
3401 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3402 MSA_FLOAT_UNOP0(pwx->d[i], to_uint64_round_to_zero, pws->d[i], 64);
3403 }
3404 break;
3405 default:
3406 assert(0);
3407 }
3408
3409 check_msacsr_cause(env, GETPC());
3410
3411 msa_move_v(pwd, pwx);
3412 }
3413
3414 void helper_msa_fsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3415 uint32_t ws)
3416 {
3417 wr_t wx, *pwx = &wx;
3418 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3419 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3420 uint32_t i;
3421
3422 clear_msacsr_cause(env);
3423
3424 switch (df) {
3425 case DF_WORD:
3426 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3427 MSA_FLOAT_UNOP(pwx->w[i], sqrt, pws->w[i], 32);
3428 }
3429 break;
3430 case DF_DOUBLE:
3431 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3432 MSA_FLOAT_UNOP(pwx->d[i], sqrt, pws->d[i], 64);
3433 }
3434 break;
3435 default:
3436 assert(0);
3437 }
3438
3439 check_msacsr_cause(env, GETPC());
3440
3441 msa_move_v(pwd, pwx);
3442 }
3443
3444 #define MSA_FLOAT_RECIPROCAL(DEST, ARG, BITS) \
3445 do { \
3446 float_status *status = &env->active_tc.msa_fp_status; \
3447 int c; \
3448 \
3449 set_float_exception_flags(0, status); \
3450 DEST = float ## BITS ## _ ## div(FLOAT_ONE ## BITS, ARG, status); \
3451 c = update_msacsr(env, float ## BITS ## _is_infinity(ARG) || \
3452 float ## BITS ## _is_quiet_nan(DEST, status) ? \
3453 0 : RECIPROCAL_INEXACT, \
3454 IS_DENORMAL(DEST, BITS)); \
3455 \
3456 if (get_enabled_exceptions(env, c)) { \
3457 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
3458 } \
3459 } while (0)
3460
3461 void helper_msa_frsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3462 uint32_t ws)
3463 {
3464 wr_t wx, *pwx = &wx;
3465 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3466 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3467 uint32_t i;
3468
3469 clear_msacsr_cause(env);
3470
3471 switch (df) {
3472 case DF_WORD:
3473 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3474 MSA_FLOAT_RECIPROCAL(pwx->w[i], float32_sqrt(pws->w[i],
3475 &env->active_tc.msa_fp_status), 32);
3476 }
3477 break;
3478 case DF_DOUBLE:
3479 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3480 MSA_FLOAT_RECIPROCAL(pwx->d[i], float64_sqrt(pws->d[i],
3481 &env->active_tc.msa_fp_status), 64);
3482 }
3483 break;
3484 default:
3485 assert(0);
3486 }
3487
3488 check_msacsr_cause(env, GETPC());
3489
3490 msa_move_v(pwd, pwx);
3491 }
3492
3493 void helper_msa_frcp_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3494 uint32_t ws)
3495 {
3496 wr_t wx, *pwx = &wx;
3497 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3498 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3499 uint32_t i;
3500
3501 clear_msacsr_cause(env);
3502
3503 switch (df) {
3504 case DF_WORD:
3505 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3506 MSA_FLOAT_RECIPROCAL(pwx->w[i], pws->w[i], 32);
3507 }
3508 break;
3509 case DF_DOUBLE:
3510 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3511 MSA_FLOAT_RECIPROCAL(pwx->d[i], pws->d[i], 64);
3512 }
3513 break;
3514 default:
3515 assert(0);
3516 }
3517
3518 check_msacsr_cause(env, GETPC());
3519
3520 msa_move_v(pwd, pwx);
3521 }
3522
3523 void helper_msa_frint_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3524 uint32_t ws)
3525 {
3526 wr_t wx, *pwx = &wx;
3527 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3528 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3529 uint32_t i;
3530
3531 clear_msacsr_cause(env);
3532
3533 switch (df) {
3534 case DF_WORD:
3535 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3536 MSA_FLOAT_UNOP(pwx->w[i], round_to_int, pws->w[i], 32);
3537 }
3538 break;
3539 case DF_DOUBLE:
3540 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3541 MSA_FLOAT_UNOP(pwx->d[i], round_to_int, pws->d[i], 64);
3542 }
3543 break;
3544 default:
3545 assert(0);
3546 }
3547
3548 check_msacsr_cause(env, GETPC());
3549
3550 msa_move_v(pwd, pwx);
3551 }
3552
3553 #define MSA_FLOAT_LOGB(DEST, ARG, BITS) \
3554 do { \
3555 float_status *status = &env->active_tc.msa_fp_status; \
3556 int c; \
3557 \
3558 set_float_exception_flags(0, status); \
3559 set_float_rounding_mode(float_round_down, status); \
3560 DEST = float ## BITS ## _ ## log2(ARG, status); \
3561 DEST = float ## BITS ## _ ## round_to_int(DEST, status); \
3562 set_float_rounding_mode(ieee_rm[(env->active_tc.msacsr & \
3563 MSACSR_RM_MASK) >> MSACSR_RM], \
3564 status); \
3565 \
3566 set_float_exception_flags(get_float_exception_flags(status) & \
3567 (~float_flag_inexact), \
3568 status); \
3569 \
3570 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
3571 \
3572 if (get_enabled_exceptions(env, c)) { \
3573 DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \
3574 } \
3575 } while (0)
3576
3577 void helper_msa_flog2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3578 uint32_t ws)
3579 {
3580 wr_t wx, *pwx = &wx;
3581 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3582 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3583 uint32_t i;
3584
3585 clear_msacsr_cause(env);
3586
3587 switch (df) {
3588 case DF_WORD:
3589 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3590 MSA_FLOAT_LOGB(pwx->w[i], pws->w[i], 32);
3591 }
3592 break;
3593 case DF_DOUBLE:
3594 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3595 MSA_FLOAT_LOGB(pwx->d[i], pws->d[i], 64);
3596 }
3597 break;
3598 default:
3599 assert(0);
3600 }
3601
3602 check_msacsr_cause(env, GETPC());
3603
3604 msa_move_v(pwd, pwx);
3605 }
3606
3607 void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3608 uint32_t ws)
3609 {
3610 wr_t wx, *pwx = &wx;
3611 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3612 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3613 uint32_t i;
3614
3615 clear_msacsr_cause(env);
3616
3617 switch (df) {
3618 case DF_WORD:
3619 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3620 /* Half precision floats come in two formats: standard
3621 IEEE and "ARM" format. The latter gains extra exponent
3622 range by omitting the NaN/Inf encodings. */
3623 flag ieee = 1;
3624
3625 MSA_FLOAT_BINOP(pwx->w[i], from_float16, Lh(pws, i), ieee, 32);
3626 }
3627 break;
3628 case DF_DOUBLE:
3629 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3630 MSA_FLOAT_UNOP(pwx->d[i], from_float32, Lw(pws, i), 64);
3631 }
3632 break;
3633 default:
3634 assert(0);
3635 }
3636
3637 check_msacsr_cause(env, GETPC());
3638 msa_move_v(pwd, pwx);
3639 }
3640
3641 void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3642 uint32_t ws)
3643 {
3644 wr_t wx, *pwx = &wx;
3645 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3646 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3647 uint32_t i;
3648
3649 clear_msacsr_cause(env);
3650
3651 switch (df) {
3652 case DF_WORD:
3653 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3654 /* Half precision floats come in two formats: standard
3655 IEEE and "ARM" format. The latter gains extra exponent
3656 range by omitting the NaN/Inf encodings. */
3657 flag ieee = 1;
3658
3659 MSA_FLOAT_BINOP(pwx->w[i], from_float16, Rh(pws, i), ieee, 32);
3660 }
3661 break;
3662 case DF_DOUBLE:
3663 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3664 MSA_FLOAT_UNOP(pwx->d[i], from_float32, Rw(pws, i), 64);
3665 }
3666 break;
3667 default:
3668 assert(0);
3669 }
3670
3671 check_msacsr_cause(env, GETPC());
3672 msa_move_v(pwd, pwx);
3673 }
3674
3675 void helper_msa_ffql_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3676 uint32_t ws)
3677 {
3678 wr_t wx, *pwx = &wx;
3679 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3680 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3681 uint32_t i;
3682
3683 switch (df) {
3684 case DF_WORD:
3685 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3686 MSA_FLOAT_UNOP(pwx->w[i], from_q16, Lh(pws, i), 32);
3687 }
3688 break;
3689 case DF_DOUBLE:
3690 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3691 MSA_FLOAT_UNOP(pwx->d[i], from_q32, Lw(pws, i), 64);
3692 }
3693 break;
3694 default:
3695 assert(0);
3696 }
3697
3698 msa_move_v(pwd, pwx);
3699 }
3700
3701 void helper_msa_ffqr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3702 uint32_t ws)
3703 {
3704 wr_t wx, *pwx = &wx;
3705 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3706 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3707 uint32_t i;
3708
3709 switch (df) {
3710 case DF_WORD:
3711 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3712 MSA_FLOAT_UNOP(pwx->w[i], from_q16, Rh(pws, i), 32);
3713 }
3714 break;
3715 case DF_DOUBLE:
3716 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3717 MSA_FLOAT_UNOP(pwx->d[i], from_q32, Rw(pws, i), 64);
3718 }
3719 break;
3720 default:
3721 assert(0);
3722 }
3723
3724 msa_move_v(pwd, pwx);
3725 }
3726
3727 void helper_msa_ftint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3728 uint32_t ws)
3729 {
3730 wr_t wx, *pwx = &wx;
3731 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3732 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3733 uint32_t i;
3734
3735 clear_msacsr_cause(env);
3736
3737 switch (df) {
3738 case DF_WORD:
3739 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3740 MSA_FLOAT_UNOP0(pwx->w[i], to_int32, pws->w[i], 32);
3741 }
3742 break;
3743 case DF_DOUBLE:
3744 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3745 MSA_FLOAT_UNOP0(pwx->d[i], to_int64, pws->d[i], 64);
3746 }
3747 break;
3748 default:
3749 assert(0);
3750 }
3751
3752 check_msacsr_cause(env, GETPC());
3753
3754 msa_move_v(pwd, pwx);
3755 }
3756
3757 void helper_msa_ftint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3758 uint32_t ws)
3759 {
3760 wr_t wx, *pwx = &wx;
3761 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3762 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3763 uint32_t i;
3764
3765 clear_msacsr_cause(env);
3766
3767 switch (df) {
3768 case DF_WORD:
3769 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3770 MSA_FLOAT_UNOP0(pwx->w[i], to_uint32, pws->w[i], 32);
3771 }
3772 break;
3773 case DF_DOUBLE:
3774 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3775 MSA_FLOAT_UNOP0(pwx->d[i], to_uint64, pws->d[i], 64);
3776 }
3777 break;
3778 default:
3779 assert(0);
3780 }
3781
3782 check_msacsr_cause(env, GETPC());
3783
3784 msa_move_v(pwd, pwx);
3785 }
3786
3787 #define float32_from_int32 int32_to_float32
3788 #define float32_from_uint32 uint32_to_float32
3789
3790 #define float64_from_int64 int64_to_float64
3791 #define float64_from_uint64 uint64_to_float64
3792
3793 void helper_msa_ffint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3794 uint32_t ws)
3795 {
3796 wr_t wx, *pwx = &wx;
3797 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3798 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3799 uint32_t i;
3800
3801 clear_msacsr_cause(env);
3802
3803 switch (df) {
3804 case DF_WORD:
3805 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3806 MSA_FLOAT_UNOP(pwx->w[i], from_int32, pws->w[i], 32);
3807 }
3808 break;
3809 case DF_DOUBLE:
3810 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3811 MSA_FLOAT_UNOP(pwx->d[i], from_int64, pws->d[i], 64);
3812 }
3813 break;
3814 default:
3815 assert(0);
3816 }
3817
3818 check_msacsr_cause(env, GETPC());
3819
3820 msa_move_v(pwd, pwx);
3821 }
3822
3823 void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3824 uint32_t ws)
3825 {
3826 wr_t wx, *pwx = &wx;
3827 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3828 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3829 uint32_t i;
3830
3831 clear_msacsr_cause(env);
3832
3833 switch (df) {
3834 case DF_WORD:
3835 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3836 MSA_FLOAT_UNOP(pwx->w[i], from_uint32, pws->w[i], 32);
3837 }
3838 break;
3839 case DF_DOUBLE:
3840 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3841 MSA_FLOAT_UNOP(pwx->d[i], from_uint64, pws->d[i], 64);
3842 }
3843 break;
3844 default:
3845 assert(0);
3846 }
3847
3848 check_msacsr_cause(env, GETPC());
3849
3850 msa_move_v(pwd, pwx);
3851 }
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