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hw/arm/xilinx_zynq: Support up to two CPU cores
[qemu/kevin.git] / hw / arm / xilinx_zynq.c
blob7f7a3d23fbefb13b931fd2e9b895e6218673649b
1 /*
2 * Xilinx Zynq Baseboard System emulation.
3 *
4 * Copyright (c) 2010 Xilinx.
5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
6 * Copyright (c) 2012 Petalogix Pty Ltd.
7 * Written by Haibing Ma
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #include "qemu/osdep.h"
19 #include "qemu/units.h"
20 #include "qapi/error.h"
21 #include "hw/sysbus.h"
22 #include "hw/arm/boot.h"
23 #include "net/net.h"
24 #include "sysemu/sysemu.h"
25 #include "hw/boards.h"
26 #include "hw/block/flash.h"
27 #include "hw/loader.h"
28 #include "hw/adc/zynq-xadc.h"
29 #include "hw/ssi/ssi.h"
30 #include "hw/usb/chipidea.h"
31 #include "qemu/error-report.h"
32 #include "hw/sd/sdhci.h"
33 #include "hw/char/cadence_uart.h"
34 #include "hw/net/cadence_gem.h"
35 #include "hw/cpu/a9mpcore.h"
36 #include "hw/qdev-clock.h"
37 #include "sysemu/reset.h"
38 #include "qom/object.h"
39 #include "exec/tswap.h"
40 #include "target/arm/cpu-qom.h"
41
42 #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
43 OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE)
44
45 /* board base frequency: 33.333333 MHz */
46 #define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3)
47
48 #define NUM_SPI_FLASHES 4
49 #define NUM_QSPI_FLASHES 2
50 #define NUM_QSPI_BUSSES 2
51
52 #define FLASH_SIZE (64 * 1024 * 1024)
53 #define FLASH_SECTOR_SIZE (128 * 1024)
54
55 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
56
57 #define MPCORE_PERIPHBASE 0xF8F00000
58 #define ZYNQ_BOARD_MIDR 0x413FC090
59
60 static const int dma_irqs[8] = {
61 46, 47, 48, 49, 72, 73, 74, 75
62 };
63
64 #define BOARD_SETUP_ADDR 0x100
65
66 #define SLCR_LOCK_OFFSET 0x004
67 #define SLCR_UNLOCK_OFFSET 0x008
68 #define SLCR_ARM_PLL_OFFSET 0x100
69
70 #define SLCR_XILINX_UNLOCK_KEY 0xdf0d
71 #define SLCR_XILINX_LOCK_KEY 0x767b
72
73 #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */
74
75 #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \
76 extract32((x), 12, 4) << 16)
77
78 /* Write immediate val to address r0 + addr. r0 should contain base offset
79 * of the SLCR block. Clobbers r1.
80 */
81
82 #define SLCR_WRITE(addr, val) \
83 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \
84 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
85 0xe5801000 + (addr)
86
87 #define ZYNQ_MAX_CPUS 2
88
89 struct ZynqMachineState {
90 MachineState parent;
91 Clock *ps_clk;
92 ARMCPU *cpu[ZYNQ_MAX_CPUS];
93 };
94
95 static void zynq_write_board_setup(ARMCPU *cpu,
96 const struct arm_boot_info *info)
97 {
98 int n;
99 uint32_t board_setup_blob[] = {
100 0xe3a004f8, /* mov r0, #0xf8000000 */
101 SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY),
102 SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008),
103 SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY),
104 0xe12fff1e, /* bx lr */
105 };
106 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
107 board_setup_blob[n] = tswap32(board_setup_blob[n]);
108 }
109 rom_add_blob_fixed("board-setup", board_setup_blob,
110 sizeof(board_setup_blob), BOARD_SETUP_ADDR);
111 }
112
113 static struct arm_boot_info zynq_binfo = {};
114
115 static void gem_init(uint32_t base, qemu_irq irq)
116 {
117 DeviceState *dev;
118 SysBusDevice *s;
119
120 dev = qdev_new(TYPE_CADENCE_GEM);
121 qemu_configure_nic_device(dev, true, NULL);
122 object_property_set_int(OBJECT(dev), "phy-addr", 7, &error_abort);
123 s = SYS_BUS_DEVICE(dev);
124 sysbus_realize_and_unref(s, &error_fatal);
125 sysbus_mmio_map(s, 0, base);
126 sysbus_connect_irq(s, 0, irq);
127 }
128
129 static inline int zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
130 bool is_qspi, int unit0)
131 {
132 int unit = unit0;
133 DeviceState *dev;
134 SysBusDevice *busdev;
135 SSIBus *spi;
136 DeviceState *flash_dev;
137 int i, j;
138 int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1;
139 int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
140
141 dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
142 qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
143 qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
144 qdev_prop_set_uint8(dev, "num-busses", num_busses);
145 busdev = SYS_BUS_DEVICE(dev);
146 sysbus_realize_and_unref(busdev, &error_fatal);
147 sysbus_mmio_map(busdev, 0, base_addr);
148 if (is_qspi) {
149 sysbus_mmio_map(busdev, 1, 0xFC000000);
150 }
151 sysbus_connect_irq(busdev, 0, irq);
152
153 for (i = 0; i < num_busses; ++i) {
154 char bus_name[16];
155 qemu_irq cs_line;
156
157 snprintf(bus_name, 16, "spi%d", i);
158 spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);
159
160 for (j = 0; j < num_ss; ++j) {
161 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit++);
162 flash_dev = qdev_new("n25q128");
163 if (dinfo) {
164 qdev_prop_set_drive_err(flash_dev, "drive",
165 blk_by_legacy_dinfo(dinfo),
166 &error_fatal);
167 }
168 qdev_prop_set_uint8(flash_dev, "cs", j);
169 qdev_realize_and_unref(flash_dev, BUS(spi), &error_fatal);
170
171 cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
172 sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
173 }
174 }
175
176 return unit;
177 }
178
179 static void zynq_init(MachineState *machine)
180 {
181 ZynqMachineState *zynq_machine = ZYNQ_MACHINE(machine);
182 MemoryRegion *address_space_mem = get_system_memory();
183 MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
184 DeviceState *dev, *slcr;
185 SysBusDevice *busdev;
186 qemu_irq pic[64];
187 int n;
188 unsigned int smp_cpus = machine->smp.cpus;
189
190 /* max 2GB ram */
191 if (machine->ram_size > 2 * GiB) {
192 error_report("RAM size more than 2 GiB is not supported");
193 exit(EXIT_FAILURE);
194 }
195
196 for (n = 0; n < smp_cpus; n++) {
197 Object *cpuobj = object_new(machine->cpu_type);
198
199 /*
200 * By default A9 CPUs have EL3 enabled. This board does not currently
201 * support EL3 so the CPU EL3 property is disabled before realization.
202 */
203 if (object_property_find(cpuobj, "has_el3")) {
204 object_property_set_bool(cpuobj, "has_el3", false, &error_fatal);
205 }
206
207 object_property_set_int(cpuobj, "midr", ZYNQ_BOARD_MIDR,
208 &error_fatal);
209 object_property_set_int(cpuobj, "reset-cbar", MPCORE_PERIPHBASE,
210 &error_fatal);
211
212 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
213
214 zynq_machine->cpu[n] = ARM_CPU(cpuobj);
215 }
216
217 /* DDR remapped to address zero. */
218 memory_region_add_subregion(address_space_mem, 0, machine->ram);
219
220 /* 256K of on-chip memory */
221 memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB,
222 &error_fatal);
223 memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
224
225 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
226
227 /* AMD */
228 pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE,
229 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
230 FLASH_SECTOR_SIZE, 1,
231 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
232 0);
233
234 /* Create the main clock source, and feed slcr with it */
235 zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK));
236 object_property_add_child(OBJECT(zynq_machine), "ps_clk",
237 OBJECT(zynq_machine->ps_clk));
238 object_unref(OBJECT(zynq_machine->ps_clk));
239 clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY);
240
241 /* Create slcr, keep a pointer to connect clocks */
242 slcr = qdev_new("xilinx-zynq_slcr");
243 qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk);
244 sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
245 sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
246
247 dev = qdev_new(TYPE_A9MPCORE_PRIV);
248 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
249 busdev = SYS_BUS_DEVICE(dev);
250 sysbus_realize_and_unref(busdev, &error_fatal);
251 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
252 zynq_binfo.gic_cpu_if_addr = MPCORE_PERIPHBASE + 0x100;
253 sysbus_create_varargs("l2x0", MPCORE_PERIPHBASE + 0x2000, NULL);
254 for (n = 0; n < smp_cpus; n++) {
255 DeviceState *cpudev = DEVICE(zynq_machine->cpu[n]);
256 sysbus_connect_irq(busdev, (2 * n) + 0,
257 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
258 sysbus_connect_irq(busdev, (2 * n) + 1,
259 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
260 }
261
262 for (n = 0; n < 64; n++) {
263 pic[n] = qdev_get_gpio_in(dev, n);
264 }
265
266 n = zynq_init_spi_flashes(0xE0006000, pic[58 - IRQ_OFFSET], false, 0);
267 n = zynq_init_spi_flashes(0xE0007000, pic[81 - IRQ_OFFSET], false, n);
268 n = zynq_init_spi_flashes(0xE000D000, pic[51 - IRQ_OFFSET], true, n);
269
270 sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]);
271 sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]);
272
273 dev = qdev_new(TYPE_CADENCE_UART);
274 busdev = SYS_BUS_DEVICE(dev);
275 qdev_prop_set_chr(dev, "chardev", serial_hd(0));
276 qdev_connect_clock_in(dev, "refclk",
277 qdev_get_clock_out(slcr, "uart0_ref_clk"));
278 sysbus_realize_and_unref(busdev, &error_fatal);
279 sysbus_mmio_map(busdev, 0, 0xE0000000);
280 sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]);
281 dev = qdev_new(TYPE_CADENCE_UART);
282 busdev = SYS_BUS_DEVICE(dev);
283 qdev_prop_set_chr(dev, "chardev", serial_hd(1));
284 qdev_connect_clock_in(dev, "refclk",
285 qdev_get_clock_out(slcr, "uart1_ref_clk"));
286 sysbus_realize_and_unref(busdev, &error_fatal);
287 sysbus_mmio_map(busdev, 0, 0xE0001000);
288 sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]);
289
290 sysbus_create_varargs("cadence_ttc", 0xF8001000,
291 pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
292 sysbus_create_varargs("cadence_ttc", 0xF8002000,
293 pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
294
295 gem_init(0xE000B000, pic[54 - IRQ_OFFSET]);
296 gem_init(0xE000C000, pic[77 - IRQ_OFFSET]);
297
298 for (n = 0; n < 2; n++) {
299 int hci_irq = n ? 79 : 56;
300 hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000;
301 DriveInfo *di;
302 BlockBackend *blk;
303 DeviceState *carddev;
304
305 /* Compatible with:
306 * - SD Host Controller Specification Version 2.0 Part A2
307 * - SDIO Specification Version 2.0
308 * - MMC Specification Version 3.31
309 */
310 dev = qdev_new(TYPE_SYSBUS_SDHCI);
311 qdev_prop_set_uint8(dev, "sd-spec-version", 2);
312 qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES);
313 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
314 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
315 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);
316
317 di = drive_get(IF_SD, 0, n);
318 blk = di ? blk_by_legacy_dinfo(di) : NULL;
319 carddev = qdev_new(TYPE_SD_CARD);
320 qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal);
321 qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"),
322 &error_fatal);
323 }
324
325 dev = qdev_new(TYPE_ZYNQ_XADC);
326 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
327 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
328 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
329
330 dev = qdev_new("pl330");
331 object_property_set_link(OBJECT(dev), "memory",
332 OBJECT(address_space_mem),
333 &error_fatal);
334 qdev_prop_set_uint8(dev, "num_chnls", 8);
335 qdev_prop_set_uint8(dev, "num_periph_req", 4);
336 qdev_prop_set_uint8(dev, "num_events", 16);
337
338 qdev_prop_set_uint8(dev, "data_width", 64);
339 qdev_prop_set_uint8(dev, "wr_cap", 8);
340 qdev_prop_set_uint8(dev, "wr_q_dep", 16);
341 qdev_prop_set_uint8(dev, "rd_cap", 8);
342 qdev_prop_set_uint8(dev, "rd_q_dep", 16);
343 qdev_prop_set_uint16(dev, "data_buffer_dep", 256);
344
345 busdev = SYS_BUS_DEVICE(dev);
346 sysbus_realize_and_unref(busdev, &error_fatal);
347 sysbus_mmio_map(busdev, 0, 0xF8003000);
348 sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
349 for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */
350 sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
351 }
352
353 dev = qdev_new("xlnx.ps7-dev-cfg");
354 busdev = SYS_BUS_DEVICE(dev);
355 sysbus_realize_and_unref(busdev, &error_fatal);
356 sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
357 sysbus_mmio_map(busdev, 0, 0xF8007000);
358
359 zynq_binfo.ram_size = machine->ram_size;
360 zynq_binfo.board_id = 0xd32;
361 zynq_binfo.loader_start = 0;
362 zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
363 zynq_binfo.write_board_setup = zynq_write_board_setup;
364
365 arm_load_kernel(zynq_machine->cpu[0], machine, &zynq_binfo);
366 }
367
368 static void zynq_machine_class_init(ObjectClass *oc, void *data)
369 {
370 static const char * const valid_cpu_types[] = {
371 ARM_CPU_TYPE_NAME("cortex-a9"),
372 NULL
373 };
374 MachineClass *mc = MACHINE_CLASS(oc);
375 mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
376 mc->init = zynq_init;
377 mc->max_cpus = ZYNQ_MAX_CPUS;
378 mc->no_sdcard = 1;
379 mc->ignore_memory_transaction_failures = true;
380 mc->valid_cpu_types = valid_cpu_types;
381 mc->default_ram_id = "zynq.ext_ram";
382 }
383
384 static const TypeInfo zynq_machine_type = {
385 .name = TYPE_ZYNQ_MACHINE,
386 .parent = TYPE_MACHINE,
387 .class_init = zynq_machine_class_init,
388 .instance_size = sizeof(ZynqMachineState),
389 };
390
391 static void zynq_machine_register_types(void)
392 {
393 type_register_static(&zynq_machine_type);
394 }
395
396 type_init(zynq_machine_register_types)
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