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isapc: Fix segfault during initialization
[qemu/kevin.git] / hw / pxa2xx_lcd.c
blob19a09ff13166ecf8a0cfc27aeb336cc2cf7e239c
1 /*
2 * Intel XScale PXA255/270 LCDC emulation.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPLv2.
8 *
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
11 */
12
13 #include "hw.h"
14 #include "console.h"
15 #include "pxa.h"
16 #include "pixel_ops.h"
17 /* FIXME: For graphic_rotate. Should probably be done in common code. */
18 #include "sysemu.h"
19 #include "framebuffer.h"
20
21 struct DMAChannel {
22 target_phys_addr_t branch;
23 uint8_t up;
24 uint8_t palette[1024];
25 uint8_t pbuffer[1024];
26 void (*redraw)(PXA2xxLCDState *s, target_phys_addr_t addr,
27 int *miny, int *maxy);
28
29 target_phys_addr_t descriptor;
30 target_phys_addr_t source;
31 uint32_t id;
32 uint32_t command;
33 };
34
35 struct PXA2xxLCDState {
36 MemoryRegion *sysmem;
37 MemoryRegion iomem;
38 qemu_irq irq;
39 int irqlevel;
40
41 int invalidated;
42 DisplayState *ds;
43 drawfn *line_fn[2];
44 int dest_width;
45 int xres, yres;
46 int pal_for;
47 int transp;
48 enum {
49 pxa_lcdc_2bpp = 1,
50 pxa_lcdc_4bpp = 2,
51 pxa_lcdc_8bpp = 3,
52 pxa_lcdc_16bpp = 4,
53 pxa_lcdc_18bpp = 5,
54 pxa_lcdc_18pbpp = 6,
55 pxa_lcdc_19bpp = 7,
56 pxa_lcdc_19pbpp = 8,
57 pxa_lcdc_24bpp = 9,
58 pxa_lcdc_25bpp = 10,
59 } bpp;
60
61 uint32_t control[6];
62 uint32_t status[2];
63 uint32_t ovl1c[2];
64 uint32_t ovl2c[2];
65 uint32_t ccr;
66 uint32_t cmdcr;
67 uint32_t trgbr;
68 uint32_t tcr;
69 uint32_t liidr;
70 uint8_t bscntr;
71
72 struct DMAChannel dma_ch[7];
73
74 qemu_irq vsync_cb;
75 int orientation;
76 };
77
78 typedef struct QEMU_PACKED {
79 uint32_t fdaddr;
80 uint32_t fsaddr;
81 uint32_t fidr;
82 uint32_t ldcmd;
83 } PXAFrameDescriptor;
84
85 #define LCCR0 0x000 /* LCD Controller Control register 0 */
86 #define LCCR1 0x004 /* LCD Controller Control register 1 */
87 #define LCCR2 0x008 /* LCD Controller Control register 2 */
88 #define LCCR3 0x00c /* LCD Controller Control register 3 */
89 #define LCCR4 0x010 /* LCD Controller Control register 4 */
90 #define LCCR5 0x014 /* LCD Controller Control register 5 */
91
92 #define FBR0 0x020 /* DMA Channel 0 Frame Branch register */
93 #define FBR1 0x024 /* DMA Channel 1 Frame Branch register */
94 #define FBR2 0x028 /* DMA Channel 2 Frame Branch register */
95 #define FBR3 0x02c /* DMA Channel 3 Frame Branch register */
96 #define FBR4 0x030 /* DMA Channel 4 Frame Branch register */
97 #define FBR5 0x110 /* DMA Channel 5 Frame Branch register */
98 #define FBR6 0x114 /* DMA Channel 6 Frame Branch register */
99
100 #define LCSR1 0x034 /* LCD Controller Status register 1 */
101 #define LCSR0 0x038 /* LCD Controller Status register 0 */
102 #define LIIDR 0x03c /* LCD Controller Interrupt ID register */
103
104 #define TRGBR 0x040 /* TMED RGB Seed register */
105 #define TCR 0x044 /* TMED Control register */
106
107 #define OVL1C1 0x050 /* Overlay 1 Control register 1 */
108 #define OVL1C2 0x060 /* Overlay 1 Control register 2 */
109 #define OVL2C1 0x070 /* Overlay 2 Control register 1 */
110 #define OVL2C2 0x080 /* Overlay 2 Control register 2 */
111 #define CCR 0x090 /* Cursor Control register */
112
113 #define CMDCR 0x100 /* Command Control register */
114 #define PRSR 0x104 /* Panel Read Status register */
115
116 #define PXA_LCDDMA_CHANS 7
117 #define DMA_FDADR 0x00 /* Frame Descriptor Address register */
118 #define DMA_FSADR 0x04 /* Frame Source Address register */
119 #define DMA_FIDR 0x08 /* Frame ID register */
120 #define DMA_LDCMD 0x0c /* Command register */
121
122 /* LCD Buffer Strength Control register */
123 #define BSCNTR 0x04000054
124
125 /* Bitfield masks */
126 #define LCCR0_ENB (1 << 0)
127 #define LCCR0_CMS (1 << 1)
128 #define LCCR0_SDS (1 << 2)
129 #define LCCR0_LDM (1 << 3)
130 #define LCCR0_SOFM0 (1 << 4)
131 #define LCCR0_IUM (1 << 5)
132 #define LCCR0_EOFM0 (1 << 6)
133 #define LCCR0_PAS (1 << 7)
134 #define LCCR0_DPD (1 << 9)
135 #define LCCR0_DIS (1 << 10)
136 #define LCCR0_QDM (1 << 11)
137 #define LCCR0_PDD (0xff << 12)
138 #define LCCR0_BSM0 (1 << 20)
139 #define LCCR0_OUM (1 << 21)
140 #define LCCR0_LCDT (1 << 22)
141 #define LCCR0_RDSTM (1 << 23)
142 #define LCCR0_CMDIM (1 << 24)
143 #define LCCR0_OUC (1 << 25)
144 #define LCCR0_LDDALT (1 << 26)
145 #define LCCR1_PPL(x) ((x) & 0x3ff)
146 #define LCCR2_LPP(x) ((x) & 0x3ff)
147 #define LCCR3_API (15 << 16)
148 #define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8))
149 #define LCCR3_PDFOR(x) (((x) >> 30) & 3)
150 #define LCCR4_K1(x) (((x) >> 0) & 7)
151 #define LCCR4_K2(x) (((x) >> 3) & 7)
152 #define LCCR4_K3(x) (((x) >> 6) & 7)
153 #define LCCR4_PALFOR(x) (((x) >> 15) & 3)
154 #define LCCR5_SOFM(ch) (1 << (ch - 1))
155 #define LCCR5_EOFM(ch) (1 << (ch + 7))
156 #define LCCR5_BSM(ch) (1 << (ch + 15))
157 #define LCCR5_IUM(ch) (1 << (ch + 23))
158 #define OVLC1_EN (1 << 31)
159 #define CCR_CEN (1 << 31)
160 #define FBR_BRA (1 << 0)
161 #define FBR_BINT (1 << 1)
162 #define FBR_SRCADDR (0xfffffff << 4)
163 #define LCSR0_LDD (1 << 0)
164 #define LCSR0_SOF0 (1 << 1)
165 #define LCSR0_BER (1 << 2)
166 #define LCSR0_ABC (1 << 3)
167 #define LCSR0_IU0 (1 << 4)
168 #define LCSR0_IU1 (1 << 5)
169 #define LCSR0_OU (1 << 6)
170 #define LCSR0_QD (1 << 7)
171 #define LCSR0_EOF0 (1 << 8)
172 #define LCSR0_BS0 (1 << 9)
173 #define LCSR0_SINT (1 << 10)
174 #define LCSR0_RDST (1 << 11)
175 #define LCSR0_CMDINT (1 << 12)
176 #define LCSR0_BERCH(x) (((x) & 7) << 28)
177 #define LCSR1_SOF(ch) (1 << (ch - 1))
178 #define LCSR1_EOF(ch) (1 << (ch + 7))
179 #define LCSR1_BS(ch) (1 << (ch + 15))
180 #define LCSR1_IU(ch) (1 << (ch + 23))
181 #define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
182 #define LDCMD_EOFINT (1 << 21)
183 #define LDCMD_SOFINT (1 << 22)
184 #define LDCMD_PAL (1 << 26)
185
186 /* Route internal interrupt lines to the global IC */
187 static void pxa2xx_lcdc_int_update(PXA2xxLCDState *s)
188 {
189 int level = 0;
190 level |= (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LDM);
191 level |= (s->status[0] & LCSR0_SOF0) && !(s->control[0] & LCCR0_SOFM0);
192 level |= (s->status[0] & LCSR0_IU0) && !(s->control[0] & LCCR0_IUM);
193 level |= (s->status[0] & LCSR0_IU1) && !(s->control[5] & LCCR5_IUM(1));
194 level |= (s->status[0] & LCSR0_OU) && !(s->control[0] & LCCR0_OUM);
195 level |= (s->status[0] & LCSR0_QD) && !(s->control[0] & LCCR0_QDM);
196 level |= (s->status[0] & LCSR0_EOF0) && !(s->control[0] & LCCR0_EOFM0);
197 level |= (s->status[0] & LCSR0_BS0) && !(s->control[0] & LCCR0_BSM0);
198 level |= (s->status[0] & LCSR0_RDST) && !(s->control[0] & LCCR0_RDSTM);
199 level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM);
200 level |= (s->status[1] & ~s->control[5]);
201
202 qemu_set_irq(s->irq, !!level);
203 s->irqlevel = level;
204 }
205
206 /* Set Branch Status interrupt high and poke associated registers */
207 static inline void pxa2xx_dma_bs_set(PXA2xxLCDState *s, int ch)
208 {
209 int unmasked;
210 if (ch == 0) {
211 s->status[0] |= LCSR0_BS0;
212 unmasked = !(s->control[0] & LCCR0_BSM0);
213 } else {
214 s->status[1] |= LCSR1_BS(ch);
215 unmasked = !(s->control[5] & LCCR5_BSM(ch));
216 }
217
218 if (unmasked) {
219 if (s->irqlevel)
220 s->status[0] |= LCSR0_SINT;
221 else
222 s->liidr = s->dma_ch[ch].id;
223 }
224 }
225
226 /* Set Start Of Frame Status interrupt high and poke associated registers */
227 static inline void pxa2xx_dma_sof_set(PXA2xxLCDState *s, int ch)
228 {
229 int unmasked;
230 if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
231 return;
232
233 if (ch == 0) {
234 s->status[0] |= LCSR0_SOF0;
235 unmasked = !(s->control[0] & LCCR0_SOFM0);
236 } else {
237 s->status[1] |= LCSR1_SOF(ch);
238 unmasked = !(s->control[5] & LCCR5_SOFM(ch));
239 }
240
241 if (unmasked) {
242 if (s->irqlevel)
243 s->status[0] |= LCSR0_SINT;
244 else
245 s->liidr = s->dma_ch[ch].id;
246 }
247 }
248
249 /* Set End Of Frame Status interrupt high and poke associated registers */
250 static inline void pxa2xx_dma_eof_set(PXA2xxLCDState *s, int ch)
251 {
252 int unmasked;
253 if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
254 return;
255
256 if (ch == 0) {
257 s->status[0] |= LCSR0_EOF0;
258 unmasked = !(s->control[0] & LCCR0_EOFM0);
259 } else {
260 s->status[1] |= LCSR1_EOF(ch);
261 unmasked = !(s->control[5] & LCCR5_EOFM(ch));
262 }
263
264 if (unmasked) {
265 if (s->irqlevel)
266 s->status[0] |= LCSR0_SINT;
267 else
268 s->liidr = s->dma_ch[ch].id;
269 }
270 }
271
272 /* Set Bus Error Status interrupt high and poke associated registers */
273 static inline void pxa2xx_dma_ber_set(PXA2xxLCDState *s, int ch)
274 {
275 s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
276 if (s->irqlevel)
277 s->status[0] |= LCSR0_SINT;
278 else
279 s->liidr = s->dma_ch[ch].id;
280 }
281
282 /* Set Read Status interrupt high and poke associated registers */
283 static inline void pxa2xx_dma_rdst_set(PXA2xxLCDState *s)
284 {
285 s->status[0] |= LCSR0_RDST;
286 if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM))
287 s->status[0] |= LCSR0_SINT;
288 }
289
290 /* Load new Frame Descriptors from DMA */
291 static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
292 {
293 PXAFrameDescriptor desc;
294 target_phys_addr_t descptr;
295 int i;
296
297 for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
298 s->dma_ch[i].source = 0;
299
300 if (!s->dma_ch[i].up)
301 continue;
302
303 if (s->dma_ch[i].branch & FBR_BRA) {
304 descptr = s->dma_ch[i].branch & FBR_SRCADDR;
305 if (s->dma_ch[i].branch & FBR_BINT)
306 pxa2xx_dma_bs_set(s, i);
307 s->dma_ch[i].branch &= ~FBR_BRA;
308 } else
309 descptr = s->dma_ch[i].descriptor;
310
311 if (!(descptr >= PXA2XX_SDRAM_BASE && descptr +
312 sizeof(desc) <= PXA2XX_SDRAM_BASE + ram_size))
313 continue;
314
315 cpu_physical_memory_read(descptr, (void *)&desc, sizeof(desc));
316 s->dma_ch[i].descriptor = tswap32(desc.fdaddr);
317 s->dma_ch[i].source = tswap32(desc.fsaddr);
318 s->dma_ch[i].id = tswap32(desc.fidr);
319 s->dma_ch[i].command = tswap32(desc.ldcmd);
320 }
321 }
322
323 static uint64_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset,
324 unsigned size)
325 {
326 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
327 int ch;
328
329 switch (offset) {
330 case LCCR0:
331 return s->control[0];
332 case LCCR1:
333 return s->control[1];
334 case LCCR2:
335 return s->control[2];
336 case LCCR3:
337 return s->control[3];
338 case LCCR4:
339 return s->control[4];
340 case LCCR5:
341 return s->control[5];
342
343 case OVL1C1:
344 return s->ovl1c[0];
345 case OVL1C2:
346 return s->ovl1c[1];
347 case OVL2C1:
348 return s->ovl2c[0];
349 case OVL2C2:
350 return s->ovl2c[1];
351
352 case CCR:
353 return s->ccr;
354
355 case CMDCR:
356 return s->cmdcr;
357
358 case TRGBR:
359 return s->trgbr;
360 case TCR:
361 return s->tcr;
362
363 case 0x200 ... 0x1000: /* DMA per-channel registers */
364 ch = (offset - 0x200) >> 4;
365 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
366 goto fail;
367
368 switch (offset & 0xf) {
369 case DMA_FDADR:
370 return s->dma_ch[ch].descriptor;
371 case DMA_FSADR:
372 return s->dma_ch[ch].source;
373 case DMA_FIDR:
374 return s->dma_ch[ch].id;
375 case DMA_LDCMD:
376 return s->dma_ch[ch].command;
377 default:
378 goto fail;
379 }
380
381 case FBR0:
382 return s->dma_ch[0].branch;
383 case FBR1:
384 return s->dma_ch[1].branch;
385 case FBR2:
386 return s->dma_ch[2].branch;
387 case FBR3:
388 return s->dma_ch[3].branch;
389 case FBR4:
390 return s->dma_ch[4].branch;
391 case FBR5:
392 return s->dma_ch[5].branch;
393 case FBR6:
394 return s->dma_ch[6].branch;
395
396 case BSCNTR:
397 return s->bscntr;
398
399 case PRSR:
400 return 0;
401
402 case LCSR0:
403 return s->status[0];
404 case LCSR1:
405 return s->status[1];
406 case LIIDR:
407 return s->liidr;
408
409 default:
410 fail:
411 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
412 }
413
414 return 0;
415 }
416
417 static void pxa2xx_lcdc_write(void *opaque, target_phys_addr_t offset,
418 uint64_t value, unsigned size)
419 {
420 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
421 int ch;
422
423 switch (offset) {
424 case LCCR0:
425 /* ACK Quick Disable done */
426 if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB))
427 s->status[0] |= LCSR0_QD;
428
429 if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT))
430 printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
431
432 if ((s->control[3] & LCCR3_API) &&
433 (value & LCCR0_ENB) && !(value & LCCR0_LCDT))
434 s->status[0] |= LCSR0_ABC;
435
436 s->control[0] = value & 0x07ffffff;
437 pxa2xx_lcdc_int_update(s);
438
439 s->dma_ch[0].up = !!(value & LCCR0_ENB);
440 s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS);
441 break;
442
443 case LCCR1:
444 s->control[1] = value;
445 break;
446
447 case LCCR2:
448 s->control[2] = value;
449 break;
450
451 case LCCR3:
452 s->control[3] = value & 0xefffffff;
453 s->bpp = LCCR3_BPP(value);
454 break;
455
456 case LCCR4:
457 s->control[4] = value & 0x83ff81ff;
458 break;
459
460 case LCCR5:
461 s->control[5] = value & 0x3f3f3f3f;
462 break;
463
464 case OVL1C1:
465 if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN))
466 printf("%s: Overlay 1 not supported\n", __FUNCTION__);
467
468 s->ovl1c[0] = value & 0x80ffffff;
469 s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS);
470 break;
471
472 case OVL1C2:
473 s->ovl1c[1] = value & 0x000fffff;
474 break;
475
476 case OVL2C1:
477 if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN))
478 printf("%s: Overlay 2 not supported\n", __FUNCTION__);
479
480 s->ovl2c[0] = value & 0x80ffffff;
481 s->dma_ch[2].up = !!(value & OVLC1_EN);
482 s->dma_ch[3].up = !!(value & OVLC1_EN);
483 s->dma_ch[4].up = !!(value & OVLC1_EN);
484 break;
485
486 case OVL2C2:
487 s->ovl2c[1] = value & 0x007fffff;
488 break;
489
490 case CCR:
491 if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
492 printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
493
494 s->ccr = value & 0x81ffffe7;
495 s->dma_ch[5].up = !!(value & CCR_CEN);
496 break;
497
498 case CMDCR:
499 s->cmdcr = value & 0xff;
500 break;
501
502 case TRGBR:
503 s->trgbr = value & 0x00ffffff;
504 break;
505
506 case TCR:
507 s->tcr = value & 0x7fff;
508 break;
509
510 case 0x200 ... 0x1000: /* DMA per-channel registers */
511 ch = (offset - 0x200) >> 4;
512 if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
513 goto fail;
514
515 switch (offset & 0xf) {
516 case DMA_FDADR:
517 s->dma_ch[ch].descriptor = value & 0xfffffff0;
518 break;
519
520 default:
521 goto fail;
522 }
523 break;
524
525 case FBR0:
526 s->dma_ch[0].branch = value & 0xfffffff3;
527 break;
528 case FBR1:
529 s->dma_ch[1].branch = value & 0xfffffff3;
530 break;
531 case FBR2:
532 s->dma_ch[2].branch = value & 0xfffffff3;
533 break;
534 case FBR3:
535 s->dma_ch[3].branch = value & 0xfffffff3;
536 break;
537 case FBR4:
538 s->dma_ch[4].branch = value & 0xfffffff3;
539 break;
540 case FBR5:
541 s->dma_ch[5].branch = value & 0xfffffff3;
542 break;
543 case FBR6:
544 s->dma_ch[6].branch = value & 0xfffffff3;
545 break;
546
547 case BSCNTR:
548 s->bscntr = value & 0xf;
549 break;
550
551 case PRSR:
552 break;
553
554 case LCSR0:
555 s->status[0] &= ~(value & 0xfff);
556 if (value & LCSR0_BER)
557 s->status[0] &= ~LCSR0_BERCH(7);
558 break;
559
560 case LCSR1:
561 s->status[1] &= ~(value & 0x3e3f3f);
562 break;
563
564 default:
565 fail:
566 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
567 }
568 }
569
570 static const MemoryRegionOps pxa2xx_lcdc_ops = {
571 .read = pxa2xx_lcdc_read,
572 .write = pxa2xx_lcdc_write,
573 .endianness = DEVICE_NATIVE_ENDIAN,
574 };
575
576 /* Load new palette for a given DMA channel, convert to internal format */
577 static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp)
578 {
579 int i, n, format, r, g, b, alpha;
580 uint32_t *dest, *src;
581 s->pal_for = LCCR4_PALFOR(s->control[4]);
582 format = s->pal_for;
583
584 switch (bpp) {
585 case pxa_lcdc_2bpp:
586 n = 4;
587 break;
588 case pxa_lcdc_4bpp:
589 n = 16;
590 break;
591 case pxa_lcdc_8bpp:
592 n = 256;
593 break;
594 default:
595 format = 0;
596 return;
597 }
598
599 src = (uint32_t *) s->dma_ch[ch].pbuffer;
600 dest = (uint32_t *) s->dma_ch[ch].palette;
601 alpha = r = g = b = 0;
602
603 for (i = 0; i < n; i ++) {
604 switch (format) {
605 case 0: /* 16 bpp, no transparency */
606 alpha = 0;
607 if (s->control[0] & LCCR0_CMS)
608 r = g = b = *src & 0xff;
609 else {
610 r = (*src & 0xf800) >> 8;
611 g = (*src & 0x07e0) >> 3;
612 b = (*src & 0x001f) << 3;
613 }
614 break;
615 case 1: /* 16 bpp plus transparency */
616 alpha = *src & (1 << 24);
617 if (s->control[0] & LCCR0_CMS)
618 r = g = b = *src & 0xff;
619 else {
620 r = (*src & 0xf800) >> 8;
621 g = (*src & 0x07e0) >> 3;
622 b = (*src & 0x001f) << 3;
623 }
624 break;
625 case 2: /* 18 bpp plus transparency */
626 alpha = *src & (1 << 24);
627 if (s->control[0] & LCCR0_CMS)
628 r = g = b = *src & 0xff;
629 else {
630 r = (*src & 0xf80000) >> 16;
631 g = (*src & 0x00fc00) >> 8;
632 b = (*src & 0x0000f8);
633 }
634 break;
635 case 3: /* 24 bpp plus transparency */
636 alpha = *src & (1 << 24);
637 if (s->control[0] & LCCR0_CMS)
638 r = g = b = *src & 0xff;
639 else {
640 r = (*src & 0xff0000) >> 16;
641 g = (*src & 0x00ff00) >> 8;
642 b = (*src & 0x0000ff);
643 }
644 break;
645 }
646 switch (ds_get_bits_per_pixel(s->ds)) {
647 case 8:
648 *dest = rgb_to_pixel8(r, g, b) | alpha;
649 break;
650 case 15:
651 *dest = rgb_to_pixel15(r, g, b) | alpha;
652 break;
653 case 16:
654 *dest = rgb_to_pixel16(r, g, b) | alpha;
655 break;
656 case 24:
657 *dest = rgb_to_pixel24(r, g, b) | alpha;
658 break;
659 case 32:
660 *dest = rgb_to_pixel32(r, g, b) | alpha;
661 break;
662 }
663 src ++;
664 dest ++;
665 }
666 }
667
668 static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s,
669 target_phys_addr_t addr, int *miny, int *maxy)
670 {
671 int src_width, dest_width;
672 drawfn fn = NULL;
673 if (s->dest_width)
674 fn = s->line_fn[s->transp][s->bpp];
675 if (!fn)
676 return;
677
678 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
679 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
680 src_width *= 3;
681 else if (s->bpp > pxa_lcdc_16bpp)
682 src_width *= 4;
683 else if (s->bpp > pxa_lcdc_8bpp)
684 src_width *= 2;
685
686 dest_width = s->xres * s->dest_width;
687 *miny = 0;
688 framebuffer_update_display(s->ds, s->sysmem,
689 addr, s->xres, s->yres,
690 src_width, dest_width, s->dest_width,
691 s->invalidated,
692 fn, s->dma_ch[0].palette, miny, maxy);
693 }
694
695 static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s,
696 target_phys_addr_t addr, int *miny, int *maxy)
697 {
698 int src_width, dest_width;
699 drawfn fn = NULL;
700 if (s->dest_width)
701 fn = s->line_fn[s->transp][s->bpp];
702 if (!fn)
703 return;
704
705 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
706 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
707 src_width *= 3;
708 else if (s->bpp > pxa_lcdc_16bpp)
709 src_width *= 4;
710 else if (s->bpp > pxa_lcdc_8bpp)
711 src_width *= 2;
712
713 dest_width = s->yres * s->dest_width;
714 *miny = 0;
715 framebuffer_update_display(s->ds, s->sysmem,
716 addr, s->xres, s->yres,
717 src_width, s->dest_width, -dest_width,
718 s->invalidated,
719 fn, s->dma_ch[0].palette,
720 miny, maxy);
721 }
722
723 static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState *s,
724 target_phys_addr_t addr, int *miny, int *maxy)
725 {
726 int src_width, dest_width;
727 drawfn fn = NULL;
728 if (s->dest_width) {
729 fn = s->line_fn[s->transp][s->bpp];
730 }
731 if (!fn) {
732 return;
733 }
734
735 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
736 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp) {
737 src_width *= 3;
738 } else if (s->bpp > pxa_lcdc_16bpp) {
739 src_width *= 4;
740 } else if (s->bpp > pxa_lcdc_8bpp) {
741 src_width *= 2;
742 }
743
744 dest_width = s->xres * s->dest_width;
745 *miny = 0;
746 framebuffer_update_display(s->ds, s->sysmem,
747 addr, s->xres, s->yres,
748 src_width, -dest_width, -s->dest_width,
749 s->invalidated,
750 fn, s->dma_ch[0].palette, miny, maxy);
751 }
752
753 static void pxa2xx_lcdc_dma0_redraw_rot270(PXA2xxLCDState *s,
754 target_phys_addr_t addr, int *miny, int *maxy)
755 {
756 int src_width, dest_width;
757 drawfn fn = NULL;
758 if (s->dest_width) {
759 fn = s->line_fn[s->transp][s->bpp];
760 }
761 if (!fn) {
762 return;
763 }
764
765 src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */
766 if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp) {
767 src_width *= 3;
768 } else if (s->bpp > pxa_lcdc_16bpp) {
769 src_width *= 4;
770 } else if (s->bpp > pxa_lcdc_8bpp) {
771 src_width *= 2;
772 }
773
774 dest_width = s->yres * s->dest_width;
775 *miny = 0;
776 framebuffer_update_display(s->ds, s->sysmem,
777 addr, s->xres, s->yres,
778 src_width, -s->dest_width, dest_width,
779 s->invalidated,
780 fn, s->dma_ch[0].palette,
781 miny, maxy);
782 }
783
784 static void pxa2xx_lcdc_resize(PXA2xxLCDState *s)
785 {
786 int width, height;
787 if (!(s->control[0] & LCCR0_ENB))
788 return;
789
790 width = LCCR1_PPL(s->control[1]) + 1;
791 height = LCCR2_LPP(s->control[2]) + 1;
792
793 if (width != s->xres || height != s->yres) {
794 if (s->orientation == 90 || s->orientation == 270) {
795 qemu_console_resize(s->ds, height, width);
796 } else {
797 qemu_console_resize(s->ds, width, height);
798 }
799 s->invalidated = 1;
800 s->xres = width;
801 s->yres = height;
802 }
803 }
804
805 static void pxa2xx_update_display(void *opaque)
806 {
807 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
808 target_phys_addr_t fbptr;
809 int miny, maxy;
810 int ch;
811 if (!(s->control[0] & LCCR0_ENB))
812 return;
813
814 pxa2xx_descriptor_load(s);
815
816 pxa2xx_lcdc_resize(s);
817 miny = s->yres;
818 maxy = 0;
819 s->transp = s->dma_ch[2].up || s->dma_ch[3].up;
820 /* Note: With overlay planes the order depends on LCCR0 bit 25. */
821 for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++)
822 if (s->dma_ch[ch].up) {
823 if (!s->dma_ch[ch].source) {
824 pxa2xx_dma_ber_set(s, ch);
825 continue;
826 }
827 fbptr = s->dma_ch[ch].source;
828 if (!(fbptr >= PXA2XX_SDRAM_BASE &&
829 fbptr <= PXA2XX_SDRAM_BASE + ram_size)) {
830 pxa2xx_dma_ber_set(s, ch);
831 continue;
832 }
833
834 if (s->dma_ch[ch].command & LDCMD_PAL) {
835 cpu_physical_memory_read(fbptr, s->dma_ch[ch].pbuffer,
836 MAX(LDCMD_LENGTH(s->dma_ch[ch].command),
837 sizeof(s->dma_ch[ch].pbuffer)));
838 pxa2xx_palette_parse(s, ch, s->bpp);
839 } else {
840 /* Do we need to reparse palette */
841 if (LCCR4_PALFOR(s->control[4]) != s->pal_for)
842 pxa2xx_palette_parse(s, ch, s->bpp);
843
844 /* ACK frame start */
845 pxa2xx_dma_sof_set(s, ch);
846
847 s->dma_ch[ch].redraw(s, fbptr, &miny, &maxy);
848 s->invalidated = 0;
849
850 /* ACK frame completed */
851 pxa2xx_dma_eof_set(s, ch);
852 }
853 }
854
855 if (s->control[0] & LCCR0_DIS) {
856 /* ACK last frame completed */
857 s->control[0] &= ~LCCR0_ENB;
858 s->status[0] |= LCSR0_LDD;
859 }
860
861 if (miny >= 0) {
862 switch (s->orientation) {
863 case 0:
864 dpy_update(s->ds, 0, miny, s->xres, maxy - miny + 1);
865 break;
866 case 90:
867 dpy_update(s->ds, miny, 0, maxy - miny + 1, s->xres);
868 break;
869 case 180:
870 maxy = s->yres - maxy - 1;
871 miny = s->yres - miny - 1;
872 dpy_update(s->ds, 0, maxy, s->xres, miny - maxy + 1);
873 break;
874 case 270:
875 maxy = s->yres - maxy - 1;
876 miny = s->yres - miny - 1;
877 dpy_update(s->ds, maxy, 0, miny - maxy + 1, s->xres);
878 break;
879 }
880 }
881 pxa2xx_lcdc_int_update(s);
882
883 qemu_irq_raise(s->vsync_cb);
884 }
885
886 static void pxa2xx_invalidate_display(void *opaque)
887 {
888 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
889 s->invalidated = 1;
890 }
891
892 static void pxa2xx_screen_dump(void *opaque, const char *filename)
893 {
894 /* TODO */
895 }
896
897 static void pxa2xx_lcdc_orientation(void *opaque, int angle)
898 {
899 PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
900
901 switch (angle) {
902 case 0:
903 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot0;
904 break;
905 case 90:
906 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot90;
907 break;
908 case 180:
909 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot180;
910 break;
911 case 270:
912 s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot270;
913 break;
914 }
915
916 s->orientation = angle;
917 s->xres = s->yres = -1;
918 pxa2xx_lcdc_resize(s);
919 }
920
921 static const VMStateDescription vmstate_dma_channel = {
922 .name = "dma_channel",
923 .version_id = 0,
924 .minimum_version_id = 0,
925 .minimum_version_id_old = 0,
926 .fields = (VMStateField[]) {
927 VMSTATE_UINTTL(branch, struct DMAChannel),
928 VMSTATE_UINT8(up, struct DMAChannel),
929 VMSTATE_BUFFER(pbuffer, struct DMAChannel),
930 VMSTATE_UINTTL(descriptor, struct DMAChannel),
931 VMSTATE_UINTTL(source, struct DMAChannel),
932 VMSTATE_UINT32(id, struct DMAChannel),
933 VMSTATE_UINT32(command, struct DMAChannel),
934 VMSTATE_END_OF_LIST()
935 }
936 };
937
938 static int pxa2xx_lcdc_post_load(void *opaque, int version_id)
939 {
940 PXA2xxLCDState *s = opaque;
941
942 s->bpp = LCCR3_BPP(s->control[3]);
943 s->xres = s->yres = s->pal_for = -1;
944
945 return 0;
946 }
947
948 static const VMStateDescription vmstate_pxa2xx_lcdc = {
949 .name = "pxa2xx_lcdc",
950 .version_id = 0,
951 .minimum_version_id = 0,
952 .minimum_version_id_old = 0,
953 .post_load = pxa2xx_lcdc_post_load,
954 .fields = (VMStateField[]) {
955 VMSTATE_INT32(irqlevel, PXA2xxLCDState),
956 VMSTATE_INT32(transp, PXA2xxLCDState),
957 VMSTATE_UINT32_ARRAY(control, PXA2xxLCDState, 6),
958 VMSTATE_UINT32_ARRAY(status, PXA2xxLCDState, 2),
959 VMSTATE_UINT32_ARRAY(ovl1c, PXA2xxLCDState, 2),
960 VMSTATE_UINT32_ARRAY(ovl2c, PXA2xxLCDState, 2),
961 VMSTATE_UINT32(ccr, PXA2xxLCDState),
962 VMSTATE_UINT32(cmdcr, PXA2xxLCDState),
963 VMSTATE_UINT32(trgbr, PXA2xxLCDState),
964 VMSTATE_UINT32(tcr, PXA2xxLCDState),
965 VMSTATE_UINT32(liidr, PXA2xxLCDState),
966 VMSTATE_UINT8(bscntr, PXA2xxLCDState),
967 VMSTATE_STRUCT_ARRAY(dma_ch, PXA2xxLCDState, 7, 0,
968 vmstate_dma_channel, struct DMAChannel),
969 VMSTATE_END_OF_LIST()
970 }
971 };
972
973 #define BITS 8
974 #include "pxa2xx_template.h"
975 #define BITS 15
976 #include "pxa2xx_template.h"
977 #define BITS 16
978 #include "pxa2xx_template.h"
979 #define BITS 24
980 #include "pxa2xx_template.h"
981 #define BITS 32
982 #include "pxa2xx_template.h"
983
984 PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
985 target_phys_addr_t base, qemu_irq irq)
986 {
987 PXA2xxLCDState *s;
988
989 s = (PXA2xxLCDState *) g_malloc0(sizeof(PXA2xxLCDState));
990 s->invalidated = 1;
991 s->irq = irq;
992 s->sysmem = sysmem;
993
994 pxa2xx_lcdc_orientation(s, graphic_rotate);
995
996 memory_region_init_io(&s->iomem, &pxa2xx_lcdc_ops, s,
997 "pxa2xx-lcd-controller", 0x00100000);
998 memory_region_add_subregion(sysmem, base, &s->iomem);
999
1000 s->ds = graphic_console_init(pxa2xx_update_display,
1001 pxa2xx_invalidate_display,
1002 pxa2xx_screen_dump, NULL, s);
1003
1004 switch (ds_get_bits_per_pixel(s->ds)) {
1005 case 0:
1006 s->dest_width = 0;
1007 break;
1008 case 8:
1009 s->line_fn[0] = pxa2xx_draw_fn_8;
1010 s->line_fn[1] = pxa2xx_draw_fn_8t;
1011 s->dest_width = 1;
1012 break;
1013 case 15:
1014 s->line_fn[0] = pxa2xx_draw_fn_15;
1015 s->line_fn[1] = pxa2xx_draw_fn_15t;
1016 s->dest_width = 2;
1017 break;
1018 case 16:
1019 s->line_fn[0] = pxa2xx_draw_fn_16;
1020 s->line_fn[1] = pxa2xx_draw_fn_16t;
1021 s->dest_width = 2;
1022 break;
1023 case 24:
1024 s->line_fn[0] = pxa2xx_draw_fn_24;
1025 s->line_fn[1] = pxa2xx_draw_fn_24t;
1026 s->dest_width = 3;
1027 break;
1028 case 32:
1029 s->line_fn[0] = pxa2xx_draw_fn_32;
1030 s->line_fn[1] = pxa2xx_draw_fn_32t;
1031 s->dest_width = 4;
1032 break;
1033 default:
1034 fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
1035 exit(1);
1036 }
1037
1038 vmstate_register(NULL, 0, &vmstate_pxa2xx_lcdc, s);
1039
1040 return s;
1041 }
1042
1043 void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler)
1044 {
1045 s->vsync_cb = handler;
1046 }
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