2 * ARM Integrator CP System emulation.
4 * Copyright (c) 2005-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL
11 #include "primecell.h"
16 #include "exec-memory.h"
37 static uint8_t integrator_spd
[128] = {
38 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
39 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
42 static uint64_t integratorcm_read(void *opaque
, target_phys_addr_t offset
,
45 integratorcm_state
*s
= (integratorcm_state
*)opaque
;
46 if (offset
>= 0x100 && offset
< 0x200) {
50 return integrator_spd
[offset
>> 2];
52 switch (offset
>> 2) {
64 if (s
->cm_lock
== 0xa05f) {
69 case 6: /* CM_LMBUSCNT */
70 /* ??? High frequency timer. */
71 hw_error("integratorcm_read: CM_LMBUSCNT");
72 case 7: /* CM_AUXOSC */
74 case 8: /* CM_SDRAM */
78 case 10: /* CM_REFCT */
79 /* ??? High frequency timer. */
80 hw_error("integratorcm_read: CM_REFCT");
81 case 12: /* CM_FLAGS */
83 case 14: /* CM_NVFLAGS */
85 case 16: /* CM_IRQ_STAT */
86 return s
->int_level
& s
->irq_enabled
;
87 case 17: /* CM_IRQ_RSTAT */
89 case 18: /* CM_IRQ_ENSET */
90 return s
->irq_enabled
;
91 case 20: /* CM_SOFT_INTSET */
92 return s
->int_level
& 1;
93 case 24: /* CM_FIQ_STAT */
94 return s
->int_level
& s
->fiq_enabled
;
95 case 25: /* CM_FIQ_RSTAT */
97 case 26: /* CM_FIQ_ENSET */
98 return s
->fiq_enabled
;
99 case 32: /* CM_VOLTAGE_CTL0 */
100 case 33: /* CM_VOLTAGE_CTL1 */
101 case 34: /* CM_VOLTAGE_CTL2 */
102 case 35: /* CM_VOLTAGE_CTL3 */
103 /* ??? Voltage control unimplemented. */
106 hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
112 static void integratorcm_do_remap(integratorcm_state
*s
)
114 /* Sync memory region state with CM_CTRL REMAP bit:
115 * bit 0 => flash at address 0; bit 1 => RAM
117 memory_region_set_enabled(&s
->flash
, !(s
->cm_ctrl
& 4));
120 static void integratorcm_set_ctrl(integratorcm_state
*s
, uint32_t value
)
123 qemu_system_reset_request();
125 if ((s
->cm_ctrl
^ value
) & 1) {
126 /* (value & 1) != 0 means the green "MISC LED" is lit.
127 * We don't have any nice place to display LEDs. printf is a bad
128 * idea because Linux uses the LED as a heartbeat and the output
129 * will swamp anything else on the terminal.
132 /* Note that the RESET bit [3] always reads as zero */
133 s
->cm_ctrl
= (s
->cm_ctrl
& ~5) | (value
& 5);
134 integratorcm_do_remap(s
);
137 static void integratorcm_update(integratorcm_state
*s
)
139 /* ??? The CPU irq/fiq is raised when either the core module or base PIC
141 if (s
->int_level
& (s
->irq_enabled
| s
->fiq_enabled
))
142 hw_error("Core module interrupt\n");
145 static void integratorcm_write(void *opaque
, target_phys_addr_t offset
,
146 uint64_t value
, unsigned size
)
148 integratorcm_state
*s
= (integratorcm_state
*)opaque
;
149 switch (offset
>> 2) {
151 if (s
->cm_lock
== 0xa05f)
154 case 3: /* CM_CTRL */
155 integratorcm_set_ctrl(s
, value
);
157 case 5: /* CM_LOCK */
158 s
->cm_lock
= value
& 0xffff;
160 case 7: /* CM_AUXOSC */
161 if (s
->cm_lock
== 0xa05f)
162 s
->cm_auxosc
= value
;
164 case 8: /* CM_SDRAM */
167 case 9: /* CM_INIT */
168 /* ??? This can change the memory bus frequency. */
171 case 12: /* CM_FLAGSS */
172 s
->cm_flags
|= value
;
174 case 13: /* CM_FLAGSC */
175 s
->cm_flags
&= ~value
;
177 case 14: /* CM_NVFLAGSS */
178 s
->cm_nvflags
|= value
;
180 case 15: /* CM_NVFLAGSS */
181 s
->cm_nvflags
&= ~value
;
183 case 18: /* CM_IRQ_ENSET */
184 s
->irq_enabled
|= value
;
185 integratorcm_update(s
);
187 case 19: /* CM_IRQ_ENCLR */
188 s
->irq_enabled
&= ~value
;
189 integratorcm_update(s
);
191 case 20: /* CM_SOFT_INTSET */
192 s
->int_level
|= (value
& 1);
193 integratorcm_update(s
);
195 case 21: /* CM_SOFT_INTCLR */
196 s
->int_level
&= ~(value
& 1);
197 integratorcm_update(s
);
199 case 26: /* CM_FIQ_ENSET */
200 s
->fiq_enabled
|= value
;
201 integratorcm_update(s
);
203 case 27: /* CM_FIQ_ENCLR */
204 s
->fiq_enabled
&= ~value
;
205 integratorcm_update(s
);
207 case 32: /* CM_VOLTAGE_CTL0 */
208 case 33: /* CM_VOLTAGE_CTL1 */
209 case 34: /* CM_VOLTAGE_CTL2 */
210 case 35: /* CM_VOLTAGE_CTL3 */
211 /* ??? Voltage control unimplemented. */
214 hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
220 /* Integrator/CM control registers. */
222 static const MemoryRegionOps integratorcm_ops
= {
223 .read
= integratorcm_read
,
224 .write
= integratorcm_write
,
225 .endianness
= DEVICE_NATIVE_ENDIAN
,
228 static int integratorcm_init(SysBusDevice
*dev
)
230 integratorcm_state
*s
= FROM_SYSBUS(integratorcm_state
, dev
);
232 s
->cm_osc
= 0x01000048;
233 /* ??? What should the high bits of this value be? */
234 s
->cm_auxosc
= 0x0007feff;
235 s
->cm_sdram
= 0x00011122;
236 if (s
->memsz
>= 256) {
237 integrator_spd
[31] = 64;
239 } else if (s
->memsz
>= 128) {
240 integrator_spd
[31] = 32;
242 } else if (s
->memsz
>= 64) {
243 integrator_spd
[31] = 16;
245 } else if (s
->memsz
>= 32) {
246 integrator_spd
[31] = 4;
249 integrator_spd
[31] = 2;
251 memcpy(integrator_spd
+ 73, "QEMU-MEMORY", 11);
252 s
->cm_init
= 0x00000112;
253 memory_region_init_ram(&s
->flash
, "integrator.flash", 0x100000);
254 vmstate_register_ram_global(&s
->flash
);
256 memory_region_init_io(&s
->iomem
, &integratorcm_ops
, s
,
257 "integratorcm", 0x00800000);
258 sysbus_init_mmio(dev
, &s
->iomem
);
260 integratorcm_do_remap(s
);
261 /* ??? Save/restore. */
265 /* Integrator/CP hardware emulation. */
266 /* Primary interrupt controller. */
268 typedef struct icp_pic_state
273 uint32_t irq_enabled
;
274 uint32_t fiq_enabled
;
279 static void icp_pic_update(icp_pic_state
*s
)
283 flags
= (s
->level
& s
->irq_enabled
);
284 qemu_set_irq(s
->parent_irq
, flags
!= 0);
285 flags
= (s
->level
& s
->fiq_enabled
);
286 qemu_set_irq(s
->parent_fiq
, flags
!= 0);
289 static void icp_pic_set_irq(void *opaque
, int irq
, int level
)
291 icp_pic_state
*s
= (icp_pic_state
*)opaque
;
293 s
->level
|= 1 << irq
;
295 s
->level
&= ~(1 << irq
);
299 static uint64_t icp_pic_read(void *opaque
, target_phys_addr_t offset
,
302 icp_pic_state
*s
= (icp_pic_state
*)opaque
;
304 switch (offset
>> 2) {
305 case 0: /* IRQ_STATUS */
306 return s
->level
& s
->irq_enabled
;
307 case 1: /* IRQ_RAWSTAT */
309 case 2: /* IRQ_ENABLESET */
310 return s
->irq_enabled
;
311 case 4: /* INT_SOFTSET */
313 case 8: /* FRQ_STATUS */
314 return s
->level
& s
->fiq_enabled
;
315 case 9: /* FRQ_RAWSTAT */
317 case 10: /* FRQ_ENABLESET */
318 return s
->fiq_enabled
;
319 case 3: /* IRQ_ENABLECLR */
320 case 5: /* INT_SOFTCLR */
321 case 11: /* FRQ_ENABLECLR */
323 printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset
);
328 static void icp_pic_write(void *opaque
, target_phys_addr_t offset
,
329 uint64_t value
, unsigned size
)
331 icp_pic_state
*s
= (icp_pic_state
*)opaque
;
333 switch (offset
>> 2) {
334 case 2: /* IRQ_ENABLESET */
335 s
->irq_enabled
|= value
;
337 case 3: /* IRQ_ENABLECLR */
338 s
->irq_enabled
&= ~value
;
340 case 4: /* INT_SOFTSET */
342 icp_pic_set_irq(s
, 0, 1);
344 case 5: /* INT_SOFTCLR */
346 icp_pic_set_irq(s
, 0, 0);
348 case 10: /* FRQ_ENABLESET */
349 s
->fiq_enabled
|= value
;
351 case 11: /* FRQ_ENABLECLR */
352 s
->fiq_enabled
&= ~value
;
354 case 0: /* IRQ_STATUS */
355 case 1: /* IRQ_RAWSTAT */
356 case 8: /* FRQ_STATUS */
357 case 9: /* FRQ_RAWSTAT */
359 printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset
);
365 static const MemoryRegionOps icp_pic_ops
= {
366 .read
= icp_pic_read
,
367 .write
= icp_pic_write
,
368 .endianness
= DEVICE_NATIVE_ENDIAN
,
371 static int icp_pic_init(SysBusDevice
*dev
)
373 icp_pic_state
*s
= FROM_SYSBUS(icp_pic_state
, dev
);
375 qdev_init_gpio_in(&dev
->qdev
, icp_pic_set_irq
, 32);
376 sysbus_init_irq(dev
, &s
->parent_irq
);
377 sysbus_init_irq(dev
, &s
->parent_fiq
);
378 memory_region_init_io(&s
->iomem
, &icp_pic_ops
, s
, "icp-pic", 0x00800000);
379 sysbus_init_mmio(dev
, &s
->iomem
);
383 /* CP control registers. */
385 static uint64_t icp_control_read(void *opaque
, target_phys_addr_t offset
,
388 switch (offset
>> 2) {
389 case 0: /* CP_IDFIELD */
391 case 1: /* CP_FLASHPROG */
393 case 2: /* CP_INTREG */
395 case 3: /* CP_DECODE */
398 hw_error("icp_control_read: Bad offset %x\n", (int)offset
);
403 static void icp_control_write(void *opaque
, target_phys_addr_t offset
,
404 uint64_t value
, unsigned size
)
406 switch (offset
>> 2) {
407 case 1: /* CP_FLASHPROG */
408 case 2: /* CP_INTREG */
409 case 3: /* CP_DECODE */
410 /* Nothing interesting implemented yet. */
413 hw_error("icp_control_write: Bad offset %x\n", (int)offset
);
417 static const MemoryRegionOps icp_control_ops
= {
418 .read
= icp_control_read
,
419 .write
= icp_control_write
,
420 .endianness
= DEVICE_NATIVE_ENDIAN
,
423 static void icp_control_init(target_phys_addr_t base
)
427 io
= (MemoryRegion
*)g_malloc0(sizeof(MemoryRegion
));
428 memory_region_init_io(io
, &icp_control_ops
, NULL
,
429 "control", 0x00800000);
430 memory_region_add_subregion(get_system_memory(), base
, io
);
431 /* ??? Save/restore. */
437 static struct arm_boot_info integrator_binfo
= {
442 static void integratorcp_init(ram_addr_t ram_size
,
443 const char *boot_device
,
444 const char *kernel_filename
, const char *kernel_cmdline
,
445 const char *initrd_filename
, const char *cpu_model
)
448 MemoryRegion
*address_space_mem
= get_system_memory();
449 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
450 MemoryRegion
*ram_alias
= g_new(MemoryRegion
, 1);
457 cpu_model
= "arm926";
458 env
= cpu_init(cpu_model
);
460 fprintf(stderr
, "Unable to find CPU definition\n");
463 memory_region_init_ram(ram
, "integrator.ram", ram_size
);
464 vmstate_register_ram_global(ram
);
465 /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
466 /* ??? RAM should repeat to fill physical memory space. */
467 /* SDRAM at address zero*/
468 memory_region_add_subregion(address_space_mem
, 0, ram
);
469 /* And again at address 0x80000000 */
470 memory_region_init_alias(ram_alias
, "ram.alias", ram
, 0, ram_size
);
471 memory_region_add_subregion(address_space_mem
, 0x80000000, ram_alias
);
473 dev
= qdev_create(NULL
, "integrator_core");
474 qdev_prop_set_uint32(dev
, "memsz", ram_size
>> 20);
475 qdev_init_nofail(dev
);
476 sysbus_mmio_map((SysBusDevice
*)dev
, 0, 0x10000000);
478 cpu_pic
= arm_pic_init_cpu(env
);
479 dev
= sysbus_create_varargs("integrator_pic", 0x14000000,
480 cpu_pic
[ARM_PIC_CPU_IRQ
],
481 cpu_pic
[ARM_PIC_CPU_FIQ
], NULL
);
482 for (i
= 0; i
< 32; i
++) {
483 pic
[i
] = qdev_get_gpio_in(dev
, i
);
485 sysbus_create_simple("integrator_pic", 0xca000000, pic
[26]);
486 sysbus_create_varargs("integrator_pit", 0x13000000,
487 pic
[5], pic
[6], pic
[7], NULL
);
488 sysbus_create_simple("pl031", 0x15000000, pic
[8]);
489 sysbus_create_simple("pl011", 0x16000000, pic
[1]);
490 sysbus_create_simple("pl011", 0x17000000, pic
[2]);
491 icp_control_init(0xcb000000);
492 sysbus_create_simple("pl050_keyboard", 0x18000000, pic
[3]);
493 sysbus_create_simple("pl050_mouse", 0x19000000, pic
[4]);
494 sysbus_create_varargs("pl181", 0x1c000000, pic
[23], pic
[24], NULL
);
495 if (nd_table
[0].vlan
)
496 smc91c111_init(&nd_table
[0], 0xc8000000, pic
[27]);
498 sysbus_create_simple("pl110", 0xc0000000, pic
[22]);
500 integrator_binfo
.ram_size
= ram_size
;
501 integrator_binfo
.kernel_filename
= kernel_filename
;
502 integrator_binfo
.kernel_cmdline
= kernel_cmdline
;
503 integrator_binfo
.initrd_filename
= initrd_filename
;
504 arm_load_kernel(env
, &integrator_binfo
);
507 static QEMUMachine integratorcp_machine
= {
508 .name
= "integratorcp",
509 .desc
= "ARM Integrator/CP (ARM926EJ-S)",
510 .init
= integratorcp_init
,
514 static void integratorcp_machine_init(void)
516 qemu_register_machine(&integratorcp_machine
);
519 machine_init(integratorcp_machine_init
);
521 static Property core_properties
[] = {
522 DEFINE_PROP_UINT32("memsz", integratorcm_state
, memsz
, 0),
523 DEFINE_PROP_END_OF_LIST(),
526 static void core_class_init(ObjectClass
*klass
, void *data
)
528 DeviceClass
*dc
= DEVICE_CLASS(klass
);
529 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
531 k
->init
= integratorcm_init
;
532 dc
->props
= core_properties
;
535 static TypeInfo core_info
= {
536 .name
= "integrator_core",
537 .parent
= TYPE_SYS_BUS_DEVICE
,
538 .instance_size
= sizeof(integratorcm_state
),
539 .class_init
= core_class_init
,
542 static void icp_pic_class_init(ObjectClass
*klass
, void *data
)
544 SysBusDeviceClass
*sdc
= SYS_BUS_DEVICE_CLASS(klass
);
546 sdc
->init
= icp_pic_init
;
549 static TypeInfo icp_pic_info
= {
550 .name
= "integrator_pic",
551 .parent
= TYPE_SYS_BUS_DEVICE
,
552 .instance_size
= sizeof(icp_pic_state
),
553 .class_init
= icp_pic_class_init
,
556 static void integratorcp_register_types(void)
558 type_register_static(&icp_pic_info
);
559 type_register_static(&core_info
);
562 type_init(integratorcp_register_types
)