4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 #include "pci_bridge.h"
26 #include "pci_internals.h"
27 #include "pcie_regs.h"
31 # define PCIE_DPRINTF(fmt, ...) \
32 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
34 # define PCIE_DPRINTF(fmt, ...) do {} while (0)
36 #define PCIE_DEV_PRINTF(dev, fmt, ...) \
37 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
39 /* From 6.2.7 Error Listing and Rules. Table 6-2, 6-3 and 6-4 */
40 static uint32_t pcie_aer_uncor_default_severity(uint32_t status
)
43 case PCI_ERR_UNC_INTN
:
46 case PCI_ERR_UNC_RX_OVER
:
48 case PCI_ERR_UNC_MALF_TLP
:
49 return PCI_ERR_ROOT_CMD_FATAL_EN
;
50 case PCI_ERR_UNC_POISON_TLP
:
51 case PCI_ERR_UNC_ECRC
:
52 case PCI_ERR_UNC_UNSUP
:
53 case PCI_ERR_UNC_COMP_TIME
:
54 case PCI_ERR_UNC_COMP_ABORT
:
55 case PCI_ERR_UNC_UNX_COMP
:
56 case PCI_ERR_UNC_ACSV
:
57 case PCI_ERR_UNC_MCBTLP
:
58 case PCI_ERR_UNC_ATOP_EBLOCKED
:
59 case PCI_ERR_UNC_TLP_PRF_BLOCKED
:
60 return PCI_ERR_ROOT_CMD_NONFATAL_EN
;
65 return PCI_ERR_ROOT_CMD_FATAL_EN
;
68 static int aer_log_add_err(PCIEAERLog
*aer_log
, const PCIEAERErr
*err
)
70 if (aer_log
->log_num
== aer_log
->log_max
) {
73 memcpy(&aer_log
->log
[aer_log
->log_num
], err
, sizeof *err
);
78 static void aer_log_del_err(PCIEAERLog
*aer_log
, PCIEAERErr
*err
)
80 assert(aer_log
->log_num
);
81 *err
= aer_log
->log
[0];
83 memmove(&aer_log
->log
[0], &aer_log
->log
[1],
84 aer_log
->log_num
* sizeof *err
);
87 static void aer_log_clear_all_err(PCIEAERLog
*aer_log
)
92 int pcie_aer_init(PCIDevice
*dev
, uint16_t offset
)
94 PCIExpressDevice
*exp
;
96 pcie_add_capability(dev
, PCI_EXT_CAP_ID_ERR
, PCI_ERR_VER
,
97 offset
, PCI_ERR_SIZEOF
);
99 exp
->aer_cap
= offset
;
101 /* log_max is property */
102 if (dev
->exp
.aer_log
.log_max
== PCIE_AER_LOG_MAX_UNSET
) {
103 dev
->exp
.aer_log
.log_max
= PCIE_AER_LOG_MAX_DEFAULT
;
105 /* clip down the value to avoid unreasobale memory usage */
106 if (dev
->exp
.aer_log
.log_max
> PCIE_AER_LOG_MAX_LIMIT
) {
109 dev
->exp
.aer_log
.log
= qemu_mallocz(sizeof dev
->exp
.aer_log
.log
[0] *
110 dev
->exp
.aer_log
.log_max
);
112 pci_set_long(dev
->w1cmask
+ offset
+ PCI_ERR_UNCOR_STATUS
,
113 PCI_ERR_UNC_SUPPORTED
);
115 pci_set_long(dev
->config
+ offset
+ PCI_ERR_UNCOR_SEVER
,
116 PCI_ERR_UNC_SEVERITY_DEFAULT
);
117 pci_set_long(dev
->wmask
+ offset
+ PCI_ERR_UNCOR_SEVER
,
118 PCI_ERR_UNC_SUPPORTED
);
120 pci_long_test_and_set_mask(dev
->w1cmask
+ offset
+ PCI_ERR_COR_STATUS
,
123 pci_set_long(dev
->config
+ offset
+ PCI_ERR_COR_MASK
,
124 PCI_ERR_COR_MASK_DEFAULT
);
125 pci_set_long(dev
->wmask
+ offset
+ PCI_ERR_COR_MASK
,
126 PCI_ERR_COR_SUPPORTED
);
128 /* capabilities and control. multiple header logging is supported */
129 if (dev
->exp
.aer_log
.log_max
> 0) {
130 pci_set_long(dev
->config
+ offset
+ PCI_ERR_CAP
,
131 PCI_ERR_CAP_ECRC_GENC
| PCI_ERR_CAP_ECRC_CHKC
|
133 pci_set_long(dev
->wmask
+ offset
+ PCI_ERR_CAP
,
134 PCI_ERR_CAP_ECRC_GENE
| PCI_ERR_CAP_ECRC_CHKE
|
137 pci_set_long(dev
->config
+ offset
+ PCI_ERR_CAP
,
138 PCI_ERR_CAP_ECRC_GENC
| PCI_ERR_CAP_ECRC_CHKC
);
139 pci_set_long(dev
->wmask
+ offset
+ PCI_ERR_CAP
,
140 PCI_ERR_CAP_ECRC_GENE
| PCI_ERR_CAP_ECRC_CHKE
);
143 switch (pcie_cap_get_type(dev
)) {
144 case PCI_EXP_TYPE_ROOT_PORT
:
145 /* this case will be set by pcie_aer_root_init() */
147 case PCI_EXP_TYPE_DOWNSTREAM
:
148 case PCI_EXP_TYPE_UPSTREAM
:
149 pci_word_test_and_set_mask(dev
->wmask
+ PCI_BRIDGE_CONTROL
,
150 PCI_BRIDGE_CTL_SERR
);
151 pci_long_test_and_set_mask(dev
->w1cmask
+ PCI_STATUS
,
152 PCI_SEC_STATUS_RCV_SYSTEM_ERROR
);
161 void pcie_aer_exit(PCIDevice
*dev
)
163 qemu_free(dev
->exp
.aer_log
.log
);
166 static void pcie_aer_update_uncor_status(PCIDevice
*dev
)
168 uint8_t *aer_cap
= dev
->config
+ dev
->exp
.aer_cap
;
169 PCIEAERLog
*aer_log
= &dev
->exp
.aer_log
;
172 for (i
= 0; i
< aer_log
->log_num
; i
++) {
173 pci_long_test_and_set_mask(aer_cap
+ PCI_ERR_UNCOR_STATUS
,
174 dev
->exp
.aer_log
.log
[i
].status
);
180 * true: error message needs to be sent up
181 * false: error message is masked
183 * 6.2.6 Error Message Control
185 * all pci express devices part
188 pcie_aer_msg_alldev(PCIDevice
*dev
, const PCIEAERMsg
*msg
)
190 if (!(pcie_aer_msg_is_uncor(msg
) &&
191 (pci_get_word(dev
->config
+ PCI_COMMAND
) & PCI_COMMAND_SERR
))) {
195 /* Signaled System Error
197 * 7.5.1.1 Command register
200 * When Set, this bit enables reporting of Non-fatal and Fatal
201 * errors detected by the Function to the Root Complex. Note that
202 * errors are reported if enabled either through this bit or through
203 * the PCI Express specific bits in the Device Control register (see
206 pci_word_test_and_set_mask(dev
->config
+ PCI_STATUS
,
207 PCI_STATUS_SIG_SYSTEM_ERROR
);
209 if (!(msg
->severity
&
210 pci_get_word(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL
))) {
214 /* send up error message */
220 * true: error message is sent up
221 * false: error message is masked
223 * 6.2.6 Error Message Control
225 * virtual pci bridge part
227 static bool pcie_aer_msg_vbridge(PCIDevice
*dev
, const PCIEAERMsg
*msg
)
229 uint16_t bridge_control
= pci_get_word(dev
->config
+ PCI_BRIDGE_CONTROL
);
231 if (pcie_aer_msg_is_uncor(msg
)) {
232 /* Received System Error */
233 pci_word_test_and_set_mask(dev
->config
+ PCI_SEC_STATUS
,
234 PCI_SEC_STATUS_RCV_SYSTEM_ERROR
);
237 if (!(bridge_control
& PCI_BRIDGE_CTL_SERR
)) {
243 void pcie_aer_root_set_vector(PCIDevice
*dev
, unsigned int vector
)
245 uint8_t *aer_cap
= dev
->config
+ dev
->exp
.aer_cap
;
246 assert(vector
< PCI_ERR_ROOT_IRQ_MAX
);
247 pci_long_test_and_clear_mask(aer_cap
+ PCI_ERR_ROOT_STATUS
,
249 pci_long_test_and_set_mask(aer_cap
+ PCI_ERR_ROOT_STATUS
,
250 vector
<< PCI_ERR_ROOT_IRQ_SHIFT
);
253 static unsigned int pcie_aer_root_get_vector(PCIDevice
*dev
)
255 uint8_t *aer_cap
= dev
->config
+ dev
->exp
.aer_cap
;
256 uint32_t root_status
= pci_get_long(aer_cap
+ PCI_ERR_ROOT_STATUS
);
257 return (root_status
& PCI_ERR_ROOT_IRQ
) >> PCI_ERR_ROOT_IRQ_SHIFT
;
262 * true: error message is sent up
263 * false: error message is masked
265 * 6.2.6 Error Message Control
269 static bool pcie_aer_msg_root_port(PCIDevice
*dev
, const PCIEAERMsg
*msg
)
275 uint32_t root_status
;
279 cmd
= pci_get_word(dev
->config
+ PCI_COMMAND
);
280 aer_cap
= dev
->config
+ dev
->exp
.aer_cap
;
281 root_cmd
= pci_get_long(aer_cap
+ PCI_ERR_ROOT_COMMAND
);
282 root_status
= pci_get_long(aer_cap
+ PCI_ERR_ROOT_STATUS
);
285 if (cmd
& PCI_COMMAND_SERR
) {
288 * The way to report System Error is platform specific and
289 * it isn't implemented in qemu right now.
290 * So just discard the error for now.
291 * OS which cares of aer would receive errors via
292 * native aer mechanims, so this wouldn't matter.
296 /* Errro Message Received: Root Error Status register */
297 switch (msg
->severity
) {
298 case PCI_ERR_ROOT_CMD_COR_EN
:
299 if (root_status
& PCI_ERR_ROOT_COR_RCV
) {
300 root_status
|= PCI_ERR_ROOT_MULTI_COR_RCV
;
302 if (root_cmd
& PCI_ERR_ROOT_CMD_COR_EN
) {
305 pci_set_word(aer_cap
+ PCI_ERR_ROOT_COR_SRC
, msg
->source_id
);
307 root_status
|= PCI_ERR_ROOT_COR_RCV
;
309 case PCI_ERR_ROOT_CMD_NONFATAL_EN
:
310 if (!(root_status
& PCI_ERR_ROOT_NONFATAL_RCV
) &&
311 root_cmd
& PCI_ERR_ROOT_CMD_NONFATAL_EN
) {
314 root_status
|= PCI_ERR_ROOT_NONFATAL_RCV
;
316 case PCI_ERR_ROOT_CMD_FATAL_EN
:
317 if (!(root_status
& PCI_ERR_ROOT_FATAL_RCV
) &&
318 root_cmd
& PCI_ERR_ROOT_CMD_FATAL_EN
) {
321 if (!(root_status
& PCI_ERR_ROOT_UNCOR_RCV
)) {
322 root_status
|= PCI_ERR_ROOT_FIRST_FATAL
;
324 root_status
|= PCI_ERR_ROOT_FATAL_RCV
;
330 if (pcie_aer_msg_is_uncor(msg
)) {
331 if (root_status
& PCI_ERR_ROOT_UNCOR_RCV
) {
332 root_status
|= PCI_ERR_ROOT_MULTI_UNCOR_RCV
;
334 pci_set_word(aer_cap
+ PCI_ERR_ROOT_SRC
, msg
->source_id
);
336 root_status
|= PCI_ERR_ROOT_UNCOR_RCV
;
338 pci_set_long(aer_cap
+ PCI_ERR_ROOT_STATUS
, root_status
);
340 if (root_cmd
& msg
->severity
) {
341 /* 6.2.4.1.2 Interrupt Generation */
342 if (pci_msi_enabled(dev
)) {
344 pci_msi_notify(dev
, pcie_aer_root_get_vector(dev
));
347 qemu_set_irq(dev
->irq
[dev
->exp
.aer_intx
], 1);
355 * 6.2.6 Error Message Control Figure 6-3
357 * Walk up the bus tree from the device, propagate the error message.
359 static void pcie_aer_msg(PCIDevice
*dev
, const PCIEAERMsg
*msg
)
364 if (!pci_is_express(dev
)) {
366 /* TODO: Shouldn't we set PCI_STATUS_SIG_SYSTEM_ERROR?
367 * Consider e.g. a PCI bridge above a PCI Express device. */
371 type
= pcie_cap_get_type(dev
);
372 if ((type
== PCI_EXP_TYPE_ROOT_PORT
||
373 type
== PCI_EXP_TYPE_UPSTREAM
||
374 type
== PCI_EXP_TYPE_DOWNSTREAM
) &&
375 !pcie_aer_msg_vbridge(dev
, msg
)) {
378 if (!pcie_aer_msg_alldev(dev
, msg
)) {
381 if (type
== PCI_EXP_TYPE_ROOT_PORT
) {
382 pcie_aer_msg_root_port(dev
, msg
);
383 /* Root port can notify system itself,
384 or send the error message to root complex event collector. */
386 * if root port is associated with an event collector,
387 * return the root complex event collector here.
388 * For now root complex event collector isn't supported.
392 dev
= pci_bridge_get_device(dev
->bus
);
396 static void pcie_aer_update_log(PCIDevice
*dev
, const PCIEAERErr
*err
)
398 uint8_t *aer_cap
= dev
->config
+ dev
->exp
.aer_cap
;
399 uint8_t first_bit
= ffs(err
->status
) - 1;
400 uint32_t errcap
= pci_get_long(aer_cap
+ PCI_ERR_CAP
);
404 assert(err
->status
& (err
->status
- 1));
406 errcap
&= ~(PCI_ERR_CAP_FEP_MASK
| PCI_ERR_CAP_TLP
);
407 errcap
|= PCI_ERR_CAP_FEP(first_bit
);
409 if (err
->flags
& PCIE_AER_ERR_HEADER_VALID
) {
410 for (i
= 0; i
< ARRAY_SIZE(err
->header
); ++i
) {
411 /* 7.10.8 Header Log Register */
412 uint8_t *header_log
=
413 aer_cap
+ PCI_ERR_HEADER_LOG
+ i
* sizeof err
->header
[0];
414 cpu_to_be32wu((uint32_t*)header_log
, err
->header
[i
]);
417 assert(!(err
->flags
& PCIE_AER_ERR_TLP_PREFIX_PRESENT
));
418 memset(aer_cap
+ PCI_ERR_HEADER_LOG
, 0, PCI_ERR_HEADER_LOG_SIZE
);
421 if ((err
->flags
& PCIE_AER_ERR_TLP_PREFIX_PRESENT
) &&
422 (pci_get_long(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL2
) &
423 PCI_EXP_DEVCAP2_EETLPP
)) {
424 for (i
= 0; i
< ARRAY_SIZE(err
->prefix
); ++i
) {
425 /* 7.10.12 tlp prefix log register */
426 uint8_t *prefix_log
=
427 aer_cap
+ PCI_ERR_TLP_PREFIX_LOG
+ i
* sizeof err
->prefix
[0];
428 cpu_to_be32wu((uint32_t*)prefix_log
, err
->prefix
[i
]);
430 errcap
|= PCI_ERR_CAP_TLP
;
432 memset(aer_cap
+ PCI_ERR_TLP_PREFIX_LOG
, 0,
433 PCI_ERR_TLP_PREFIX_LOG_SIZE
);
435 pci_set_long(aer_cap
+ PCI_ERR_CAP
, errcap
);
438 static void pcie_aer_clear_log(PCIDevice
*dev
)
440 uint8_t *aer_cap
= dev
->config
+ dev
->exp
.aer_cap
;
442 pci_long_test_and_clear_mask(aer_cap
+ PCI_ERR_CAP
,
443 PCI_ERR_CAP_FEP_MASK
| PCI_ERR_CAP_TLP
);
445 memset(aer_cap
+ PCI_ERR_HEADER_LOG
, 0, PCI_ERR_HEADER_LOG_SIZE
);
446 memset(aer_cap
+ PCI_ERR_TLP_PREFIX_LOG
, 0, PCI_ERR_TLP_PREFIX_LOG_SIZE
);
449 static void pcie_aer_clear_error(PCIDevice
*dev
)
451 uint8_t *aer_cap
= dev
->config
+ dev
->exp
.aer_cap
;
452 uint32_t errcap
= pci_get_long(aer_cap
+ PCI_ERR_CAP
);
453 PCIEAERLog
*aer_log
= &dev
->exp
.aer_log
;
456 if (!(errcap
& PCI_ERR_CAP_MHRE
) || !aer_log
->log_num
) {
457 pcie_aer_clear_log(dev
);
462 * If more errors are queued, set corresponding bits in uncorrectable
464 * We emulate uncorrectable error status register as W1CS.
465 * So set bit in uncorrectable error status here again for multiple
466 * error recording support.
468 * 6.2.4.2 Multiple Error Handling(Advanced Error Reporting Capability)
470 pcie_aer_update_uncor_status(dev
);
472 aer_log_del_err(aer_log
, &err
);
473 pcie_aer_update_log(dev
, &err
);
476 static int pcie_aer_record_error(PCIDevice
*dev
,
477 const PCIEAERErr
*err
)
479 uint8_t *aer_cap
= dev
->config
+ dev
->exp
.aer_cap
;
480 uint32_t errcap
= pci_get_long(aer_cap
+ PCI_ERR_CAP
);
481 int fep
= PCI_ERR_CAP_FEP(errcap
);
484 assert(err
->status
& (err
->status
- 1));
486 if (errcap
& PCI_ERR_CAP_MHRE
&&
487 (pci_get_long(aer_cap
+ PCI_ERR_UNCOR_STATUS
) & (1U << fep
))) {
488 /* Not first error. queue error */
489 if (aer_log_add_err(&dev
->exp
.aer_log
, err
) < 0) {
496 pcie_aer_update_log(dev
, err
);
500 typedef struct PCIEAERInject
{
503 const PCIEAERErr
*err
;
506 uint32_t error_status
;
507 bool unsupported_request
;
512 static bool pcie_aer_inject_cor_error(PCIEAERInject
*inj
,
513 uint32_t uncor_status
,
514 bool is_advisory_nonfatal
)
516 PCIDevice
*dev
= inj
->dev
;
518 inj
->devsta
|= PCI_EXP_DEVSTA_CED
;
519 if (inj
->unsupported_request
) {
520 inj
->devsta
|= PCI_EXP_DEVSTA_URD
;
522 pci_set_word(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVSTA
, inj
->devsta
);
526 pci_long_test_and_set_mask(inj
->aer_cap
+ PCI_ERR_COR_STATUS
,
528 mask
= pci_get_long(inj
->aer_cap
+ PCI_ERR_COR_MASK
);
529 if (mask
& inj
->error_status
) {
532 if (is_advisory_nonfatal
) {
533 uint32_t uncor_mask
=
534 pci_get_long(inj
->aer_cap
+ PCI_ERR_UNCOR_MASK
);
535 if (!(uncor_mask
& uncor_status
)) {
536 inj
->log_overflow
= !!pcie_aer_record_error(dev
, inj
->err
);
538 pci_long_test_and_set_mask(inj
->aer_cap
+ PCI_ERR_UNCOR_STATUS
,
543 if (inj
->unsupported_request
&& !(inj
->devctl
& PCI_EXP_DEVCTL_URRE
)) {
546 if (!(inj
->devctl
& PCI_EXP_DEVCTL_CERE
)) {
550 inj
->msg
.severity
= PCI_ERR_ROOT_CMD_COR_EN
;
554 static bool pcie_aer_inject_uncor_error(PCIEAERInject
*inj
, bool is_fatal
)
556 PCIDevice
*dev
= inj
->dev
;
560 inj
->devsta
|= PCI_EXP_DEVSTA_FED
;
562 inj
->devsta
|= PCI_EXP_DEVSTA_NFED
;
564 if (inj
->unsupported_request
) {
565 inj
->devsta
|= PCI_EXP_DEVSTA_URD
;
567 pci_set_long(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVSTA
, inj
->devsta
);
570 uint32_t mask
= pci_get_long(inj
->aer_cap
+ PCI_ERR_UNCOR_MASK
);
571 if (mask
& inj
->error_status
) {
572 pci_long_test_and_set_mask(inj
->aer_cap
+ PCI_ERR_UNCOR_STATUS
,
577 inj
->log_overflow
= !!pcie_aer_record_error(dev
, inj
->err
);
578 pci_long_test_and_set_mask(inj
->aer_cap
+ PCI_ERR_UNCOR_STATUS
,
582 cmd
= pci_get_word(dev
->config
+ PCI_COMMAND
);
583 if (inj
->unsupported_request
&&
584 !(inj
->devctl
& PCI_EXP_DEVCTL_URRE
) && !(cmd
& PCI_COMMAND_SERR
)) {
588 if (!((cmd
& PCI_COMMAND_SERR
) ||
589 (inj
->devctl
& PCI_EXP_DEVCTL_FERE
))) {
592 inj
->msg
.severity
= PCI_ERR_ROOT_CMD_FATAL_EN
;
594 if (!((cmd
& PCI_COMMAND_SERR
) ||
595 (inj
->devctl
& PCI_EXP_DEVCTL_NFERE
))) {
598 inj
->msg
.severity
= PCI_ERR_ROOT_CMD_NONFATAL_EN
;
604 * non-Function specific error must be recorded in all functions.
605 * It is the responsibility of the caller of this function.
606 * It is also caller's responsiblity to determine which function should
609 * 6.2.4 Error Logging
610 * 6.2.5 Sqeunce of Device Error Signaling and Logging Operations
611 * table 6-2: Flowchard Showing Sequence of Device Error Signaling and Logging
614 int pcie_aer_inject_error(PCIDevice
*dev
, const PCIEAERErr
*err
)
616 uint8_t *aer_cap
= NULL
;
619 uint32_t error_status
= err
->status
;
622 if (!pci_is_express(dev
)) {
626 if (err
->flags
& PCIE_AER_ERR_IS_CORRECTABLE
) {
627 error_status
&= PCI_ERR_COR_SUPPORTED
;
629 error_status
&= PCI_ERR_UNC_SUPPORTED
;
632 /* invalid status bit. one and only one bit must be set */
633 if (!error_status
|| (error_status
& (error_status
- 1))) {
637 if (dev
->exp
.aer_cap
) {
638 uint8_t *exp_cap
= dev
->config
+ dev
->exp
.exp_cap
;
639 aer_cap
= dev
->config
+ dev
->exp
.aer_cap
;
640 devctl
= pci_get_long(exp_cap
+ PCI_EXP_DEVCTL
);
641 devsta
= pci_get_long(exp_cap
+ PCI_EXP_DEVSTA
);
645 inj
.aer_cap
= aer_cap
;
649 inj
.error_status
= error_status
;
650 inj
.unsupported_request
= !(err
->flags
& PCIE_AER_ERR_IS_CORRECTABLE
) &&
651 err
->status
== PCI_ERR_UNC_UNSUP
;
652 inj
.log_overflow
= false;
654 if (err
->flags
& PCIE_AER_ERR_IS_CORRECTABLE
) {
655 if (!pcie_aer_inject_cor_error(&inj
, 0, false)) {
660 pcie_aer_uncor_default_severity(error_status
) ==
661 PCI_ERR_ROOT_CMD_FATAL_EN
;
664 error_status
& pci_get_long(aer_cap
+ PCI_ERR_UNCOR_SEVER
);
666 if (!is_fatal
&& (err
->flags
& PCIE_AER_ERR_MAYBE_ADVISORY
)) {
667 inj
.error_status
= PCI_ERR_COR_ADV_NONFATAL
;
668 if (!pcie_aer_inject_cor_error(&inj
, error_status
, true)) {
672 if (!pcie_aer_inject_uncor_error(&inj
, is_fatal
)) {
678 /* send up error message */
679 inj
.msg
.source_id
= err
->source_id
;
680 pcie_aer_msg(dev
, &inj
.msg
);
682 if (inj
.log_overflow
) {
683 PCIEAERErr header_log_overflow
= {
684 .status
= PCI_ERR_COR_HL_OVERFLOW
,
685 .flags
= PCIE_AER_ERR_IS_CORRECTABLE
,
687 int ret
= pcie_aer_inject_error(dev
, &header_log_overflow
);
693 void pcie_aer_write_config(PCIDevice
*dev
,
694 uint32_t addr
, uint32_t val
, int len
)
696 uint8_t *aer_cap
= dev
->config
+ dev
->exp
.aer_cap
;
697 uint32_t errcap
= pci_get_long(aer_cap
+ PCI_ERR_CAP
);
698 uint32_t first_error
= 1U << PCI_ERR_CAP_FEP(errcap
);
699 uint32_t uncorsta
= pci_get_long(aer_cap
+ PCI_ERR_UNCOR_STATUS
);
701 /* uncorrectable error */
702 if (!(uncorsta
& first_error
)) {
703 /* the bit that corresponds to the first error is cleared */
704 pcie_aer_clear_error(dev
);
705 } else if (errcap
& PCI_ERR_CAP_MHRE
) {
706 /* When PCI_ERR_CAP_MHRE is enabled and the first error isn't cleared
707 * nothing should happen. So we have to revert the modification to
710 pcie_aer_update_uncor_status(dev
);
712 /* capability & control
713 * PCI_ERR_CAP_MHRE might be cleared, so clear of header log.
715 aer_log_clear_all_err(&dev
->exp
.aer_log
);
719 void pcie_aer_root_init(PCIDevice
*dev
)
721 uint16_t pos
= dev
->exp
.aer_cap
;
723 pci_set_long(dev
->wmask
+ pos
+ PCI_ERR_ROOT_COMMAND
,
724 PCI_ERR_ROOT_CMD_EN_MASK
);
725 pci_set_long(dev
->w1cmask
+ pos
+ PCI_ERR_ROOT_STATUS
,
726 PCI_ERR_ROOT_STATUS_REPORT_MASK
);
729 void pcie_aer_root_reset(PCIDevice
*dev
)
731 uint8_t* aer_cap
= dev
->config
+ dev
->exp
.aer_cap
;
733 pci_set_long(aer_cap
+ PCI_ERR_ROOT_COMMAND
, 0);
736 * Advanced Error Interrupt Message Number in Root Error Status Register
737 * must be updated by chip dependent code because it's chip dependent
738 * which number is used.
742 static bool pcie_aer_root_does_trigger(uint32_t cmd
, uint32_t status
)
745 ((cmd
& PCI_ERR_ROOT_CMD_COR_EN
) && (status
& PCI_ERR_ROOT_COR_RCV
)) ||
746 ((cmd
& PCI_ERR_ROOT_CMD_NONFATAL_EN
) &&
747 (status
& PCI_ERR_ROOT_NONFATAL_RCV
)) ||
748 ((cmd
& PCI_ERR_ROOT_CMD_FATAL_EN
) &&
749 (status
& PCI_ERR_ROOT_FATAL_RCV
));
752 void pcie_aer_root_write_config(PCIDevice
*dev
,
753 uint32_t addr
, uint32_t val
, int len
,
754 uint32_t root_cmd_prev
)
756 uint8_t *aer_cap
= dev
->config
+ dev
->exp
.aer_cap
;
758 /* root command register */
759 uint32_t root_cmd
= pci_get_long(aer_cap
+ PCI_ERR_ROOT_COMMAND
);
760 if (root_cmd
& PCI_ERR_ROOT_CMD_EN_MASK
) {
761 /* 6.2.4.1.2 Interrupt Generation */
764 uint32_t root_cmd_set
= (root_cmd_prev
^ root_cmd
) & root_cmd
;
765 uint32_t root_status
= pci_get_long(aer_cap
+ PCI_ERR_ROOT_STATUS
);
767 if (pci_msi_enabled(dev
)) {
768 if (pcie_aer_root_does_trigger(root_cmd_set
, root_status
)) {
769 pci_msi_notify(dev
, pcie_aer_root_get_vector(dev
));
772 int int_level
= pcie_aer_root_does_trigger(root_cmd
, root_status
);
773 qemu_set_irq(dev
->irq
[dev
->exp
.aer_intx
], int_level
);
778 static const VMStateDescription vmstate_pcie_aer_err
= {
779 .name
= "PCIE_AER_ERROR",
781 .minimum_version_id
= 1,
782 .minimum_version_id_old
= 1,
783 .fields
= (VMStateField
[]) {
784 VMSTATE_UINT32(status
, PCIEAERErr
),
785 VMSTATE_UINT16(source_id
, PCIEAERErr
),
786 VMSTATE_UINT16(flags
, PCIEAERErr
),
787 VMSTATE_UINT32_ARRAY(header
, PCIEAERErr
, 4),
788 VMSTATE_UINT32_ARRAY(prefix
, PCIEAERErr
, 4),
789 VMSTATE_END_OF_LIST()
793 #define VMSTATE_PCIE_AER_ERRS(_field, _state, _field_num, _vmsd, _type) { \
794 .name = (stringify(_field)), \
796 .num_offset = vmstate_offset_value(_state, _field_num, uint16_t), \
797 .size = sizeof(_type), \
799 .flags = VMS_POINTER | VMS_VARRAY_UINT16 | VMS_STRUCT, \
800 .offset = vmstate_offset_pointer(_state, _field, _type), \
803 const VMStateDescription vmstate_pcie_aer_log
= {
804 .name
= "PCIE_AER_ERROR_LOG",
806 .minimum_version_id
= 1,
807 .minimum_version_id_old
= 1,
808 .fields
= (VMStateField
[]) {
809 VMSTATE_UINT16(log_num
, PCIEAERLog
),
810 VMSTATE_UINT16(log_max
, PCIEAERLog
),
811 VMSTATE_PCIE_AER_ERRS(log
, PCIEAERLog
, log_num
,
812 vmstate_pcie_aer_err
, PCIEAERErr
),
813 VMSTATE_END_OF_LIST()