2 * ARM Integrator CP System emulation.
4 * Copyright (c) 2005-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
13 #include "hw/sysbus.h"
14 #include "migration/vmstate.h"
15 #include "hw/boards.h"
16 #include "hw/arm/boot.h"
17 #include "hw/misc/arm_integrator_debug.h"
18 #include "hw/net/smc91c111.h"
20 #include "exec/address-spaces.h"
21 #include "sysemu/runstate.h"
22 #include "sysemu/sysemu.h"
24 #include "qemu/error-report.h"
25 #include "hw/char/pl011.h"
29 #include "qom/object.h"
30 #include "audio/audio.h"
32 #define TYPE_INTEGRATOR_CM "integrator_core"
33 OBJECT_DECLARE_SIMPLE_TYPE(IntegratorCMState
, INTEGRATOR_CM
)
35 struct IntegratorCMState
{
37 SysBusDevice parent_obj
;
51 uint32_t cm_refcnt_offset
;
57 static uint8_t integrator_spd
[128] = {
58 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
59 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
62 static const VMStateDescription vmstate_integratorcm
= {
63 .name
= "integratorcm",
65 .minimum_version_id
= 1,
66 .fields
= (VMStateField
[]) {
67 VMSTATE_UINT32(cm_osc
, IntegratorCMState
),
68 VMSTATE_UINT32(cm_ctrl
, IntegratorCMState
),
69 VMSTATE_UINT32(cm_lock
, IntegratorCMState
),
70 VMSTATE_UINT32(cm_auxosc
, IntegratorCMState
),
71 VMSTATE_UINT32(cm_sdram
, IntegratorCMState
),
72 VMSTATE_UINT32(cm_init
, IntegratorCMState
),
73 VMSTATE_UINT32(cm_flags
, IntegratorCMState
),
74 VMSTATE_UINT32(cm_nvflags
, IntegratorCMState
),
75 VMSTATE_UINT32(int_level
, IntegratorCMState
),
76 VMSTATE_UINT32(irq_enabled
, IntegratorCMState
),
77 VMSTATE_UINT32(fiq_enabled
, IntegratorCMState
),
82 static uint64_t integratorcm_read(void *opaque
, hwaddr offset
,
85 IntegratorCMState
*s
= opaque
;
86 if (offset
>= 0x100 && offset
< 0x200) {
90 return integrator_spd
[offset
>> 2];
92 switch (offset
>> 2) {
101 case 4: /* CM_STAT */
103 case 5: /* CM_LOCK */
104 if (s
->cm_lock
== 0xa05f) {
109 case 6: /* CM_LMBUSCNT */
110 /* ??? High frequency timer. */
111 hw_error("integratorcm_read: CM_LMBUSCNT");
112 case 7: /* CM_AUXOSC */
114 case 8: /* CM_SDRAM */
116 case 9: /* CM_INIT */
118 case 10: /* CM_REFCNT */
119 /* This register, CM_REFCNT, provides a 32-bit count value.
120 * The count increments at the fixed reference clock frequency of 24MHz
121 * and can be used as a real-time counter.
123 return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), 24,
124 1000) - s
->cm_refcnt_offset
;
125 case 12: /* CM_FLAGS */
127 case 14: /* CM_NVFLAGS */
128 return s
->cm_nvflags
;
129 case 16: /* CM_IRQ_STAT */
130 return s
->int_level
& s
->irq_enabled
;
131 case 17: /* CM_IRQ_RSTAT */
133 case 18: /* CM_IRQ_ENSET */
134 return s
->irq_enabled
;
135 case 20: /* CM_SOFT_INTSET */
136 return s
->int_level
& 1;
137 case 24: /* CM_FIQ_STAT */
138 return s
->int_level
& s
->fiq_enabled
;
139 case 25: /* CM_FIQ_RSTAT */
141 case 26: /* CM_FIQ_ENSET */
142 return s
->fiq_enabled
;
143 case 32: /* CM_VOLTAGE_CTL0 */
144 case 33: /* CM_VOLTAGE_CTL1 */
145 case 34: /* CM_VOLTAGE_CTL2 */
146 case 35: /* CM_VOLTAGE_CTL3 */
147 /* ??? Voltage control unimplemented. */
150 qemu_log_mask(LOG_UNIMP
,
151 "%s: Unimplemented offset 0x%" HWADDR_PRIX
"\n",
157 static void integratorcm_do_remap(IntegratorCMState
*s
)
159 /* Sync memory region state with CM_CTRL REMAP bit:
160 * bit 0 => flash at address 0; bit 1 => RAM
162 memory_region_set_enabled(&s
->flash
, !(s
->cm_ctrl
& 4));
165 static void integratorcm_set_ctrl(IntegratorCMState
*s
, uint32_t value
)
168 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
170 if ((s
->cm_ctrl
^ value
) & 1) {
171 /* (value & 1) != 0 means the green "MISC LED" is lit.
172 * We don't have any nice place to display LEDs. printf is a bad
173 * idea because Linux uses the LED as a heartbeat and the output
174 * will swamp anything else on the terminal.
177 /* Note that the RESET bit [3] always reads as zero */
178 s
->cm_ctrl
= (s
->cm_ctrl
& ~5) | (value
& 5);
179 integratorcm_do_remap(s
);
182 static void integratorcm_update(IntegratorCMState
*s
)
184 /* ??? The CPU irq/fiq is raised when either the core module or base PIC
186 if (s
->int_level
& (s
->irq_enabled
| s
->fiq_enabled
))
187 hw_error("Core module interrupt\n");
190 static void integratorcm_write(void *opaque
, hwaddr offset
,
191 uint64_t value
, unsigned size
)
193 IntegratorCMState
*s
= opaque
;
194 switch (offset
>> 2) {
196 if (s
->cm_lock
== 0xa05f)
199 case 3: /* CM_CTRL */
200 integratorcm_set_ctrl(s
, value
);
202 case 5: /* CM_LOCK */
203 s
->cm_lock
= value
& 0xffff;
205 case 7: /* CM_AUXOSC */
206 if (s
->cm_lock
== 0xa05f)
207 s
->cm_auxosc
= value
;
209 case 8: /* CM_SDRAM */
212 case 9: /* CM_INIT */
213 /* ??? This can change the memory bus frequency. */
216 case 12: /* CM_FLAGSS */
217 s
->cm_flags
|= value
;
219 case 13: /* CM_FLAGSC */
220 s
->cm_flags
&= ~value
;
222 case 14: /* CM_NVFLAGSS */
223 s
->cm_nvflags
|= value
;
225 case 15: /* CM_NVFLAGSS */
226 s
->cm_nvflags
&= ~value
;
228 case 18: /* CM_IRQ_ENSET */
229 s
->irq_enabled
|= value
;
230 integratorcm_update(s
);
232 case 19: /* CM_IRQ_ENCLR */
233 s
->irq_enabled
&= ~value
;
234 integratorcm_update(s
);
236 case 20: /* CM_SOFT_INTSET */
237 s
->int_level
|= (value
& 1);
238 integratorcm_update(s
);
240 case 21: /* CM_SOFT_INTCLR */
241 s
->int_level
&= ~(value
& 1);
242 integratorcm_update(s
);
244 case 26: /* CM_FIQ_ENSET */
245 s
->fiq_enabled
|= value
;
246 integratorcm_update(s
);
248 case 27: /* CM_FIQ_ENCLR */
249 s
->fiq_enabled
&= ~value
;
250 integratorcm_update(s
);
252 case 32: /* CM_VOLTAGE_CTL0 */
253 case 33: /* CM_VOLTAGE_CTL1 */
254 case 34: /* CM_VOLTAGE_CTL2 */
255 case 35: /* CM_VOLTAGE_CTL3 */
256 /* ??? Voltage control unimplemented. */
259 qemu_log_mask(LOG_UNIMP
,
260 "%s: Unimplemented offset 0x%" HWADDR_PRIX
"\n",
266 /* Integrator/CM control registers. */
268 static const MemoryRegionOps integratorcm_ops
= {
269 .read
= integratorcm_read
,
270 .write
= integratorcm_write
,
271 .endianness
= DEVICE_NATIVE_ENDIAN
,
274 static void integratorcm_init(Object
*obj
)
276 IntegratorCMState
*s
= INTEGRATOR_CM(obj
);
278 s
->cm_osc
= 0x01000048;
279 /* ??? What should the high bits of this value be? */
280 s
->cm_auxosc
= 0x0007feff;
281 s
->cm_sdram
= 0x00011122;
282 memcpy(integrator_spd
+ 73, "QEMU-MEMORY", 11);
283 s
->cm_init
= 0x00000112;
284 s
->cm_refcnt_offset
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), 24,
287 /* ??? Save/restore. */
290 static void integratorcm_realize(DeviceState
*d
, Error
**errp
)
292 IntegratorCMState
*s
= INTEGRATOR_CM(d
);
293 SysBusDevice
*dev
= SYS_BUS_DEVICE(d
);
294 Error
*local_err
= NULL
;
296 memory_region_init_ram(&s
->flash
, OBJECT(d
), "integrator.flash", 0x100000,
299 error_propagate(errp
, local_err
);
303 memory_region_init_io(&s
->iomem
, OBJECT(d
), &integratorcm_ops
, s
,
304 "integratorcm", 0x00800000);
305 sysbus_init_mmio(dev
, &s
->iomem
);
307 integratorcm_do_remap(s
);
309 if (s
->memsz
>= 256) {
310 integrator_spd
[31] = 64;
312 } else if (s
->memsz
>= 128) {
313 integrator_spd
[31] = 32;
315 } else if (s
->memsz
>= 64) {
316 integrator_spd
[31] = 16;
318 } else if (s
->memsz
>= 32) {
319 integrator_spd
[31] = 4;
322 integrator_spd
[31] = 2;
326 /* Integrator/CP hardware emulation. */
327 /* Primary interrupt controller. */
329 #define TYPE_INTEGRATOR_PIC "integrator_pic"
330 OBJECT_DECLARE_SIMPLE_TYPE(icp_pic_state
, INTEGRATOR_PIC
)
332 struct icp_pic_state
{
334 SysBusDevice parent_obj
;
339 uint32_t irq_enabled
;
340 uint32_t fiq_enabled
;
345 static const VMStateDescription vmstate_icp_pic
= {
348 .minimum_version_id
= 1,
349 .fields
= (VMStateField
[]) {
350 VMSTATE_UINT32(level
, icp_pic_state
),
351 VMSTATE_UINT32(irq_enabled
, icp_pic_state
),
352 VMSTATE_UINT32(fiq_enabled
, icp_pic_state
),
353 VMSTATE_END_OF_LIST()
357 static void icp_pic_update(icp_pic_state
*s
)
361 flags
= (s
->level
& s
->irq_enabled
);
362 qemu_set_irq(s
->parent_irq
, flags
!= 0);
363 flags
= (s
->level
& s
->fiq_enabled
);
364 qemu_set_irq(s
->parent_fiq
, flags
!= 0);
367 static void icp_pic_set_irq(void *opaque
, int irq
, int level
)
369 icp_pic_state
*s
= (icp_pic_state
*)opaque
;
371 s
->level
|= 1 << irq
;
373 s
->level
&= ~(1 << irq
);
377 static uint64_t icp_pic_read(void *opaque
, hwaddr offset
,
380 icp_pic_state
*s
= (icp_pic_state
*)opaque
;
382 switch (offset
>> 2) {
383 case 0: /* IRQ_STATUS */
384 return s
->level
& s
->irq_enabled
;
385 case 1: /* IRQ_RAWSTAT */
387 case 2: /* IRQ_ENABLESET */
388 return s
->irq_enabled
;
389 case 4: /* INT_SOFTSET */
391 case 8: /* FRQ_STATUS */
392 return s
->level
& s
->fiq_enabled
;
393 case 9: /* FRQ_RAWSTAT */
395 case 10: /* FRQ_ENABLESET */
396 return s
->fiq_enabled
;
397 case 3: /* IRQ_ENABLECLR */
398 case 5: /* INT_SOFTCLR */
399 case 11: /* FRQ_ENABLECLR */
401 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad offset 0x%" HWADDR_PRIX
"\n",
407 static void icp_pic_write(void *opaque
, hwaddr offset
,
408 uint64_t value
, unsigned size
)
410 icp_pic_state
*s
= (icp_pic_state
*)opaque
;
412 switch (offset
>> 2) {
413 case 2: /* IRQ_ENABLESET */
414 s
->irq_enabled
|= value
;
416 case 3: /* IRQ_ENABLECLR */
417 s
->irq_enabled
&= ~value
;
419 case 4: /* INT_SOFTSET */
421 icp_pic_set_irq(s
, 0, 1);
423 case 5: /* INT_SOFTCLR */
425 icp_pic_set_irq(s
, 0, 0);
427 case 10: /* FRQ_ENABLESET */
428 s
->fiq_enabled
|= value
;
430 case 11: /* FRQ_ENABLECLR */
431 s
->fiq_enabled
&= ~value
;
433 case 0: /* IRQ_STATUS */
434 case 1: /* IRQ_RAWSTAT */
435 case 8: /* FRQ_STATUS */
436 case 9: /* FRQ_RAWSTAT */
438 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad offset 0x%" HWADDR_PRIX
"\n",
445 static const MemoryRegionOps icp_pic_ops
= {
446 .read
= icp_pic_read
,
447 .write
= icp_pic_write
,
448 .endianness
= DEVICE_NATIVE_ENDIAN
,
451 static void icp_pic_init(Object
*obj
)
453 DeviceState
*dev
= DEVICE(obj
);
454 icp_pic_state
*s
= INTEGRATOR_PIC(obj
);
455 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
457 qdev_init_gpio_in(dev
, icp_pic_set_irq
, 32);
458 sysbus_init_irq(sbd
, &s
->parent_irq
);
459 sysbus_init_irq(sbd
, &s
->parent_fiq
);
460 memory_region_init_io(&s
->iomem
, obj
, &icp_pic_ops
, s
,
461 "icp-pic", 0x00800000);
462 sysbus_init_mmio(sbd
, &s
->iomem
);
465 /* CP control registers. */
467 #define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs"
468 OBJECT_DECLARE_SIMPLE_TYPE(ICPCtrlRegsState
, ICP_CONTROL_REGS
)
470 struct ICPCtrlRegsState
{
472 SysBusDevice parent_obj
;
478 uint32_t intreg_state
;
481 #define ICP_GPIO_MMC_WPROT "mmc-wprot"
482 #define ICP_GPIO_MMC_CARDIN "mmc-cardin"
484 #define ICP_INTREG_WPROT (1 << 0)
485 #define ICP_INTREG_CARDIN (1 << 3)
487 static const VMStateDescription vmstate_icp_control
= {
488 .name
= "icp_control",
490 .minimum_version_id
= 1,
491 .fields
= (VMStateField
[]) {
492 VMSTATE_UINT32(intreg_state
, ICPCtrlRegsState
),
493 VMSTATE_END_OF_LIST()
497 static uint64_t icp_control_read(void *opaque
, hwaddr offset
,
500 ICPCtrlRegsState
*s
= opaque
;
502 switch (offset
>> 2) {
503 case 0: /* CP_IDFIELD */
505 case 1: /* CP_FLASHPROG */
507 case 2: /* CP_INTREG */
508 return s
->intreg_state
;
509 case 3: /* CP_DECODE */
512 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad offset 0x%" HWADDR_PRIX
"\n",
518 static void icp_control_write(void *opaque
, hwaddr offset
,
519 uint64_t value
, unsigned size
)
521 ICPCtrlRegsState
*s
= opaque
;
523 switch (offset
>> 2) {
524 case 2: /* CP_INTREG */
525 s
->intreg_state
&= ~(value
& ICP_INTREG_CARDIN
);
526 qemu_set_irq(s
->mmc_irq
, !!(s
->intreg_state
& ICP_INTREG_CARDIN
));
528 case 1: /* CP_FLASHPROG */
529 case 3: /* CP_DECODE */
530 /* Nothing interesting implemented yet. */
533 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad offset 0x%" HWADDR_PRIX
"\n",
538 static const MemoryRegionOps icp_control_ops
= {
539 .read
= icp_control_read
,
540 .write
= icp_control_write
,
541 .endianness
= DEVICE_NATIVE_ENDIAN
,
544 static void icp_control_mmc_wprot(void *opaque
, int line
, int level
)
546 ICPCtrlRegsState
*s
= opaque
;
548 s
->intreg_state
&= ~ICP_INTREG_WPROT
;
550 s
->intreg_state
|= ICP_INTREG_WPROT
;
554 static void icp_control_mmc_cardin(void *opaque
, int line
, int level
)
556 ICPCtrlRegsState
*s
= opaque
;
558 /* line is released by writing to CP_INTREG */
560 s
->intreg_state
|= ICP_INTREG_CARDIN
;
561 qemu_set_irq(s
->mmc_irq
, 1);
565 static void icp_control_init(Object
*obj
)
567 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
568 ICPCtrlRegsState
*s
= ICP_CONTROL_REGS(obj
);
569 DeviceState
*dev
= DEVICE(obj
);
571 memory_region_init_io(&s
->iomem
, OBJECT(s
), &icp_control_ops
, s
,
572 "icp_ctrl_regs", 0x00800000);
573 sysbus_init_mmio(sbd
, &s
->iomem
);
575 qdev_init_gpio_in_named(dev
, icp_control_mmc_wprot
, ICP_GPIO_MMC_WPROT
, 1);
576 qdev_init_gpio_in_named(dev
, icp_control_mmc_cardin
,
577 ICP_GPIO_MMC_CARDIN
, 1);
578 sysbus_init_irq(sbd
, &s
->mmc_irq
);
584 static struct arm_boot_info integrator_binfo
= {
589 static void integratorcp_init(MachineState
*machine
)
591 ram_addr_t ram_size
= machine
->ram_size
;
594 MemoryRegion
*address_space_mem
= get_system_memory();
595 MemoryRegion
*ram_alias
= g_new(MemoryRegion
, 1);
597 DeviceState
*dev
, *sic
, *icp
;
601 cpuobj
= object_new(machine
->cpu_type
);
603 /* By default ARM1176 CPUs have EL3 enabled. This board does not
604 * currently support EL3 so the CPU EL3 property is disabled before
607 if (object_property_find(cpuobj
, "has_el3")) {
608 object_property_set_bool(cpuobj
, "has_el3", false, &error_fatal
);
611 qdev_realize(DEVICE(cpuobj
), NULL
, &error_fatal
);
613 cpu
= ARM_CPU(cpuobj
);
615 /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
616 /* ??? RAM should repeat to fill physical memory space. */
617 /* SDRAM at address zero*/
618 memory_region_add_subregion(address_space_mem
, 0, machine
->ram
);
619 /* And again at address 0x80000000 */
620 memory_region_init_alias(ram_alias
, NULL
, "ram.alias", machine
->ram
,
622 memory_region_add_subregion(address_space_mem
, 0x80000000, ram_alias
);
624 dev
= qdev_new(TYPE_INTEGRATOR_CM
);
625 qdev_prop_set_uint32(dev
, "memsz", ram_size
>> 20);
626 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
627 sysbus_mmio_map((SysBusDevice
*)dev
, 0, 0x10000000);
629 dev
= sysbus_create_varargs(TYPE_INTEGRATOR_PIC
, 0x14000000,
630 qdev_get_gpio_in(DEVICE(cpu
), ARM_CPU_IRQ
),
631 qdev_get_gpio_in(DEVICE(cpu
), ARM_CPU_FIQ
),
633 for (i
= 0; i
< 32; i
++) {
634 pic
[i
] = qdev_get_gpio_in(dev
, i
);
636 sic
= sysbus_create_simple(TYPE_INTEGRATOR_PIC
, 0xca000000, pic
[26]);
637 sysbus_create_varargs("integrator_pit", 0x13000000,
638 pic
[5], pic
[6], pic
[7], NULL
);
639 sysbus_create_simple("pl031", 0x15000000, pic
[8]);
640 pl011_create(0x16000000, pic
[1], serial_hd(0));
641 pl011_create(0x17000000, pic
[2], serial_hd(1));
642 icp
= sysbus_create_simple(TYPE_ICP_CONTROL_REGS
, 0xcb000000,
643 qdev_get_gpio_in(sic
, 3));
644 sysbus_create_simple("pl050_keyboard", 0x18000000, pic
[3]);
645 sysbus_create_simple("pl050_mouse", 0x19000000, pic
[4]);
646 sysbus_create_simple(TYPE_INTEGRATOR_DEBUG
, 0x1a000000, 0);
648 dev
= sysbus_create_varargs("pl181", 0x1c000000, pic
[23], pic
[24], NULL
);
649 qdev_connect_gpio_out_named(dev
, "card-read-only", 0,
650 qdev_get_gpio_in_named(icp
, ICP_GPIO_MMC_WPROT
, 0));
651 qdev_connect_gpio_out_named(dev
, "card-inserted", 0,
652 qdev_get_gpio_in_named(icp
, ICP_GPIO_MMC_CARDIN
, 0));
653 dinfo
= drive_get(IF_SD
, 0, 0);
657 card
= qdev_new(TYPE_SD_CARD
);
658 qdev_prop_set_drive_err(card
, "drive", blk_by_legacy_dinfo(dinfo
),
660 qdev_realize_and_unref(card
, qdev_get_child_bus(dev
, "sd-bus"),
664 dev
= qdev_new("pl041");
665 if (machine
->audiodev
) {
666 qdev_prop_set_string(dev
, "audiodev", machine
->audiodev
);
668 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
669 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, 0x1d000000);
670 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, pic
[25]);
672 if (nd_table
[0].used
)
673 smc91c111_init(&nd_table
[0], 0xc8000000, pic
[27]);
675 sysbus_create_simple("pl110", 0xc0000000, pic
[22]);
677 integrator_binfo
.ram_size
= ram_size
;
678 arm_load_kernel(cpu
, machine
, &integrator_binfo
);
681 static void integratorcp_machine_init(MachineClass
*mc
)
683 mc
->desc
= "ARM Integrator/CP (ARM926EJ-S)";
684 mc
->init
= integratorcp_init
;
685 mc
->ignore_memory_transaction_failures
= true;
686 mc
->default_cpu_type
= ARM_CPU_TYPE_NAME("arm926");
687 mc
->default_ram_id
= "integrator.ram";
689 machine_add_audiodev_property(mc
);
692 DEFINE_MACHINE("integratorcp", integratorcp_machine_init
)
694 static Property core_properties
[] = {
695 DEFINE_PROP_UINT32("memsz", IntegratorCMState
, memsz
, 0),
696 DEFINE_PROP_END_OF_LIST(),
699 static void core_class_init(ObjectClass
*klass
, void *data
)
701 DeviceClass
*dc
= DEVICE_CLASS(klass
);
703 device_class_set_props(dc
, core_properties
);
704 dc
->realize
= integratorcm_realize
;
705 dc
->vmsd
= &vmstate_integratorcm
;
708 static void icp_pic_class_init(ObjectClass
*klass
, void *data
)
710 DeviceClass
*dc
= DEVICE_CLASS(klass
);
712 dc
->vmsd
= &vmstate_icp_pic
;
715 static void icp_control_class_init(ObjectClass
*klass
, void *data
)
717 DeviceClass
*dc
= DEVICE_CLASS(klass
);
719 dc
->vmsd
= &vmstate_icp_control
;
722 static const TypeInfo core_info
= {
723 .name
= TYPE_INTEGRATOR_CM
,
724 .parent
= TYPE_SYS_BUS_DEVICE
,
725 .instance_size
= sizeof(IntegratorCMState
),
726 .instance_init
= integratorcm_init
,
727 .class_init
= core_class_init
,
730 static const TypeInfo icp_pic_info
= {
731 .name
= TYPE_INTEGRATOR_PIC
,
732 .parent
= TYPE_SYS_BUS_DEVICE
,
733 .instance_size
= sizeof(icp_pic_state
),
734 .instance_init
= icp_pic_init
,
735 .class_init
= icp_pic_class_init
,
738 static const TypeInfo icp_ctrl_regs_info
= {
739 .name
= TYPE_ICP_CONTROL_REGS
,
740 .parent
= TYPE_SYS_BUS_DEVICE
,
741 .instance_size
= sizeof(ICPCtrlRegsState
),
742 .instance_init
= icp_control_init
,
743 .class_init
= icp_control_class_init
,
746 static void integratorcp_register_types(void)
748 type_register_static(&icp_pic_info
);
749 type_register_static(&core_info
);
750 type_register_static(&icp_ctrl_regs_info
);
753 type_init(integratorcp_register_types
)