2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * KVM/MIPS: MIPS specific KVM APIs
8 * Copyright (C) 2012-2014 Imagination Technologies Ltd.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
12 #include <sys/types.h>
13 #include <sys/ioctl.h>
16 #include <linux/kvm.h>
18 #include "qemu-common.h"
19 #include "qemu/error-report.h"
20 #include "qemu/timer.h"
21 #include "sysemu/sysemu.h"
22 #include "sysemu/kvm.h"
24 #include "sysemu/cpus.h"
29 #define DPRINTF(fmt, ...) \
30 do { if (DEBUG_KVM) { fprintf(stderr, fmt, ## __VA_ARGS__); } } while (0)
32 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
36 static void kvm_mips_update_state(void *opaque
, int running
, RunState state
);
38 unsigned long kvm_arch_vcpu_id(CPUState
*cs
)
43 int kvm_arch_init(KVMState
*s
)
45 /* MIPS has 128 signals */
46 kvm_set_sigmask_len(s
, 16);
48 DPRINTF("%s\n", __func__
);
52 int kvm_arch_init_vcpu(CPUState
*cs
)
56 qemu_add_vm_change_state_handler(kvm_mips_update_state
, cs
);
58 DPRINTF("%s\n", __func__
);
62 void kvm_mips_reset_vcpu(MIPSCPU
*cpu
)
64 DPRINTF("%s\n", __func__
);
67 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
69 DPRINTF("%s\n", __func__
);
73 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
75 DPRINTF("%s\n", __func__
);
79 static inline int cpu_mips_io_interrupts_pending(MIPSCPU
*cpu
)
81 CPUMIPSState
*env
= &cpu
->env
;
83 DPRINTF("%s: %#x\n", __func__
, env
->CP0_Cause
& (1 << (2 + CP0Ca_IP
)));
84 return env
->CP0_Cause
& (0x1 << (2 + CP0Ca_IP
));
88 void kvm_arch_pre_run(CPUState
*cs
, struct kvm_run
*run
)
90 MIPSCPU
*cpu
= MIPS_CPU(cs
);
92 struct kvm_mips_interrupt intr
;
94 if ((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
95 cpu_mips_io_interrupts_pending(cpu
)) {
98 r
= kvm_vcpu_ioctl(cs
, KVM_INTERRUPT
, &intr
);
100 error_report("%s: cpu %d: failed to inject IRQ %x",
101 __func__
, cs
->cpu_index
, intr
.irq
);
106 void kvm_arch_post_run(CPUState
*cs
, struct kvm_run
*run
)
108 DPRINTF("%s\n", __func__
);
111 int kvm_arch_process_async_events(CPUState
*cs
)
116 int kvm_arch_handle_exit(CPUState
*cs
, struct kvm_run
*run
)
120 DPRINTF("%s\n", __func__
);
121 switch (run
->exit_reason
) {
123 error_report("%s: unknown exit reason %d",
124 __func__
, run
->exit_reason
);
132 bool kvm_arch_stop_on_emulation_error(CPUState
*cs
)
134 DPRINTF("%s\n", __func__
);
138 int kvm_arch_on_sigbus_vcpu(CPUState
*cs
, int code
, void *addr
)
140 DPRINTF("%s\n", __func__
);
144 int kvm_arch_on_sigbus(int code
, void *addr
)
146 DPRINTF("%s\n", __func__
);
150 void kvm_arch_init_irq_routing(KVMState
*s
)
154 int kvm_mips_set_interrupt(MIPSCPU
*cpu
, int irq
, int level
)
156 CPUState
*cs
= CPU(cpu
);
157 struct kvm_mips_interrupt intr
;
159 if (!kvm_enabled()) {
171 kvm_vcpu_ioctl(cs
, KVM_INTERRUPT
, &intr
);
176 int kvm_mips_set_ipi_interrupt(MIPSCPU
*cpu
, int irq
, int level
)
178 CPUState
*cs
= current_cpu
;
179 CPUState
*dest_cs
= CPU(cpu
);
180 struct kvm_mips_interrupt intr
;
182 if (!kvm_enabled()) {
186 intr
.cpu
= dest_cs
->cpu_index
;
194 DPRINTF("%s: CPU %d, IRQ: %d\n", __func__
, intr
.cpu
, intr
.irq
);
196 kvm_vcpu_ioctl(cs
, KVM_INTERRUPT
, &intr
);
201 #define MIPS_CP0_32(_R, _S) \
202 (KVM_REG_MIPS | KVM_REG_SIZE_U32 | 0x10000 | (8 * (_R) + (_S)))
204 #define MIPS_CP0_64(_R, _S) \
205 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0x10000 | (8 * (_R) + (_S)))
207 #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
208 #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
209 #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
210 #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
211 #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
212 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
213 #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
214 #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
215 #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
216 #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
217 #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
218 #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
219 #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
220 #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
222 /* CP0_Count control */
223 #define KVM_REG_MIPS_COUNT_CTL (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \
225 #define KVM_REG_MIPS_COUNT_CTL_DC 0x00000001 /* master disable */
226 /* CP0_Count resume monotonic nanoseconds */
227 #define KVM_REG_MIPS_COUNT_RESUME (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \
229 /* CP0_Count rate in Hz */
230 #define KVM_REG_MIPS_COUNT_HZ (KVM_REG_MIPS | KVM_REG_SIZE_U64 | \
233 static inline int kvm_mips_put_one_reg(CPUState
*cs
, uint64_t reg_id
,
236 uint64_t val64
= *addr
;
237 struct kvm_one_reg cp0reg
= {
239 .addr
= (uintptr_t)&val64
242 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &cp0reg
);
245 static inline int kvm_mips_put_one_ulreg(CPUState
*cs
, uint64_t reg_id
,
248 uint64_t val64
= *addr
;
249 struct kvm_one_reg cp0reg
= {
251 .addr
= (uintptr_t)&val64
254 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &cp0reg
);
257 static inline int kvm_mips_put_one_reg64(CPUState
*cs
, uint64_t reg_id
,
260 struct kvm_one_reg cp0reg
= {
262 .addr
= (uintptr_t)addr
265 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, &cp0reg
);
268 static inline int kvm_mips_get_one_reg(CPUState
*cs
, uint64_t reg_id
,
273 struct kvm_one_reg cp0reg
= {
275 .addr
= (uintptr_t)&val64
278 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &cp0reg
);
285 static inline int kvm_mips_get_one_ulreg(CPUState
*cs
, uint64 reg_id
,
290 struct kvm_one_reg cp0reg
= {
292 .addr
= (uintptr_t)&val64
295 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &cp0reg
);
302 static inline int kvm_mips_get_one_reg64(CPUState
*cs
, uint64 reg_id
,
305 struct kvm_one_reg cp0reg
= {
307 .addr
= (uintptr_t)addr
310 return kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, &cp0reg
);
314 * We freeze the KVM timer when either the VM clock is stopped or the state is
315 * saved (the state is dirty).
319 * Save the state of the KVM timer when VM clock is stopped or state is synced
322 static int kvm_mips_save_count(CPUState
*cs
)
324 MIPSCPU
*cpu
= MIPS_CPU(cs
);
325 CPUMIPSState
*env
= &cpu
->env
;
329 /* freeze KVM timer */
330 err
= kvm_mips_get_one_reg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
332 DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__
, err
);
334 } else if (!(count_ctl
& KVM_REG_MIPS_COUNT_CTL_DC
)) {
335 count_ctl
|= KVM_REG_MIPS_COUNT_CTL_DC
;
336 err
= kvm_mips_put_one_reg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
338 DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__
, err
);
344 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_CAUSE
, &env
->CP0_Cause
);
346 DPRINTF("%s: Failed to get CP0_CAUSE (%d)\n", __func__
, err
);
351 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_COUNT
, &env
->CP0_Count
);
353 DPRINTF("%s: Failed to get CP0_COUNT (%d)\n", __func__
, err
);
361 * Restore the state of the KVM timer when VM clock is restarted or state is
364 static int kvm_mips_restore_count(CPUState
*cs
)
366 MIPSCPU
*cpu
= MIPS_CPU(cs
);
367 CPUMIPSState
*env
= &cpu
->env
;
369 int err_dc
, err
, ret
= 0;
371 /* check the timer is frozen */
372 err_dc
= kvm_mips_get_one_reg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
374 DPRINTF("%s: Failed to get COUNT_CTL (%d)\n", __func__
, err_dc
);
376 } else if (!(count_ctl
& KVM_REG_MIPS_COUNT_CTL_DC
)) {
377 /* freeze timer (sets COUNT_RESUME for us) */
378 count_ctl
|= KVM_REG_MIPS_COUNT_CTL_DC
;
379 err
= kvm_mips_put_one_reg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
381 DPRINTF("%s: Failed to set COUNT_CTL.DC=1 (%d)\n", __func__
, err
);
387 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_CAUSE
, &env
->CP0_Cause
);
389 DPRINTF("%s: Failed to put CP0_CAUSE (%d)\n", __func__
, err
);
394 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_COUNT
, &env
->CP0_Count
);
396 DPRINTF("%s: Failed to put CP0_COUNT (%d)\n", __func__
, err
);
400 /* resume KVM timer */
402 count_ctl
&= ~KVM_REG_MIPS_COUNT_CTL_DC
;
403 err
= kvm_mips_put_one_reg64(cs
, KVM_REG_MIPS_COUNT_CTL
, &count_ctl
);
405 DPRINTF("%s: Failed to set COUNT_CTL.DC=0 (%d)\n", __func__
, err
);
414 * Handle the VM clock being started or stopped
416 static void kvm_mips_update_state(void *opaque
, int running
, RunState state
)
418 CPUState
*cs
= opaque
;
420 uint64_t count_resume
;
423 * If state is already dirty (synced to QEMU) then the KVM timer state is
424 * already saved and can be restored when it is synced back to KVM.
427 if (!cs
->kvm_vcpu_dirty
) {
428 ret
= kvm_mips_save_count(cs
);
430 fprintf(stderr
, "Failed saving count\n");
434 /* Set clock restore time to now */
435 count_resume
= get_clock();
436 ret
= kvm_mips_put_one_reg64(cs
, KVM_REG_MIPS_COUNT_RESUME
,
439 fprintf(stderr
, "Failed setting COUNT_RESUME\n");
443 if (!cs
->kvm_vcpu_dirty
) {
444 ret
= kvm_mips_restore_count(cs
);
446 fprintf(stderr
, "Failed restoring count\n");
452 static int kvm_mips_put_cp0_registers(CPUState
*cs
, int level
)
454 MIPSCPU
*cpu
= MIPS_CPU(cs
);
455 CPUMIPSState
*env
= &cpu
->env
;
460 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_INDEX
, &env
->CP0_Index
);
462 DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__
, err
);
465 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_CONTEXT
,
468 DPRINTF("%s: Failed to put CP0_CONTEXT (%d)\n", __func__
, err
);
471 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_USERLOCAL
,
472 &env
->active_tc
.CP0_UserLocal
);
474 DPRINTF("%s: Failed to put CP0_USERLOCAL (%d)\n", __func__
, err
);
477 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_PAGEMASK
,
480 DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__
, err
);
483 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_WIRED
, &env
->CP0_Wired
);
485 DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__
, err
);
488 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_HWRENA
, &env
->CP0_HWREna
);
490 DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__
, err
);
493 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_BADVADDR
,
496 DPRINTF("%s: Failed to put CP0_BADVADDR (%d)\n", __func__
, err
);
500 /* If VM clock stopped then state will be restored when it is restarted */
501 if (runstate_is_running()) {
502 err
= kvm_mips_restore_count(cs
);
508 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_ENTRYHI
,
511 DPRINTF("%s: Failed to put CP0_ENTRYHI (%d)\n", __func__
, err
);
514 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_COMPARE
,
517 DPRINTF("%s: Failed to put CP0_COMPARE (%d)\n", __func__
, err
);
520 err
= kvm_mips_put_one_reg(cs
, KVM_REG_MIPS_CP0_STATUS
, &env
->CP0_Status
);
522 DPRINTF("%s: Failed to put CP0_STATUS (%d)\n", __func__
, err
);
525 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_EPC
, &env
->CP0_EPC
);
527 DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__
, err
);
530 err
= kvm_mips_put_one_ulreg(cs
, KVM_REG_MIPS_CP0_ERROREPC
,
533 DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__
, err
);
540 static int kvm_mips_get_cp0_registers(CPUState
*cs
)
542 MIPSCPU
*cpu
= MIPS_CPU(cs
);
543 CPUMIPSState
*env
= &cpu
->env
;
546 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_INDEX
, &env
->CP0_Index
);
548 DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__
, err
);
551 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_CONTEXT
,
554 DPRINTF("%s: Failed to get CP0_CONTEXT (%d)\n", __func__
, err
);
557 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_USERLOCAL
,
558 &env
->active_tc
.CP0_UserLocal
);
560 DPRINTF("%s: Failed to get CP0_USERLOCAL (%d)\n", __func__
, err
);
563 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_PAGEMASK
,
566 DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__
, err
);
569 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_WIRED
, &env
->CP0_Wired
);
571 DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__
, err
);
574 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_HWRENA
, &env
->CP0_HWREna
);
576 DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__
, err
);
579 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_BADVADDR
,
582 DPRINTF("%s: Failed to get CP0_BADVADDR (%d)\n", __func__
, err
);
585 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_ENTRYHI
,
588 DPRINTF("%s: Failed to get CP0_ENTRYHI (%d)\n", __func__
, err
);
591 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_COMPARE
,
594 DPRINTF("%s: Failed to get CP0_COMPARE (%d)\n", __func__
, err
);
597 err
= kvm_mips_get_one_reg(cs
, KVM_REG_MIPS_CP0_STATUS
, &env
->CP0_Status
);
599 DPRINTF("%s: Failed to get CP0_STATUS (%d)\n", __func__
, err
);
603 /* If VM clock stopped then state was already saved when it was stopped */
604 if (runstate_is_running()) {
605 err
= kvm_mips_save_count(cs
);
611 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_EPC
, &env
->CP0_EPC
);
613 DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__
, err
);
616 err
= kvm_mips_get_one_ulreg(cs
, KVM_REG_MIPS_CP0_ERROREPC
,
619 DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__
, err
);
626 int kvm_arch_put_registers(CPUState
*cs
, int level
)
628 MIPSCPU
*cpu
= MIPS_CPU(cs
);
629 CPUMIPSState
*env
= &cpu
->env
;
630 struct kvm_regs regs
;
634 /* Set the registers based on QEMU's view of things */
635 for (i
= 0; i
< 32; i
++) {
636 regs
.gpr
[i
] = env
->active_tc
.gpr
[i
];
639 regs
.hi
= env
->active_tc
.HI
[0];
640 regs
.lo
= env
->active_tc
.LO
[0];
641 regs
.pc
= env
->active_tc
.PC
;
643 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_REGS
, ®s
);
649 ret
= kvm_mips_put_cp0_registers(cs
, level
);
657 int kvm_arch_get_registers(CPUState
*cs
)
659 MIPSCPU
*cpu
= MIPS_CPU(cs
);
660 CPUMIPSState
*env
= &cpu
->env
;
662 struct kvm_regs regs
;
665 /* Get the current register set as KVM seems it */
666 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_REGS
, ®s
);
672 for (i
= 0; i
< 32; i
++) {
673 env
->active_tc
.gpr
[i
] = regs
.gpr
[i
];
676 env
->active_tc
.HI
[0] = regs
.hi
;
677 env
->active_tc
.LO
[0] = regs
.lo
;
678 env
->active_tc
.PC
= regs
.pc
;
680 kvm_mips_get_cp0_registers(cs
);