2 * Q35 chipset based pc system emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2009, 2010
6 * Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
10 * This is based on pc.c, but heavily modified.
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 #include "hw/loader.h"
32 #include "sysemu/arch_init.h"
33 #include "hw/i2c/smbus.h"
34 #include "hw/boards.h"
35 #include "hw/timer/mc146818rtc.h"
36 #include "hw/xen/xen.h"
37 #include "sysemu/kvm.h"
38 #include "hw/kvm/clock.h"
39 #include "hw/pci-host/q35.h"
40 #include "exec/address-spaces.h"
41 #include "hw/i386/ich9.h"
42 #include "hw/i386/smbios.h"
43 #include "hw/ide/pci.h"
44 #include "hw/ide/ahci.h"
46 #include "hw/cpu/icc_bus.h"
47 #include "qemu/error-report.h"
49 /* ICH9 AHCI has 6 ports */
50 #define MAX_SATA_PORTS 6
52 static bool has_acpi_build
= true;
53 static bool smbios_defaults
= true;
54 static bool smbios_legacy_mode
;
55 /* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to
56 * host addresses aligned at 1Gbyte boundaries. This way we can use 1GByte
59 static bool gigabyte_align
= true;
60 static bool has_reserved_memory
= true;
62 /* PC hardware initialisation */
63 static void pc_q35_init(MachineState
*machine
)
65 PCMachineState
*pc_machine
= PC_MACHINE(machine
);
66 ram_addr_t below_4g_mem_size
, above_4g_mem_size
;
71 BusState
*idebus
[MAX_SATA_PORTS
];
74 MemoryRegion
*pci_memory
;
75 MemoryRegion
*rom_memory
;
76 MemoryRegion
*ram_memory
;
84 ICH9LPCState
*ich9_lpc
;
86 DeviceState
*icc_bridge
;
87 PcGuestInfo
*guest_info
;
90 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
91 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
92 * also known as MMCFG).
93 * If it doesn't, we need to split it in chunks below and above 4G.
94 * In any case, try to make sure that guest addresses aligned at
95 * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
96 * For old machine types, use whatever split we used historically to avoid
99 if (machine
->ram_size
>= 0xb0000000) {
100 lowmem
= gigabyte_align
? 0x80000000 : 0xb0000000;
105 /* Handle the machine opt max-ram-below-4g. It is basically doing
106 * min(qemu limit, user limit).
108 if (lowmem
> pc_machine
->max_ram_below_4g
) {
109 lowmem
= pc_machine
->max_ram_below_4g
;
110 if (machine
->ram_size
- lowmem
> lowmem
&&
111 lowmem
& ((1ULL << 30) - 1)) {
112 error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64
113 ") not a multiple of 1G; possible bad performance.",
114 pc_machine
->max_ram_below_4g
);
118 if (machine
->ram_size
>= lowmem
) {
119 above_4g_mem_size
= machine
->ram_size
- lowmem
;
120 below_4g_mem_size
= lowmem
;
122 above_4g_mem_size
= 0;
123 below_4g_mem_size
= machine
->ram_size
;
126 if (xen_enabled() && xen_hvm_init(&below_4g_mem_size
, &above_4g_mem_size
,
128 fprintf(stderr
, "xen hardware virtual machine initialisation failed\n");
132 icc_bridge
= qdev_create(NULL
, TYPE_ICC_BRIDGE
);
133 object_property_add_child(qdev_get_machine(), "icc-bridge",
134 OBJECT(icc_bridge
), NULL
);
136 pc_cpus_init(machine
->cpu_model
, icc_bridge
);
137 pc_acpi_init("q35-acpi-dsdt.aml");
143 pci_memory
= g_new(MemoryRegion
, 1);
144 memory_region_init(pci_memory
, NULL
, "pci", UINT64_MAX
);
145 rom_memory
= pci_memory
;
148 rom_memory
= get_system_memory();
151 guest_info
= pc_guest_info_init(below_4g_mem_size
, above_4g_mem_size
);
152 guest_info
->isapc_ram_fw
= false;
153 guest_info
->has_acpi_build
= has_acpi_build
;
154 guest_info
->has_reserved_memory
= has_reserved_memory
;
156 /* Migration was not supported in 2.0 for Q35, so do not bother
157 * with this hack (see hw/i386/acpi-build.c).
159 guest_info
->legacy_acpi_table_size
= 0;
161 if (smbios_defaults
) {
162 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
163 /* These values are guest ABI, do not change */
164 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
165 mc
->name
, smbios_legacy_mode
);
168 /* allocate ram and load rom/bios */
169 if (!xen_enabled()) {
170 pc_memory_init(machine
, get_system_memory(),
171 below_4g_mem_size
, above_4g_mem_size
,
172 rom_memory
, &ram_memory
, guest_info
);
176 gsi_state
= g_malloc0(sizeof(*gsi_state
));
177 if (kvm_irqchip_in_kernel()) {
178 kvm_pc_setup_irq_routing(pci_enabled
);
179 gsi
= qemu_allocate_irqs(kvm_pc_gsi_handler
, gsi_state
,
182 gsi
= qemu_allocate_irqs(gsi_handler
, gsi_state
, GSI_NUM_PINS
);
185 /* create pci host bus */
186 q35_host
= Q35_HOST_DEVICE(qdev_create(NULL
, TYPE_Q35_HOST_DEVICE
));
188 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host
), NULL
);
189 q35_host
->mch
.ram_memory
= ram_memory
;
190 q35_host
->mch
.pci_address_space
= pci_memory
;
191 q35_host
->mch
.system_memory
= get_system_memory();
192 q35_host
->mch
.address_space_io
= get_system_io();
193 q35_host
->mch
.below_4g_mem_size
= below_4g_mem_size
;
194 q35_host
->mch
.above_4g_mem_size
= above_4g_mem_size
;
195 q35_host
->mch
.guest_info
= guest_info
;
197 qdev_init_nofail(DEVICE(q35_host
));
198 phb
= PCI_HOST_BRIDGE(q35_host
);
201 lpc
= pci_create_simple_multifunction(host_bus
, PCI_DEVFN(ICH9_LPC_DEV
,
202 ICH9_LPC_FUNC
), true,
203 TYPE_ICH9_LPC_DEVICE
);
205 object_property_add_link(OBJECT(machine
), PC_MACHINE_ACPI_DEVICE_PROP
,
206 TYPE_HOTPLUG_HANDLER
,
207 (Object
**)&pc_machine
->acpi_dev
,
208 object_property_allow_set_link
,
209 OBJ_PROP_LINK_UNREF_ON_RELEASE
, &error_abort
);
210 object_property_set_link(OBJECT(machine
), OBJECT(lpc
),
211 PC_MACHINE_ACPI_DEVICE_PROP
, &error_abort
);
213 ich9_lpc
= ICH9_LPC_DEVICE(lpc
);
215 ich9_lpc
->ioapic
= gsi_state
->ioapic_irq
;
216 pci_bus_irqs(host_bus
, ich9_lpc_set_irq
, ich9_lpc_map_irq
, ich9_lpc
,
218 pci_bus_set_route_irq_fn(host_bus
, ich9_route_intx_pin_to_irq
);
219 isa_bus
= ich9_lpc
->isa_bus
;
222 isa_bus_irqs(isa_bus
, gsi
);
224 if (kvm_irqchip_in_kernel()) {
225 i8259
= kvm_i8259_init(isa_bus
);
226 } else if (xen_enabled()) {
227 i8259
= xen_interrupt_controller_init();
229 cpu_irq
= pc_allocate_cpu_irq();
230 i8259
= i8259_init(isa_bus
, cpu_irq
[0]);
233 for (i
= 0; i
< ISA_NUM_IRQS
; i
++) {
234 gsi_state
->i8259_irq
[i
] = i8259
[i
];
237 ioapic_init_gsi(gsi_state
, "q35");
239 qdev_init_nofail(icc_bridge
);
241 pc_register_ferr_irq(gsi
[13]);
243 /* init basic PC hardware */
244 pc_basic_device_init(isa_bus
, gsi
, &rtc_state
, &floppy
, false, 0xff0104);
246 /* connect pm stuff to lpc */
247 ich9_lpc_pm_init(lpc
);
249 /* ahci and SATA device, for q35 1 ahci controller is built-in */
250 ahci
= pci_create_simple_multifunction(host_bus
,
251 PCI_DEVFN(ICH9_SATA1_DEV
,
254 idebus
[0] = qdev_get_child_bus(&ahci
->qdev
, "ide.0");
255 idebus
[1] = qdev_get_child_bus(&ahci
->qdev
, "ide.1");
257 if (usb_enabled(false)) {
258 /* Should we create 6 UHCI according to ich9 spec? */
259 ehci_create_ich9_with_companions(host_bus
, 0x1d);
262 /* TODO: Populate SPD eeprom data. */
263 smbus_eeprom_init(ich9_smb_init(host_bus
,
264 PCI_DEVFN(ICH9_SMB_DEV
, ICH9_SMB_FUNC
),
268 pc_cmos_init(below_4g_mem_size
, above_4g_mem_size
, machine
->boot_order
,
269 floppy
, idebus
[0], idebus
[1], rtc_state
);
271 /* the rest devices to which pci devfn is automatically assigned */
272 pc_vga_init(isa_bus
, host_bus
);
273 pc_nic_init(isa_bus
, host_bus
);
275 pc_pci_device_init(host_bus
);
279 static void pc_compat_2_0(MachineState
*machine
)
281 smbios_legacy_mode
= true;
282 has_reserved_memory
= false;
285 static void pc_compat_1_7(MachineState
*machine
)
287 pc_compat_2_0(machine
);
288 smbios_defaults
= false;
289 gigabyte_align
= false;
290 option_rom_has_mr
= true;
291 x86_cpu_compat_disable_kvm_features(FEAT_1_ECX
, CPUID_EXT_X2APIC
);
294 static void pc_compat_1_6(MachineState
*machine
)
296 pc_compat_1_7(machine
);
297 rom_file_has_mr
= false;
298 has_acpi_build
= false;
301 static void pc_compat_1_5(MachineState
*machine
)
303 pc_compat_1_6(machine
);
306 static void pc_compat_1_4(MachineState
*machine
)
308 pc_compat_1_5(machine
);
309 x86_cpu_compat_set_features("n270", FEAT_1_ECX
, 0, CPUID_EXT_MOVBE
);
310 x86_cpu_compat_set_features("Westmere", FEAT_1_ECX
, 0, CPUID_EXT_PCLMULQDQ
);
313 static void pc_q35_init_2_0(MachineState
*machine
)
315 pc_compat_2_0(machine
);
316 pc_q35_init(machine
);
319 static void pc_q35_init_1_7(MachineState
*machine
)
321 pc_compat_1_7(machine
);
322 pc_q35_init(machine
);
325 static void pc_q35_init_1_6(MachineState
*machine
)
327 pc_compat_1_6(machine
);
328 pc_q35_init(machine
);
331 static void pc_q35_init_1_5(MachineState
*machine
)
333 pc_compat_1_5(machine
);
334 pc_q35_init(machine
);
337 static void pc_q35_init_1_4(MachineState
*machine
)
339 pc_compat_1_4(machine
);
340 pc_q35_init(machine
);
343 #define PC_Q35_MACHINE_OPTIONS \
344 PC_DEFAULT_MACHINE_OPTIONS, \
345 .desc = "Standard PC (Q35 + ICH9, 2009)", \
346 .hot_add_cpu = pc_hot_add_cpu
348 #define PC_Q35_2_2_MACHINE_OPTIONS \
349 PC_Q35_MACHINE_OPTIONS, \
350 .default_machine_opts = "firmware=bios-256k.bin"
352 static QEMUMachine pc_q35_machine_v2_2
= {
353 PC_Q35_2_2_MACHINE_OPTIONS
,
354 .name
= "pc-q35-2.2",
359 #define PC_Q35_2_1_MACHINE_OPTIONS PC_Q35_2_2_MACHINE_OPTIONS
361 static QEMUMachine pc_q35_machine_v2_1
= {
362 PC_Q35_2_1_MACHINE_OPTIONS
,
363 .name
= "pc-q35-2.1",
365 .compat_props
= (GlobalProperty
[]) {
367 { /* end of list */ }
371 #define PC_Q35_2_0_MACHINE_OPTIONS PC_Q35_2_1_MACHINE_OPTIONS
373 static QEMUMachine pc_q35_machine_v2_0
= {
374 PC_Q35_2_0_MACHINE_OPTIONS
,
375 .name
= "pc-q35-2.0",
376 .init
= pc_q35_init_2_0
,
377 .compat_props
= (GlobalProperty
[]) {
379 { /* end of list */ }
383 #define PC_Q35_1_7_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS
385 static QEMUMachine pc_q35_machine_v1_7
= {
386 PC_Q35_1_7_MACHINE_OPTIONS
,
387 .name
= "pc-q35-1.7",
388 .init
= pc_q35_init_1_7
,
389 .compat_props
= (GlobalProperty
[]) {
391 { /* end of list */ }
395 #define PC_Q35_1_6_MACHINE_OPTIONS PC_Q35_MACHINE_OPTIONS
397 static QEMUMachine pc_q35_machine_v1_6
= {
398 PC_Q35_1_6_MACHINE_OPTIONS
,
399 .name
= "pc-q35-1.6",
400 .init
= pc_q35_init_1_6
,
401 .compat_props
= (GlobalProperty
[]) {
403 { /* end of list */ }
407 static QEMUMachine pc_q35_machine_v1_5
= {
408 PC_Q35_1_6_MACHINE_OPTIONS
,
409 .name
= "pc-q35-1.5",
410 .init
= pc_q35_init_1_5
,
411 .compat_props
= (GlobalProperty
[]) {
413 { /* end of list */ }
417 #define PC_Q35_1_4_MACHINE_OPTIONS \
418 PC_Q35_1_6_MACHINE_OPTIONS, \
421 static QEMUMachine pc_q35_machine_v1_4
= {
422 PC_Q35_1_4_MACHINE_OPTIONS
,
423 .name
= "pc-q35-1.4",
424 .init
= pc_q35_init_1_4
,
425 .compat_props
= (GlobalProperty
[]) {
427 { /* end of list */ }
431 static void pc_q35_machine_init(void)
433 qemu_register_pc_machine(&pc_q35_machine_v2_2
);
434 qemu_register_pc_machine(&pc_q35_machine_v2_1
);
435 qemu_register_pc_machine(&pc_q35_machine_v2_0
);
436 qemu_register_pc_machine(&pc_q35_machine_v1_7
);
437 qemu_register_pc_machine(&pc_q35_machine_v1_6
);
438 qemu_register_pc_machine(&pc_q35_machine_v1_5
);
439 qemu_register_pc_machine(&pc_q35_machine_v1_4
);
442 machine_init(pc_q35_machine_init
);