4 #include "qemu-common.h"
7 #include "exec/memory.h"
8 #include "sysemu/dma.h"
10 /* PCI includes legacy ISA access. */
11 #include "hw/isa/isa.h"
13 #include "hw/pci/pcie.h"
17 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
18 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
19 #define PCI_FUNC(devfn) ((devfn) & 0x07)
20 #define PCI_SLOT_MAX 32
21 #define PCI_FUNC_MAX 8
23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
24 #include "hw/pci/pci_ids.h"
26 /* QEMU-specific Vendor and Device ID definitions */
29 #define PCI_DEVICE_ID_IBM_440GX 0x027f
30 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
32 /* Hitachi (0x1054) */
33 #define PCI_VENDOR_ID_HITACHI 0x1054
34 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
37 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
41 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
43 /* Realtek (0x10ec) */
44 #define PCI_DEVICE_ID_REALTEK_8029 0x8029
47 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
49 /* Marvell (0x11ab) */
50 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
52 /* QEMU/Bochs VGA (0x1234) */
53 #define PCI_VENDOR_ID_QEMU 0x1234
54 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
57 #define PCI_VENDOR_ID_VMWARE 0x15ad
58 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
59 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
60 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
61 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
62 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0
63 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
64 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
67 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209
68 #define PCI_DEVICE_ID_INTEL_82557 0x1229
69 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922
71 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
72 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
73 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
74 #define PCI_SUBDEVICE_ID_QEMU 0x1100
76 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
77 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
78 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
79 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
80 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004
81 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005
82 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009
84 #define PCI_VENDOR_ID_REDHAT 0x1b36
85 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001
86 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002
87 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003
88 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004
89 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005
90 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100
92 #define FMT_PCIBUS PRIx64
94 typedef void PCIConfigWriteFunc(PCIDevice
*pci_dev
,
95 uint32_t address
, uint32_t data
, int len
);
96 typedef uint32_t PCIConfigReadFunc(PCIDevice
*pci_dev
,
97 uint32_t address
, int len
);
98 typedef void PCIMapIORegionFunc(PCIDevice
*pci_dev
, int region_num
,
99 pcibus_t addr
, pcibus_t size
, int type
);
100 typedef void PCIUnregisterFunc(PCIDevice
*pci_dev
);
102 typedef struct PCIIORegion
{
103 pcibus_t addr
; /* current PCI mapping address. -1 means not mapped */
104 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
107 MemoryRegion
*memory
;
108 MemoryRegion
*address_space
;
111 #define PCI_ROM_SLOT 6
112 #define PCI_NUM_REGIONS 7
118 QEMU_PCI_VGA_NUM_REGIONS
,
121 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
122 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
123 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
124 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
125 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
126 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
128 #include "hw/pci/pci_regs.h"
130 /* PCI HEADER_TYPE */
131 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
133 /* Size of the standard PCI config header */
134 #define PCI_CONFIG_HEADER_SIZE 0x40
135 /* Size of the standard PCI config space */
136 #define PCI_CONFIG_SPACE_SIZE 0x100
137 /* Size of the standart PCIe config space: 4KB */
138 #define PCIE_CONFIG_SPACE_SIZE 0x1000
140 #define PCI_NUM_PINS 4 /* A-D */
142 /* Bits in cap_present field. */
144 QEMU_PCI_CAP_MSI
= 0x1,
145 QEMU_PCI_CAP_MSIX
= 0x2,
146 QEMU_PCI_CAP_EXPRESS
= 0x4,
148 /* multifunction capable device */
149 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
150 QEMU_PCI_CAP_MULTIFUNCTION
= (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR
),
152 /* command register SERR bit enabled */
153 #define QEMU_PCI_CAP_SERR_BITNR 4
154 QEMU_PCI_CAP_SERR
= (1 << QEMU_PCI_CAP_SERR_BITNR
),
155 /* Standard hot plug controller. */
156 #define QEMU_PCI_SHPC_BITNR 5
157 QEMU_PCI_CAP_SHPC
= (1 << QEMU_PCI_SHPC_BITNR
),
158 #define QEMU_PCI_SLOTID_BITNR 6
159 QEMU_PCI_CAP_SLOTID
= (1 << QEMU_PCI_SLOTID_BITNR
),
162 #define TYPE_PCI_DEVICE "pci-device"
163 #define PCI_DEVICE(obj) \
164 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
165 #define PCI_DEVICE_CLASS(klass) \
166 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
167 #define PCI_DEVICE_GET_CLASS(obj) \
168 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
170 typedef struct PCIINTxRoute
{
179 typedef struct PCIDeviceClass
{
180 DeviceClass parent_class
;
182 int (*init
)(PCIDevice
*dev
);
183 PCIUnregisterFunc
*exit
;
184 PCIConfigReadFunc
*config_read
;
185 PCIConfigWriteFunc
*config_write
;
191 uint16_t subsystem_vendor_id
; /* only for header type = 0 */
192 uint16_t subsystem_id
; /* only for header type = 0 */
195 * pci-to-pci bridge or normal device.
196 * This doesn't mean pci host switch.
197 * When card bus bridge is supported, this would be enhanced.
202 int is_express
; /* is this device pci express? */
204 /* device isn't hot-pluggable */
211 typedef void (*PCIINTxRoutingNotifier
)(PCIDevice
*dev
);
212 typedef int (*MSIVectorUseNotifier
)(PCIDevice
*dev
, unsigned int vector
,
214 typedef void (*MSIVectorReleaseNotifier
)(PCIDevice
*dev
, unsigned int vector
);
215 typedef void (*MSIVectorPollNotifier
)(PCIDevice
*dev
,
216 unsigned int vector_start
,
217 unsigned int vector_end
);
222 /* PCI config space */
225 /* Used to enable config checks on load. Note that writable bits are
226 * never checked even if set in cmask. */
229 /* Used to implement R/W bytes */
232 /* Used to implement RW1C(Write 1 to Clear) bytes */
235 /* Used to allocate config space for capabilities. */
238 /* the following fields are read only */
242 PCIIORegion io_regions
[PCI_NUM_REGIONS
];
243 AddressSpace bus_master_as
;
244 MemoryRegion bus_master_enable_region
;
246 /* do not access the following fields */
247 PCIConfigReadFunc
*config_read
;
248 PCIConfigWriteFunc
*config_write
;
250 /* IRQ objects for the INTA-INTD pins. */
253 /* Legacy PCI VGA regions */
254 MemoryRegion
*vga_regions
[QEMU_PCI_VGA_NUM_REGIONS
];
257 /* Current IRQ levels. Used internally by the generic PCI code. */
260 /* Capability bits */
261 uint32_t cap_present
;
263 /* Offset of MSI-X capability in config space */
269 /* Space to store MSIX table & pending bit array */
272 /* MemoryRegion container for msix exclusive BAR setup */
273 MemoryRegion msix_exclusive_bar
;
274 /* Memory Regions for MSIX table and pending bit entries. */
275 MemoryRegion msix_table_mmio
;
276 MemoryRegion msix_pba_mmio
;
277 /* Reference-count for entries actually in use by driver. */
278 unsigned *msix_entry_used
;
279 /* MSIX function mask set or MSIX disabled */
280 bool msix_function_masked
;
281 /* Version id needed for VMState */
284 /* Offset of MSI capability in config space */
288 PCIExpressDevice exp
;
293 /* Location of option rom */
299 /* INTx routing notifier */
300 PCIINTxRoutingNotifier intx_routing_notifier
;
302 /* MSI-X notifiers */
303 MSIVectorUseNotifier msix_vector_use_notifier
;
304 MSIVectorReleaseNotifier msix_vector_release_notifier
;
305 MSIVectorPollNotifier msix_vector_poll_notifier
;
308 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
309 uint8_t attr
, MemoryRegion
*memory
);
310 void pci_register_vga(PCIDevice
*pci_dev
, MemoryRegion
*mem
,
311 MemoryRegion
*io_lo
, MemoryRegion
*io_hi
);
312 void pci_unregister_vga(PCIDevice
*pci_dev
);
313 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
);
315 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
316 uint8_t offset
, uint8_t size
);
318 void pci_del_capability(PCIDevice
*pci_dev
, uint8_t cap_id
, uint8_t cap_size
);
320 uint8_t pci_find_capability(PCIDevice
*pci_dev
, uint8_t cap_id
);
323 uint32_t pci_default_read_config(PCIDevice
*d
,
324 uint32_t address
, int len
);
325 void pci_default_write_config(PCIDevice
*d
,
326 uint32_t address
, uint32_t val
, int len
);
327 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
);
328 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
);
329 MemoryRegion
*pci_address_space(PCIDevice
*dev
);
330 MemoryRegion
*pci_address_space_io(PCIDevice
*dev
);
332 typedef void (*pci_set_irq_fn
)(void *opaque
, int irq_num
, int level
);
333 typedef int (*pci_map_irq_fn
)(PCIDevice
*pci_dev
, int irq_num
);
334 typedef PCIINTxRoute (*pci_route_irq_fn
)(void *opaque
, int pin
);
337 PCI_HOTPLUG_DISABLED
,
339 PCI_COLDPLUG_ENABLED
,
342 typedef int (*pci_hotplug_fn
)(DeviceState
*qdev
, PCIDevice
*pci_dev
,
343 PCIHotplugState state
);
345 #define TYPE_PCI_BUS "PCI"
346 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
347 #define TYPE_PCIE_BUS "PCIE"
349 bool pci_bus_is_express(PCIBus
*bus
);
350 bool pci_bus_is_root(PCIBus
*bus
);
351 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
353 MemoryRegion
*address_space_mem
,
354 MemoryRegion
*address_space_io
,
355 uint8_t devfn_min
, const char *typename
);
356 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
,
357 MemoryRegion
*address_space_mem
,
358 MemoryRegion
*address_space_io
,
359 uint8_t devfn_min
, const char *typename
);
360 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
361 void *irq_opaque
, int nirq
);
362 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
);
363 void pci_bus_hotplug(PCIBus
*bus
, pci_hotplug_fn hotplug
, DeviceState
*dev
);
364 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
365 int pci_swizzle_map_irq_fn(PCIDevice
*pci_dev
, int pin
);
366 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
367 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
369 MemoryRegion
*address_space_mem
,
370 MemoryRegion
*address_space_io
,
371 uint8_t devfn_min
, int nirq
, const char *typename
);
372 void pci_bus_set_route_irq_fn(PCIBus
*, pci_route_irq_fn
);
373 PCIINTxRoute
pci_device_route_intx_to_irq(PCIDevice
*dev
, int pin
);
374 bool pci_intx_route_changed(PCIINTxRoute
*old
, PCIINTxRoute
*new);
375 void pci_bus_fire_intx_routing_notifier(PCIBus
*bus
);
376 void pci_device_set_intx_routing_notifier(PCIDevice
*dev
,
377 PCIINTxRoutingNotifier notifier
);
378 void pci_device_reset(PCIDevice
*dev
);
379 void pci_bus_reset(PCIBus
*bus
);
381 PCIDevice
*pci_nic_init(NICInfo
*nd
, PCIBus
*rootbus
,
382 const char *default_model
,
383 const char *default_devaddr
);
384 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, PCIBus
*rootbus
,
385 const char *default_model
,
386 const char *default_devaddr
);
388 PCIDevice
*pci_vga_init(PCIBus
*bus
);
390 int pci_bus_num(PCIBus
*s
);
391 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
392 void (*fn
)(PCIBus
*bus
, PCIDevice
*d
, void *opaque
),
394 PCIBus
*pci_find_primary_bus(void);
395 PCIBus
*pci_device_root_bus(const PCIDevice
*d
);
396 const char *pci_root_bus_path(PCIDevice
*dev
);
397 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
);
398 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
);
399 PCIBus
*pci_get_bus_devfn(int *devfnp
, PCIBus
*root
, const char *devaddr
);
401 int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
,
402 unsigned int *slotp
, unsigned int *funcp
);
404 void pci_device_deassert_intx(PCIDevice
*dev
);
406 typedef AddressSpace
*(*PCIIOMMUFunc
)(PCIBus
*, void *, int);
408 void pci_setup_iommu(PCIBus
*bus
, PCIIOMMUFunc fn
, void *opaque
);
411 pci_set_byte(uint8_t *config
, uint8_t val
)
416 static inline uint8_t
417 pci_get_byte(const uint8_t *config
)
423 pci_set_word(uint8_t *config
, uint16_t val
)
425 cpu_to_le16wu((uint16_t *)config
, val
);
428 static inline uint16_t
429 pci_get_word(const uint8_t *config
)
431 return le16_to_cpupu((const uint16_t *)config
);
435 pci_set_long(uint8_t *config
, uint32_t val
)
437 cpu_to_le32wu((uint32_t *)config
, val
);
440 static inline uint32_t
441 pci_get_long(const uint8_t *config
)
443 return le32_to_cpupu((const uint32_t *)config
);
447 pci_set_quad(uint8_t *config
, uint64_t val
)
449 cpu_to_le64w((uint64_t *)config
, val
);
452 static inline uint64_t
453 pci_get_quad(const uint8_t *config
)
455 return le64_to_cpup((const uint64_t *)config
);
459 pci_config_set_vendor_id(uint8_t *pci_config
, uint16_t val
)
461 pci_set_word(&pci_config
[PCI_VENDOR_ID
], val
);
465 pci_config_set_device_id(uint8_t *pci_config
, uint16_t val
)
467 pci_set_word(&pci_config
[PCI_DEVICE_ID
], val
);
471 pci_config_set_revision(uint8_t *pci_config
, uint8_t val
)
473 pci_set_byte(&pci_config
[PCI_REVISION_ID
], val
);
477 pci_config_set_class(uint8_t *pci_config
, uint16_t val
)
479 pci_set_word(&pci_config
[PCI_CLASS_DEVICE
], val
);
483 pci_config_set_prog_interface(uint8_t *pci_config
, uint8_t val
)
485 pci_set_byte(&pci_config
[PCI_CLASS_PROG
], val
);
489 pci_config_set_interrupt_pin(uint8_t *pci_config
, uint8_t val
)
491 pci_set_byte(&pci_config
[PCI_INTERRUPT_PIN
], val
);
495 * helper functions to do bit mask operation on configuration space.
496 * Just to set bit, use test-and-set and discard returned value.
497 * Just to clear bit, use test-and-clear and discard returned value.
498 * NOTE: They aren't atomic.
500 static inline uint8_t
501 pci_byte_test_and_clear_mask(uint8_t *config
, uint8_t mask
)
503 uint8_t val
= pci_get_byte(config
);
504 pci_set_byte(config
, val
& ~mask
);
508 static inline uint8_t
509 pci_byte_test_and_set_mask(uint8_t *config
, uint8_t mask
)
511 uint8_t val
= pci_get_byte(config
);
512 pci_set_byte(config
, val
| mask
);
516 static inline uint16_t
517 pci_word_test_and_clear_mask(uint8_t *config
, uint16_t mask
)
519 uint16_t val
= pci_get_word(config
);
520 pci_set_word(config
, val
& ~mask
);
524 static inline uint16_t
525 pci_word_test_and_set_mask(uint8_t *config
, uint16_t mask
)
527 uint16_t val
= pci_get_word(config
);
528 pci_set_word(config
, val
| mask
);
532 static inline uint32_t
533 pci_long_test_and_clear_mask(uint8_t *config
, uint32_t mask
)
535 uint32_t val
= pci_get_long(config
);
536 pci_set_long(config
, val
& ~mask
);
540 static inline uint32_t
541 pci_long_test_and_set_mask(uint8_t *config
, uint32_t mask
)
543 uint32_t val
= pci_get_long(config
);
544 pci_set_long(config
, val
| mask
);
548 static inline uint64_t
549 pci_quad_test_and_clear_mask(uint8_t *config
, uint64_t mask
)
551 uint64_t val
= pci_get_quad(config
);
552 pci_set_quad(config
, val
& ~mask
);
556 static inline uint64_t
557 pci_quad_test_and_set_mask(uint8_t *config
, uint64_t mask
)
559 uint64_t val
= pci_get_quad(config
);
560 pci_set_quad(config
, val
| mask
);
564 /* Access a register specified by a mask */
566 pci_set_byte_by_mask(uint8_t *config
, uint8_t mask
, uint8_t reg
)
568 uint8_t val
= pci_get_byte(config
);
569 uint8_t rval
= reg
<< (ffs(mask
) - 1);
570 pci_set_byte(config
, (~mask
& val
) | (mask
& rval
));
573 static inline uint8_t
574 pci_get_byte_by_mask(uint8_t *config
, uint8_t mask
)
576 uint8_t val
= pci_get_byte(config
);
577 return (val
& mask
) >> (ffs(mask
) - 1);
581 pci_set_word_by_mask(uint8_t *config
, uint16_t mask
, uint16_t reg
)
583 uint16_t val
= pci_get_word(config
);
584 uint16_t rval
= reg
<< (ffs(mask
) - 1);
585 pci_set_word(config
, (~mask
& val
) | (mask
& rval
));
588 static inline uint16_t
589 pci_get_word_by_mask(uint8_t *config
, uint16_t mask
)
591 uint16_t val
= pci_get_word(config
);
592 return (val
& mask
) >> (ffs(mask
) - 1);
596 pci_set_long_by_mask(uint8_t *config
, uint32_t mask
, uint32_t reg
)
598 uint32_t val
= pci_get_long(config
);
599 uint32_t rval
= reg
<< (ffs(mask
) - 1);
600 pci_set_long(config
, (~mask
& val
) | (mask
& rval
));
603 static inline uint32_t
604 pci_get_long_by_mask(uint8_t *config
, uint32_t mask
)
606 uint32_t val
= pci_get_long(config
);
607 return (val
& mask
) >> (ffs(mask
) - 1);
611 pci_set_quad_by_mask(uint8_t *config
, uint64_t mask
, uint64_t reg
)
613 uint64_t val
= pci_get_quad(config
);
614 uint64_t rval
= reg
<< (ffs(mask
) - 1);
615 pci_set_quad(config
, (~mask
& val
) | (mask
& rval
));
618 static inline uint64_t
619 pci_get_quad_by_mask(uint8_t *config
, uint64_t mask
)
621 uint64_t val
= pci_get_quad(config
);
622 return (val
& mask
) >> (ffs(mask
) - 1);
625 PCIDevice
*pci_create_multifunction(PCIBus
*bus
, int devfn
, bool multifunction
,
627 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
630 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
);
631 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
);
633 static inline int pci_is_express(const PCIDevice
*d
)
635 return d
->cap_present
& QEMU_PCI_CAP_EXPRESS
;
638 static inline uint32_t pci_config_size(const PCIDevice
*d
)
640 return pci_is_express(d
) ? PCIE_CONFIG_SPACE_SIZE
: PCI_CONFIG_SPACE_SIZE
;
643 /* DMA access functions */
644 static inline AddressSpace
*pci_get_address_space(PCIDevice
*dev
)
646 return &dev
->bus_master_as
;
649 static inline int pci_dma_rw(PCIDevice
*dev
, dma_addr_t addr
,
650 void *buf
, dma_addr_t len
, DMADirection dir
)
652 dma_memory_rw(pci_get_address_space(dev
), addr
, buf
, len
, dir
);
656 static inline int pci_dma_read(PCIDevice
*dev
, dma_addr_t addr
,
657 void *buf
, dma_addr_t len
)
659 return pci_dma_rw(dev
, addr
, buf
, len
, DMA_DIRECTION_TO_DEVICE
);
662 static inline int pci_dma_write(PCIDevice
*dev
, dma_addr_t addr
,
663 const void *buf
, dma_addr_t len
)
665 return pci_dma_rw(dev
, addr
, (void *) buf
, len
, DMA_DIRECTION_FROM_DEVICE
);
668 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
669 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \
672 return ld##_l##_dma(pci_get_address_space(dev), addr); \
674 static inline void st##_s##_pci_dma(PCIDevice *dev, \
675 dma_addr_t addr, uint##_bits##_t val) \
677 st##_s##_dma(pci_get_address_space(dev), addr, val); \
680 PCI_DMA_DEFINE_LDST(ub
, b
, 8);
681 PCI_DMA_DEFINE_LDST(uw_le
, w_le
, 16)
682 PCI_DMA_DEFINE_LDST(l_le
, l_le
, 32);
683 PCI_DMA_DEFINE_LDST(q_le
, q_le
, 64);
684 PCI_DMA_DEFINE_LDST(uw_be
, w_be
, 16)
685 PCI_DMA_DEFINE_LDST(l_be
, l_be
, 32);
686 PCI_DMA_DEFINE_LDST(q_be
, q_be
, 64);
688 #undef PCI_DMA_DEFINE_LDST
690 static inline void *pci_dma_map(PCIDevice
*dev
, dma_addr_t addr
,
691 dma_addr_t
*plen
, DMADirection dir
)
695 buf
= dma_memory_map(pci_get_address_space(dev
), addr
, plen
, dir
);
699 static inline void pci_dma_unmap(PCIDevice
*dev
, void *buffer
, dma_addr_t len
,
700 DMADirection dir
, dma_addr_t access_len
)
702 dma_memory_unmap(pci_get_address_space(dev
), buffer
, len
, dir
, access_len
);
705 static inline void pci_dma_sglist_init(QEMUSGList
*qsg
, PCIDevice
*dev
,
708 qemu_sglist_init(qsg
, DEVICE(dev
), alloc_hint
, pci_get_address_space(dev
));
711 extern const VMStateDescription vmstate_pci_device
;
713 #define VMSTATE_PCI_DEVICE(_field, _state) { \
714 .name = (stringify(_field)), \
715 .size = sizeof(PCIDevice), \
716 .vmsd = &vmstate_pci_device, \
717 .flags = VMS_STRUCT, \
718 .offset = vmstate_offset_value(_state, _field, PCIDevice), \
721 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
722 .name = (stringify(_field)), \
723 .size = sizeof(PCIDevice), \
724 .vmsd = &vmstate_pci_device, \
725 .flags = VMS_STRUCT|VMS_POINTER, \
726 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \