tcg/tcg.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef TCG_H
  26 #define TCG_H
  27
  28 #include "qemu-common.h"
  29 #include "cpu.h"
  30 #include "exec/tb-context.h"
  31 #include "qemu/bitops.h"
  32 #include "qemu/queue.h"
  33 #include "tcg-mo.h"
  34 #include "tcg-target.h"
  35
  36 /* XXX: make safe guess about sizes */
  37 #define MAX_OP_PER_INSTR 266
  38
  39 #if HOST_LONG_BITS == 32
  40 #define MAX_OPC_PARAM_PER_ARG 2
  41 #else
  42 #define MAX_OPC_PARAM_PER_ARG 1
  43 #endif
  44 #define MAX_OPC_PARAM_IARGS 6
  45 #define MAX_OPC_PARAM_OARGS 1
  46 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  47
  48 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  49  * and up to 4 + N parameters on 64-bit archs
  50  * (N = number of input arguments + output arguments).  */
  51 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  52
  53 #define CPU_TEMP_BUF_NLONGS 128
  54
  55 /* Default target word size to pointer size.  */
  56 #ifndef TCG_TARGET_REG_BITS
  57 # if UINTPTR_MAX == UINT32_MAX
  58 #  define TCG_TARGET_REG_BITS 32
  59 # elif UINTPTR_MAX == UINT64_MAX
  60 #  define TCG_TARGET_REG_BITS 64
  61 # else
  62 #  error Unknown pointer size for tcg target
  63 # endif
  64 #endif
  65
  66 #if TCG_TARGET_REG_BITS == 32
  67 typedef int32_t tcg_target_long;
  68 typedef uint32_t tcg_target_ulong;
  69 #define TCG_PRIlx PRIx32
  70 #define TCG_PRIld PRId32
  71 #elif TCG_TARGET_REG_BITS == 64
  72 typedef int64_t tcg_target_long;
  73 typedef uint64_t tcg_target_ulong;
  74 #define TCG_PRIlx PRIx64
  75 #define TCG_PRIld PRId64
  76 #else
  77 #error unsupported
  78 #endif
  79
  80 /* Oversized TCG guests make things like MTTCG hard
  81  * as we can't use atomics for cputlb updates.
  82  */
  83 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
  84 #define TCG_OVERSIZED_GUEST 1
  85 #else
  86 #define TCG_OVERSIZED_GUEST 0
  87 #endif
  88
  89 #if TCG_TARGET_NB_REGS <= 32
  90 typedef uint32_t TCGRegSet;
  91 #elif TCG_TARGET_NB_REGS <= 64
  92 typedef uint64_t TCGRegSet;
  93 #else
  94 #error unsupported
  95 #endif
  96
  97 #if TCG_TARGET_REG_BITS == 32
  98 /* Turn some undef macros into false macros.  */
  99 #define TCG_TARGET_HAS_extrl_i64_i32    0
 100 #define TCG_TARGET_HAS_extrh_i64_i32    0
 101 #define TCG_TARGET_HAS_div_i64          0
 102 #define TCG_TARGET_HAS_rem_i64          0
 103 #define TCG_TARGET_HAS_div2_i64         0
 104 #define TCG_TARGET_HAS_rot_i64          0
 105 #define TCG_TARGET_HAS_ext8s_i64        0
 106 #define TCG_TARGET_HAS_ext16s_i64       0
 107 #define TCG_TARGET_HAS_ext32s_i64       0
 108 #define TCG_TARGET_HAS_ext8u_i64        0
 109 #define TCG_TARGET_HAS_ext16u_i64       0
 110 #define TCG_TARGET_HAS_ext32u_i64       0
 111 #define TCG_TARGET_HAS_bswap16_i64      0
 112 #define TCG_TARGET_HAS_bswap32_i64      0
 113 #define TCG_TARGET_HAS_bswap64_i64      0
 114 #define TCG_TARGET_HAS_neg_i64          0
 115 #define TCG_TARGET_HAS_not_i64          0
 116 #define TCG_TARGET_HAS_andc_i64         0
 117 #define TCG_TARGET_HAS_orc_i64          0
 118 #define TCG_TARGET_HAS_eqv_i64          0
 119 #define TCG_TARGET_HAS_nand_i64         0
 120 #define TCG_TARGET_HAS_nor_i64          0
 121 #define TCG_TARGET_HAS_clz_i64          0
 122 #define TCG_TARGET_HAS_ctz_i64          0
 123 #define TCG_TARGET_HAS_ctpop_i64        0
 124 #define TCG_TARGET_HAS_deposit_i64      0
 125 #define TCG_TARGET_HAS_extract_i64      0
 126 #define TCG_TARGET_HAS_sextract_i64     0
 127 #define TCG_TARGET_HAS_movcond_i64      0
 128 #define TCG_TARGET_HAS_add2_i64         0
 129 #define TCG_TARGET_HAS_sub2_i64         0
 130 #define TCG_TARGET_HAS_mulu2_i64        0
 131 #define TCG_TARGET_HAS_muls2_i64        0
 132 #define TCG_TARGET_HAS_muluh_i64        0
 133 #define TCG_TARGET_HAS_mulsh_i64        0
 134 /* Turn some undef macros into true macros.  */
 135 #define TCG_TARGET_HAS_add2_i32         1
 136 #define TCG_TARGET_HAS_sub2_i32         1
 137 #endif
 138
 139 #ifndef TCG_TARGET_deposit_i32_valid
 140 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1
 141 #endif
 142 #ifndef TCG_TARGET_deposit_i64_valid
 143 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1
 144 #endif
 145 #ifndef TCG_TARGET_extract_i32_valid
 146 #define TCG_TARGET_extract_i32_valid(ofs, len) 1
 147 #endif
 148 #ifndef TCG_TARGET_extract_i64_valid
 149 #define TCG_TARGET_extract_i64_valid(ofs, len) 1
 150 #endif
 151
 152 /* Only one of DIV or DIV2 should be defined.  */
 153 #if defined(TCG_TARGET_HAS_div_i32)
 154 #define TCG_TARGET_HAS_div2_i32         0
 155 #elif defined(TCG_TARGET_HAS_div2_i32)
 156 #define TCG_TARGET_HAS_div_i32          0
 157 #define TCG_TARGET_HAS_rem_i32          0
 158 #endif
 159 #if defined(TCG_TARGET_HAS_div_i64)
 160 #define TCG_TARGET_HAS_div2_i64         0
 161 #elif defined(TCG_TARGET_HAS_div2_i64)
 162 #define TCG_TARGET_HAS_div_i64          0
 163 #define TCG_TARGET_HAS_rem_i64          0
 164 #endif
 165
 166 /* For 32-bit targets, some sort of unsigned widening multiply is required.  */
 167 #if TCG_TARGET_REG_BITS == 32 \
 168     && !(defined(TCG_TARGET_HAS_mulu2_i32) \
 169          || defined(TCG_TARGET_HAS_muluh_i32))
 170 # error "Missing unsigned widening multiply"
 171 #endif
 172
 173 #if !defined(TCG_TARGET_HAS_v64) \
 174     && !defined(TCG_TARGET_HAS_v128) \
 175     && !defined(TCG_TARGET_HAS_v256)
 176 #define TCG_TARGET_MAYBE_vec            0
 177 #define TCG_TARGET_HAS_neg_vec          0
 178 #define TCG_TARGET_HAS_not_vec          0
 179 #define TCG_TARGET_HAS_andc_vec         0
 180 #define TCG_TARGET_HAS_orc_vec          0
 181 #else
 182 #define TCG_TARGET_MAYBE_vec            1
 183 #endif
 184 #ifndef TCG_TARGET_HAS_v64
 185 #define TCG_TARGET_HAS_v64              0
 186 #endif
 187 #ifndef TCG_TARGET_HAS_v128
 188 #define TCG_TARGET_HAS_v128             0
 189 #endif
 190 #ifndef TCG_TARGET_HAS_v256
 191 #define TCG_TARGET_HAS_v256             0
 192 #endif
 193
 194 #ifndef TARGET_INSN_START_EXTRA_WORDS
 195 # define TARGET_INSN_START_WORDS 1
 196 #else
 197 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
 198 #endif
 199
 200 typedef enum TCGOpcode {
 201 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
 202 #include "tcg-opc.h"
 203 #undef DEF
 204     NB_OPS,
 205 } TCGOpcode;
 206
 207 #define tcg_regset_set_reg(d, r)   ((d) |= (TCGRegSet)1 << (r))
 208 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r)))
 209 #define tcg_regset_test_reg(d, r)  (((d) >> (r)) & 1)
 210
 211 #ifndef TCG_TARGET_INSN_UNIT_SIZE
 212 # error "Missing TCG_TARGET_INSN_UNIT_SIZE"
 213 #elif TCG_TARGET_INSN_UNIT_SIZE == 1
 214 typedef uint8_t tcg_insn_unit;
 215 #elif TCG_TARGET_INSN_UNIT_SIZE == 2
 216 typedef uint16_t tcg_insn_unit;
 217 #elif TCG_TARGET_INSN_UNIT_SIZE == 4
 218 typedef uint32_t tcg_insn_unit;
 219 #elif TCG_TARGET_INSN_UNIT_SIZE == 8
 220 typedef uint64_t tcg_insn_unit;
 221 #else
 222 /* The port better have done this.  */
 223 #endif
 224
 225
 226 #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS
 227 # define tcg_debug_assert(X) do { assert(X); } while (0)
 228 #elif QEMU_GNUC_PREREQ(4, 5)
 229 # define tcg_debug_assert(X) \
 230     do { if (!(X)) { __builtin_unreachable(); } } while (0)
 231 #else
 232 # define tcg_debug_assert(X) do { (void)(X); } while (0)
 233 #endif
 234
 235 typedef struct TCGRelocation {
 236     struct TCGRelocation *next;
 237     int type;
 238     tcg_insn_unit *ptr;
 239     intptr_t addend;
 240 } TCGRelocation;
 241
 242 typedef struct TCGLabel {
 243     unsigned has_value : 1;
 244     unsigned id : 31;
 245     union {
 246         uintptr_t value;
 247         tcg_insn_unit *value_ptr;
 248         TCGRelocation *first_reloc;
 249     } u;
 250 } TCGLabel;
 251
 252 typedef struct TCGPool {
 253     struct TCGPool *next;
 254     int size;
 255     uint8_t data[0] __attribute__ ((aligned));
 256 } TCGPool;
 257
 258 #define TCG_POOL_CHUNK_SIZE 32768
 259
 260 #define TCG_MAX_TEMPS 512
 261 #define TCG_MAX_INSNS 512
 262
 263 /* when the size of the arguments of a called function is smaller than
 264    this value, they are statically allocated in the TB stack frame */
 265 #define TCG_STATIC_CALL_ARGS_SIZE 128
 266
 267 typedef enum TCGType {
 268     TCG_TYPE_I32,
 269     TCG_TYPE_I64,
 270
 271     TCG_TYPE_V64,
 272     TCG_TYPE_V128,
 273     TCG_TYPE_V256,
 274
 275     TCG_TYPE_COUNT, /* number of different types */
 276
 277     /* An alias for the size of the host register.  */
 278 #if TCG_TARGET_REG_BITS == 32
 279     TCG_TYPE_REG = TCG_TYPE_I32,
 280 #else
 281     TCG_TYPE_REG = TCG_TYPE_I64,
 282 #endif
 283
 284     /* An alias for the size of the native pointer.  */
 285 #if UINTPTR_MAX == UINT32_MAX
 286     TCG_TYPE_PTR = TCG_TYPE_I32,
 287 #else
 288     TCG_TYPE_PTR = TCG_TYPE_I64,
 289 #endif
 290
 291     /* An alias for the size of the target "long", aka register.  */
 292 #if TARGET_LONG_BITS == 64
 293     TCG_TYPE_TL = TCG_TYPE_I64,
 294 #else
 295     TCG_TYPE_TL = TCG_TYPE_I32,
 296 #endif
 297 } TCGType;
 298
 299 /* Constants for qemu_ld and qemu_st for the Memory Operation field.  */
 300 typedef enum TCGMemOp {
 301     MO_8     = 0,
 302     MO_16    = 1,
 303     MO_32    = 2,
 304     MO_64    = 3,
 305     MO_SIZE  = 3,   /* Mask for the above.  */
 306
 307     MO_SIGN  = 4,   /* Sign-extended, otherwise zero-extended.  */
 308
 309     MO_BSWAP = 8,   /* Host reverse endian.  */
 310 #ifdef HOST_WORDS_BIGENDIAN
 311     MO_LE    = MO_BSWAP,
 312     MO_BE    = 0,
 313 #else
 314     MO_LE    = 0,
 315     MO_BE    = MO_BSWAP,
 316 #endif
 317 #ifdef TARGET_WORDS_BIGENDIAN
 318     MO_TE    = MO_BE,
 319 #else
 320     MO_TE    = MO_LE,
 321 #endif
 322
 323     /* MO_UNALN accesses are never checked for alignment.
 324      * MO_ALIGN accesses will result in a call to the CPU's
 325      * do_unaligned_access hook if the guest address is not aligned.
 326      * The default depends on whether the target CPU defines ALIGNED_ONLY.
 327      *
 328      * Some architectures (e.g. ARMv8) need the address which is aligned
 329      * to a size more than the size of the memory access.
 330      * Some architectures (e.g. SPARCv9) need an address which is aligned,
 331      * but less strictly than the natural alignment.
 332      *
 333      * MO_ALIGN supposes the alignment size is the size of a memory access.
 334      *
 335      * There are three options:
 336      * - unaligned access permitted (MO_UNALN).
 337      * - an alignment to the size of an access (MO_ALIGN);
 338      * - an alignment to a specified size, which may be more or less than
 339      *   the access size (MO_ALIGN_x where 'x' is a size in bytes);
 340      */
 341     MO_ASHIFT = 4,
 342     MO_AMASK = 7 << MO_ASHIFT,
 343 #ifdef ALIGNED_ONLY
 344     MO_ALIGN = 0,
 345     MO_UNALN = MO_AMASK,
 346 #else
 347     MO_ALIGN = MO_AMASK,
 348     MO_UNALN = 0,
 349 #endif
 350     MO_ALIGN_2  = 1 << MO_ASHIFT,
 351     MO_ALIGN_4  = 2 << MO_ASHIFT,
 352     MO_ALIGN_8  = 3 << MO_ASHIFT,
 353     MO_ALIGN_16 = 4 << MO_ASHIFT,
 354     MO_ALIGN_32 = 5 << MO_ASHIFT,
 355     MO_ALIGN_64 = 6 << MO_ASHIFT,
 356
 357     /* Combinations of the above, for ease of use.  */
 358     MO_UB    = MO_8,
 359     MO_UW    = MO_16,
 360     MO_UL    = MO_32,
 361     MO_SB    = MO_SIGN | MO_8,
 362     MO_SW    = MO_SIGN | MO_16,
 363     MO_SL    = MO_SIGN | MO_32,
 364     MO_Q     = MO_64,
 365
 366     MO_LEUW  = MO_LE | MO_UW,
 367     MO_LEUL  = MO_LE | MO_UL,
 368     MO_LESW  = MO_LE | MO_SW,
 369     MO_LESL  = MO_LE | MO_SL,
 370     MO_LEQ   = MO_LE | MO_Q,
 371
 372     MO_BEUW  = MO_BE | MO_UW,
 373     MO_BEUL  = MO_BE | MO_UL,
 374     MO_BESW  = MO_BE | MO_SW,
 375     MO_BESL  = MO_BE | MO_SL,
 376     MO_BEQ   = MO_BE | MO_Q,
 377
 378     MO_TEUW  = MO_TE | MO_UW,
 379     MO_TEUL  = MO_TE | MO_UL,
 380     MO_TESW  = MO_TE | MO_SW,
 381     MO_TESL  = MO_TE | MO_SL,
 382     MO_TEQ   = MO_TE | MO_Q,
 383
 384     MO_SSIZE = MO_SIZE | MO_SIGN,
 385 } TCGMemOp;
 386
 387 /**
 388  * get_alignment_bits
 389  * @memop: TCGMemOp value
 390  *
 391  * Extract the alignment size from the memop.
 392  */
 393 static inline unsigned get_alignment_bits(TCGMemOp memop)
 394 {
 395     unsigned a = memop & MO_AMASK;
 396
 397     if (a == MO_UNALN) {
 398         /* No alignment required.  */
 399         a = 0;
 400     } else if (a == MO_ALIGN) {
 401         /* A natural alignment requirement.  */
 402         a = memop & MO_SIZE;
 403     } else {
 404         /* A specific alignment requirement.  */
 405         a = a >> MO_ASHIFT;
 406     }
 407 #if defined(CONFIG_SOFTMMU)
 408     /* The requested alignment cannot overlap the TLB flags.  */
 409     tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0);
 410 #endif
 411     return a;
 412 }
 413
 414 typedef tcg_target_ulong TCGArg;
 415
 416 /* Define type and accessor macros for TCG variables.
 417
 418    TCG variables are the inputs and outputs of TCG ops, as described
 419    in tcg/README. Target CPU front-end code uses these types to deal
 420    with TCG variables as it emits TCG code via the tcg_gen_* functions.
 421    They come in several flavours:
 422     * TCGv_i32 : 32 bit integer type
 423     * TCGv_i64 : 64 bit integer type
 424     * TCGv_ptr : a host pointer type
 425     * TCGv_vec : a host vector type; the exact size is not exposed
 426                  to the CPU front-end code.
 427     * TCGv : an integer type the same size as target_ulong
 428              (an alias for either TCGv_i32 or TCGv_i64)
 429    The compiler's type checking will complain if you mix them
 430    up and pass the wrong sized TCGv to a function.
 431
 432    Users of tcg_gen_* don't need to know about any of the internal
 433    details of these, and should treat them as opaque types.
 434    You won't be able to look inside them in a debugger either.
 435
 436    Internal implementation details follow:
 437
 438    Note that there is no definition of the structs TCGv_i32_d etc anywhere.
 439    This is deliberate, because the values we store in variables of type
 440    TCGv_i32 are not really pointers-to-structures. They're just small
 441    integers, but keeping them in pointer types like this means that the
 442    compiler will complain if you accidentally pass a TCGv_i32 to a
 443    function which takes a TCGv_i64, and so on. Only the internals of
 444    TCG need to care about the actual contents of the types.  */
 445
 446 typedef struct TCGv_i32_d *TCGv_i32;
 447 typedef struct TCGv_i64_d *TCGv_i64;
 448 typedef struct TCGv_ptr_d *TCGv_ptr;
 449 typedef struct TCGv_vec_d *TCGv_vec;
 450 typedef TCGv_ptr TCGv_env;
 451 #if TARGET_LONG_BITS == 32
 452 #define TCGv TCGv_i32
 453 #elif TARGET_LONG_BITS == 64
 454 #define TCGv TCGv_i64
 455 #else
 456 #error Unhandled TARGET_LONG_BITS value
 457 #endif
 458
 459 /* call flags */
 460 /* Helper does not read globals (either directly or through an exception). It
 461    implies TCG_CALL_NO_WRITE_GLOBALS. */
 462 #define TCG_CALL_NO_READ_GLOBALS    0x0010
 463 /* Helper does not write globals */
 464 #define TCG_CALL_NO_WRITE_GLOBALS   0x0020
 465 /* Helper can be safely suppressed if the return value is not used. */
 466 #define TCG_CALL_NO_SIDE_EFFECTS    0x0040
 467
 468 /* convenience version of most used call flags */
 469 #define TCG_CALL_NO_RWG         TCG_CALL_NO_READ_GLOBALS
 470 #define TCG_CALL_NO_WG          TCG_CALL_NO_WRITE_GLOBALS
 471 #define TCG_CALL_NO_SE          TCG_CALL_NO_SIDE_EFFECTS
 472 #define TCG_CALL_NO_RWG_SE      (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
 473 #define TCG_CALL_NO_WG_SE       (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
 474
 475 /* Used to align parameters.  See the comment before tcgv_i32_temp.  */
 476 #define TCG_CALL_DUMMY_ARG      ((TCGArg)0)
 477
 478 /* Conditions.  Note that these are laid out for easy manipulation by
 479    the functions below:
 480      bit 0 is used for inverting;
 481      bit 1 is signed,
 482      bit 2 is unsigned,
 483      bit 3 is used with bit 0 for swapping signed/unsigned.  */
 484 typedef enum {
 485     /* non-signed */
 486     TCG_COND_NEVER  = 0 | 0 | 0 | 0,
 487     TCG_COND_ALWAYS = 0 | 0 | 0 | 1,
 488     TCG_COND_EQ     = 8 | 0 | 0 | 0,
 489     TCG_COND_NE     = 8 | 0 | 0 | 1,
 490     /* signed */
 491     TCG_COND_LT     = 0 | 0 | 2 | 0,
 492     TCG_COND_GE     = 0 | 0 | 2 | 1,
 493     TCG_COND_LE     = 8 | 0 | 2 | 0,
 494     TCG_COND_GT     = 8 | 0 | 2 | 1,
 495     /* unsigned */
 496     TCG_COND_LTU    = 0 | 4 | 0 | 0,
 497     TCG_COND_GEU    = 0 | 4 | 0 | 1,
 498     TCG_COND_LEU    = 8 | 4 | 0 | 0,
 499     TCG_COND_GTU    = 8 | 4 | 0 | 1,
 500 } TCGCond;
 501
 502 /* Invert the sense of the comparison.  */
 503 static inline TCGCond tcg_invert_cond(TCGCond c)
 504 {
 505     return (TCGCond)(c ^ 1);
 506 }
 507
 508 /* Swap the operands in a comparison.  */
 509 static inline TCGCond tcg_swap_cond(TCGCond c)
 510 {
 511     return c & 6 ? (TCGCond)(c ^ 9) : c;
 512 }
 513
 514 /* Create an "unsigned" version of a "signed" comparison.  */
 515 static inline TCGCond tcg_unsigned_cond(TCGCond c)
 516 {
 517     return c & 2 ? (TCGCond)(c ^ 6) : c;
 518 }
 519
 520 /* Create a "signed" version of an "unsigned" comparison.  */
 521 static inline TCGCond tcg_signed_cond(TCGCond c)
 522 {
 523     return c & 4 ? (TCGCond)(c ^ 6) : c;
 524 }
 525
 526 /* Must a comparison be considered unsigned?  */
 527 static inline bool is_unsigned_cond(TCGCond c)
 528 {
 529     return (c & 4) != 0;
 530 }
 531
 532 /* Create a "high" version of a double-word comparison.
 533    This removes equality from a LTE or GTE comparison.  */
 534 static inline TCGCond tcg_high_cond(TCGCond c)
 535 {
 536     switch (c) {
 537     case TCG_COND_GE:
 538     case TCG_COND_LE:
 539     case TCG_COND_GEU:
 540     case TCG_COND_LEU:
 541         return (TCGCond)(c ^ 8);
 542     default:
 543         return c;
 544     }
 545 }
 546
 547 typedef enum TCGTempVal {
 548     TEMP_VAL_DEAD,
 549     TEMP_VAL_REG,
 550     TEMP_VAL_MEM,
 551     TEMP_VAL_CONST,
 552 } TCGTempVal;
 553
 554 typedef struct TCGTemp {
 555     TCGReg reg:8;
 556     TCGTempVal val_type:8;
 557     TCGType base_type:8;
 558     TCGType type:8;
 559     unsigned int fixed_reg:1;
 560     unsigned int indirect_reg:1;
 561     unsigned int indirect_base:1;
 562     unsigned int mem_coherent:1;
 563     unsigned int mem_allocated:1;
 564     /* If true, the temp is saved across both basic blocks and
 565        translation blocks.  */
 566     unsigned int temp_global:1;
 567     /* If true, the temp is saved across basic blocks but dead
 568        at the end of translation blocks.  If false, the temp is
 569        dead at the end of basic blocks.  */
 570     unsigned int temp_local:1;
 571     unsigned int temp_allocated:1;
 572
 573     tcg_target_long val;
 574     struct TCGTemp *mem_base;
 575     intptr_t mem_offset;
 576     const char *name;
 577
 578     /* Pass-specific information that can be stored for a temporary.
 579        One word worth of integer data, and one pointer to data
 580        allocated separately.  */
 581     uintptr_t state;
 582     void *state_ptr;
 583 } TCGTemp;
 584
 585 typedef struct TCGContext TCGContext;
 586
 587 typedef struct TCGTempSet {
 588     unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)];
 589 } TCGTempSet;
 590
 591 /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding,
 592    this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands.
 593    There are never more than 2 outputs, which means that we can store all
 594    dead + sync data within 16 bits.  */
 595 #define DEAD_ARG  4
 596 #define SYNC_ARG  1
 597 typedef uint16_t TCGLifeData;
 598
 599 /* The layout here is designed to avoid a bitfield crossing of
 600    a 32-bit boundary, which would cause GCC to add extra padding.  */
 601 typedef struct TCGOp {
 602     TCGOpcode opc   : 8;        /*  8 */
 603
 604     /* Parameters for this opcode.  See below.  */
 605     unsigned param1 : 4;        /* 12 */
 606     unsigned param2 : 4;        /* 16 */
 607
 608     /* Lifetime data of the operands.  */
 609     unsigned life   : 16;       /* 32 */
 610
 611     /* Next and previous opcodes.  */
 612     QTAILQ_ENTRY(TCGOp) link;
 613
 614     /* Arguments for the opcode.  */
 615     TCGArg args[MAX_OPC_PARAM];
 616 } TCGOp;
 617
 618 #define TCGOP_CALLI(X)    (X)->param1
 619 #define TCGOP_CALLO(X)    (X)->param2
 620
 621 #define TCGOP_VECL(X)     (X)->param1
 622 #define TCGOP_VECE(X)     (X)->param2
 623
 624 /* Make sure operands fit in the bitfields above.  */
 625 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8));
 626
 627 typedef struct TCGProfile {
 628     int64_t tb_count1;
 629     int64_t tb_count;
 630     int64_t op_count; /* total insn count */
 631     int op_count_max; /* max insn per TB */
 632     int64_t temp_count;
 633     int temp_count_max;
 634     int64_t del_op_count;
 635     int64_t code_in_len;
 636     int64_t code_out_len;
 637     int64_t search_out_len;
 638     int64_t interm_time;
 639     int64_t code_time;
 640     int64_t la_time;
 641     int64_t opt_time;
 642     int64_t restore_count;
 643     int64_t restore_time;
 644     int64_t table_op_count[NB_OPS];
 645 } TCGProfile;
 646
 647 struct TCGContext {
 648     uint8_t *pool_cur, *pool_end;
 649     TCGPool *pool_first, *pool_current, *pool_first_large;
 650     int nb_labels;
 651     int nb_globals;
 652     int nb_temps;
 653     int nb_indirects;
 654
 655     /* goto_tb support */
 656     tcg_insn_unit *code_buf;
 657     uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */
 658     uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */
 659     uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */
 660
 661     TCGRegSet reserved_regs;
 662     uint32_t tb_cflags; /* cflags of the current TB */
 663     intptr_t current_frame_offset;
 664     intptr_t frame_start;
 665     intptr_t frame_end;
 666     TCGTemp *frame_temp;
 667
 668     tcg_insn_unit *code_ptr;
 669
 670 #ifdef CONFIG_PROFILER
 671     TCGProfile prof;
 672 #endif
 673
 674 #ifdef CONFIG_DEBUG_TCG
 675     int temps_in_use;
 676     int goto_tb_issue_mask;
 677 #endif
 678
 679     /* Code generation.  Note that we specifically do not use tcg_insn_unit
 680        here, because there's too much arithmetic throughout that relies
 681        on addition and subtraction working on bytes.  Rely on the GCC
 682        extension that allows arithmetic on void*.  */
 683     void *code_gen_prologue;
 684     void *code_gen_epilogue;
 685     void *code_gen_buffer;
 686     size_t code_gen_buffer_size;
 687     void *code_gen_ptr;
 688     void *data_gen_ptr;
 689
 690     /* Threshold to flush the translated code buffer.  */
 691     void *code_gen_highwater;
 692
 693     /* Track which vCPU triggers events */
 694     CPUState *cpu;                      /* *_trans */
 695
 696     /* These structures are private to tcg-target.inc.c.  */
 697 #ifdef TCG_TARGET_NEED_LDST_LABELS
 698     struct TCGLabelQemuLdst *ldst_labels;
 699 #endif
 700 #ifdef TCG_TARGET_NEED_POOL_LABELS
 701     struct TCGLabelPoolData *pool_labels;
 702 #endif
 703
 704     TCGLabel *exitreq_label;
 705
 706     TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
 707     TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
 708
 709     QTAILQ_HEAD(TCGOpHead, TCGOp) ops, free_ops;
 710
 711     /* Tells which temporary holds a given register.
 712        It does not take into account fixed registers */
 713     TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
 714
 715     uint16_t gen_insn_end_off[TCG_MAX_INSNS];
 716     target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
 717 };
 718
 719 extern TCGContext tcg_init_ctx;
 720 extern __thread TCGContext *tcg_ctx;
 721 extern TCGv_env cpu_env;
 722
 723 static inline size_t temp_idx(TCGTemp *ts)
 724 {
 725     ptrdiff_t n = ts - tcg_ctx->temps;
 726     tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps);
 727     return n;
 728 }
 729
 730 static inline TCGArg temp_arg(TCGTemp *ts)
 731 {
 732     return (uintptr_t)ts;
 733 }
 734
 735 static inline TCGTemp *arg_temp(TCGArg a)
 736 {
 737     return (TCGTemp *)(uintptr_t)a;
 738 }
 739
 740 /* Using the offset of a temporary, relative to TCGContext, rather than
 741    its index means that we don't use 0.  That leaves offset 0 free for
 742    a NULL representation without having to leave index 0 unused.  */
 743 static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v)
 744 {
 745     uintptr_t o = (uintptr_t)v;
 746     TCGTemp *t = (void *)tcg_ctx + o;
 747     tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o);
 748     return t;
 749 }
 750
 751 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v)
 752 {
 753     return tcgv_i32_temp((TCGv_i32)v);
 754 }
 755
 756 static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v)
 757 {
 758     return tcgv_i32_temp((TCGv_i32)v);
 759 }
 760
 761 static inline TCGTemp *tcgv_vec_temp(TCGv_vec v)
 762 {
 763     return tcgv_i32_temp((TCGv_i32)v);
 764 }
 765
 766 static inline TCGArg tcgv_i32_arg(TCGv_i32 v)
 767 {
 768     return temp_arg(tcgv_i32_temp(v));
 769 }
 770
 771 static inline TCGArg tcgv_i64_arg(TCGv_i64 v)
 772 {
 773     return temp_arg(tcgv_i64_temp(v));
 774 }
 775
 776 static inline TCGArg tcgv_ptr_arg(TCGv_ptr v)
 777 {
 778     return temp_arg(tcgv_ptr_temp(v));
 779 }
 780
 781 static inline TCGArg tcgv_vec_arg(TCGv_vec v)
 782 {
 783     return temp_arg(tcgv_vec_temp(v));
 784 }
 785
 786 static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t)
 787 {
 788     (void)temp_idx(t); /* trigger embedded assert */
 789     return (TCGv_i32)((void *)t - (void *)tcg_ctx);
 790 }
 791
 792 static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t)
 793 {
 794     return (TCGv_i64)temp_tcgv_i32(t);
 795 }
 796
 797 static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t)
 798 {
 799     return (TCGv_ptr)temp_tcgv_i32(t);
 800 }
 801
 802 static inline TCGv_vec temp_tcgv_vec(TCGTemp *t)
 803 {
 804     return (TCGv_vec)temp_tcgv_i32(t);
 805 }
 806
 807 #if TCG_TARGET_REG_BITS == 32
 808 static inline TCGv_i32 TCGV_LOW(TCGv_i64 t)
 809 {
 810     return temp_tcgv_i32(tcgv_i64_temp(t));
 811 }
 812
 813 static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t)
 814 {
 815     return temp_tcgv_i32(tcgv_i64_temp(t) + 1);
 816 }
 817 #endif
 818
 819 static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v)
 820 {
 821     op->args[arg] = v;
 822 }
 823
 824 /* The last op that was emitted.  */
 825 static inline TCGOp *tcg_last_op(void)
 826 {
 827     return QTAILQ_LAST(&tcg_ctx->ops, TCGOpHead);
 828 }
 829
 830 /* Test for whether to terminate the TB for using too many opcodes.  */
 831 static inline bool tcg_op_buf_full(void)
 832 {
 833     return false;
 834 }
 835
 836 /* pool based memory allocation */
 837
 838 /* user-mode: tb_lock must be held for tcg_malloc_internal. */
 839 void *tcg_malloc_internal(TCGContext *s, int size);
 840 void tcg_pool_reset(TCGContext *s);
 841 TranslationBlock *tcg_tb_alloc(TCGContext *s);
 842
 843 void tcg_region_init(void);
 844 void tcg_region_reset_all(void);
 845
 846 size_t tcg_code_size(void);
 847 size_t tcg_code_capacity(void);
 848
 849 /* user-mode: Called with tb_lock held.  */
 850 static inline void *tcg_malloc(int size)
 851 {
 852     TCGContext *s = tcg_ctx;
 853     uint8_t *ptr, *ptr_end;
 854
 855     /* ??? This is a weak placeholder for minimum malloc alignment.  */
 856     size = QEMU_ALIGN_UP(size, 8);
 857
 858     ptr = s->pool_cur;
 859     ptr_end = ptr + size;
 860     if (unlikely(ptr_end > s->pool_end)) {
 861         return tcg_malloc_internal(tcg_ctx, size);
 862     } else {
 863         s->pool_cur = ptr_end;
 864         return ptr;
 865     }
 866 }
 867
 868 void tcg_context_init(TCGContext *s);
 869 void tcg_register_thread(void);
 870 void tcg_prologue_init(TCGContext *s);
 871 void tcg_func_start(TCGContext *s);
 872
 873 int tcg_gen_code(TCGContext *s, TranslationBlock *tb);
 874
 875 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
 876
 877 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr,
 878                                      intptr_t, const char *);
 879
 880 TCGv_i32 tcg_temp_new_internal_i32(int temp_local);
 881 TCGv_i64 tcg_temp_new_internal_i64(int temp_local);
 882 TCGv_vec tcg_temp_new_vec(TCGType type);
 883 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match);
 884
 885 void tcg_temp_free_i32(TCGv_i32 arg);
 886 void tcg_temp_free_i64(TCGv_i64 arg);
 887 void tcg_temp_free_vec(TCGv_vec arg);
 888
 889 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
 890                                               const char *name)
 891 {
 892     TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
 893     return temp_tcgv_i32(t);
 894 }
 895
 896 static inline TCGv_i32 tcg_temp_new_i32(void)
 897 {
 898     return tcg_temp_new_internal_i32(0);
 899 }
 900
 901 static inline TCGv_i32 tcg_temp_local_new_i32(void)
 902 {
 903     return tcg_temp_new_internal_i32(1);
 904 }
 905
 906 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
 907                                               const char *name)
 908 {
 909     TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
 910     return temp_tcgv_i64(t);
 911 }
 912
 913 static inline TCGv_i64 tcg_temp_new_i64(void)
 914 {
 915     return tcg_temp_new_internal_i64(0);
 916 }
 917
 918 static inline TCGv_i64 tcg_temp_local_new_i64(void)
 919 {
 920     return tcg_temp_new_internal_i64(1);
 921 }
 922
 923 #if defined(CONFIG_DEBUG_TCG)
 924 /* If you call tcg_clear_temp_count() at the start of a section of
 925  * code which is not supposed to leak any TCG temporaries, then
 926  * calling tcg_check_temp_count() at the end of the section will
 927  * return 1 if the section did in fact leak a temporary.
 928  */
 929 void tcg_clear_temp_count(void);
 930 int tcg_check_temp_count(void);
 931 #else
 932 #define tcg_clear_temp_count() do { } while (0)
 933 #define tcg_check_temp_count() 0
 934 #endif
 935
 936 void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf);
 937 void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf);
 938
 939 #define TCG_CT_ALIAS  0x80
 940 #define TCG_CT_IALIAS 0x40
 941 #define TCG_CT_NEWREG 0x20 /* output requires a new register */
 942 #define TCG_CT_REG    0x01
 943 #define TCG_CT_CONST  0x02 /* any constant of register size */
 944
 945 typedef struct TCGArgConstraint {
 946     uint16_t ct;
 947     uint8_t alias_index;
 948     union {
 949         TCGRegSet regs;
 950     } u;
 951 } TCGArgConstraint;
 952
 953 #define TCG_MAX_OP_ARGS 16
 954
 955 /* Bits for TCGOpDef->flags, 8 bits available.  */
 956 enum {
 957     /* Instruction defines the end of a basic block.  */
 958     TCG_OPF_BB_END       = 0x01,
 959     /* Instruction clobbers call registers and potentially update globals.  */
 960     TCG_OPF_CALL_CLOBBER = 0x02,
 961     /* Instruction has side effects: it cannot be removed if its outputs
 962        are not used, and might trigger exceptions.  */
 963     TCG_OPF_SIDE_EFFECTS = 0x04,
 964     /* Instruction operands are 64-bits (otherwise 32-bits).  */
 965     TCG_OPF_64BIT        = 0x08,
 966     /* Instruction is optional and not implemented by the host, or insn
 967        is generic and should not be implemened by the host.  */
 968     TCG_OPF_NOT_PRESENT  = 0x10,
 969     /* Instruction operands are vectors.  */
 970     TCG_OPF_VECTOR       = 0x20,
 971 };
 972
 973 typedef struct TCGOpDef {
 974     const char *name;
 975     uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
 976     uint8_t flags;
 977     TCGArgConstraint *args_ct;
 978     int *sorted_args;
 979 #if defined(CONFIG_DEBUG_TCG)
 980     int used;
 981 #endif
 982 } TCGOpDef;
 983
 984 extern TCGOpDef tcg_op_defs[];
 985 extern const size_t tcg_op_defs_max;
 986
 987 typedef struct TCGTargetOpDef {
 988     TCGOpcode op;
 989     const char *args_ct_str[TCG_MAX_OP_ARGS];
 990 } TCGTargetOpDef;
 991
 992 #define tcg_abort() \
 993 do {\
 994     fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
 995     abort();\
 996 } while (0)
 997
 998 #if UINTPTR_MAX == UINT32_MAX
 999 static inline TCGv_ptr TCGV_NAT_TO_PTR(TCGv_i32 n) { return (TCGv_ptr)n; }
1000 static inline TCGv_i32 TCGV_PTR_TO_NAT(TCGv_ptr n) { return (TCGv_i32)n; }
1001
1002 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i32((intptr_t)(V)))
1003 #define tcg_global_mem_new_ptr(R, O, N) \
1004     TCGV_NAT_TO_PTR(tcg_global_mem_new_i32((R), (O), (N)))
1005 #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i32())
1006 #define tcg_temp_free_ptr(T) tcg_temp_free_i32(TCGV_PTR_TO_NAT(T))
1007 #else
1008 static inline TCGv_ptr TCGV_NAT_TO_PTR(TCGv_i64 n) { return (TCGv_ptr)n; }
1009 static inline TCGv_i64 TCGV_PTR_TO_NAT(TCGv_ptr n) { return (TCGv_i64)n; }
1010
1011 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i64((intptr_t)(V)))
1012 #define tcg_global_mem_new_ptr(R, O, N) \
1013     TCGV_NAT_TO_PTR(tcg_global_mem_new_i64((R), (O), (N)))
1014 #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i64())
1015 #define tcg_temp_free_ptr(T) tcg_temp_free_i64(TCGV_PTR_TO_NAT(T))
1016 #endif
1017
1018 bool tcg_op_supported(TCGOpcode op);
1019
1020 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args);
1021
1022 TCGOp *tcg_emit_op(TCGOpcode opc);
1023 void tcg_op_remove(TCGContext *s, TCGOp *op);
1024 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc, int narg);
1025 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc, int narg);
1026
1027 void tcg_optimize(TCGContext *s);
1028
1029 /* only used for debugging purposes */
1030 void tcg_dump_ops(TCGContext *s);
1031
1032 TCGv_i32 tcg_const_i32(int32_t val);
1033 TCGv_i64 tcg_const_i64(int64_t val);
1034 TCGv_i32 tcg_const_local_i32(int32_t val);
1035 TCGv_i64 tcg_const_local_i64(int64_t val);
1036 TCGv_vec tcg_const_zeros_vec(TCGType);
1037 TCGv_vec tcg_const_ones_vec(TCGType);
1038 TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec);
1039 TCGv_vec tcg_const_ones_vec_matching(TCGv_vec);
1040
1041 TCGLabel *gen_new_label(void);
1042
1043 /**
1044  * label_arg
1045  * @l: label
1046  *
1047  * Encode a label for storage in the TCG opcode stream.
1048  */
1049
1050 static inline TCGArg label_arg(TCGLabel *l)
1051 {
1052     return (uintptr_t)l;
1053 }
1054
1055 /**
1056  * arg_label
1057  * @i: value
1058  *
1059  * The opposite of label_arg.  Retrieve a label from the
1060  * encoding of the TCG opcode stream.
1061  */
1062
1063 static inline TCGLabel *arg_label(TCGArg i)
1064 {
1065     return (TCGLabel *)(uintptr_t)i;
1066 }
1067
1068 /**
1069  * tcg_ptr_byte_diff
1070  * @a, @b: addresses to be differenced
1071  *
1072  * There are many places within the TCG backends where we need a byte
1073  * difference between two pointers.  While this can be accomplished
1074  * with local casting, it's easy to get wrong -- especially if one is
1075  * concerned with the signedness of the result.
1076  *
1077  * This version relies on GCC's void pointer arithmetic to get the
1078  * correct result.
1079  */
1080
1081 static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b)
1082 {
1083     return a - b;
1084 }
1085
1086 /**
1087  * tcg_pcrel_diff
1088  * @s: the tcg context
1089  * @target: address of the target
1090  *
1091  * Produce a pc-relative difference, from the current code_ptr
1092  * to the destination address.
1093  */
1094
1095 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target)
1096 {
1097     return tcg_ptr_byte_diff(target, s->code_ptr);
1098 }
1099
1100 /**
1101  * tcg_current_code_size
1102  * @s: the tcg context
1103  *
1104  * Compute the current code size within the translation block.
1105  * This is used to fill in qemu's data structures for goto_tb.
1106  */
1107
1108 static inline size_t tcg_current_code_size(TCGContext *s)
1109 {
1110     return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);
1111 }
1112
1113 /* Combine the TCGMemOp and mmu_idx parameters into a single value.  */
1114 typedef uint32_t TCGMemOpIdx;
1115
1116 /**
1117  * make_memop_idx
1118  * @op: memory operation
1119  * @idx: mmu index
1120  *
1121  * Encode these values into a single parameter.
1122  */
1123 static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)
1124 {
1125     tcg_debug_assert(idx <= 15);
1126     return (op << 4) | idx;
1127 }
1128
1129 /**
1130  * get_memop
1131  * @oi: combined op/idx parameter
1132  *
1133  * Extract the memory operation from the combined value.
1134  */
1135 static inline TCGMemOp get_memop(TCGMemOpIdx oi)
1136 {
1137     return oi >> 4;
1138 }
1139
1140 /**
1141  * get_mmuidx
1142  * @oi: combined op/idx parameter
1143  *
1144  * Extract the mmu index from the combined value.
1145  */
1146 static inline unsigned get_mmuidx(TCGMemOpIdx oi)
1147 {
1148     return oi & 15;
1149 }
1150
1151 /**
1152  * tcg_qemu_tb_exec:
1153  * @env: pointer to CPUArchState for the CPU
1154  * @tb_ptr: address of generated code for the TB to execute
1155  *
1156  * Start executing code from a given translation block.
1157  * Where translation blocks have been linked, execution
1158  * may proceed from the given TB into successive ones.
1159  * Control eventually returns only when some action is needed
1160  * from the top-level loop: either control must pass to a TB
1161  * which has not yet been directly linked, or an asynchronous
1162  * event such as an interrupt needs handling.
1163  *
1164  * Return: The return value is the value passed to the corresponding
1165  * tcg_gen_exit_tb() at translation time of the last TB attempted to execute.
1166  * The value is either zero or a 4-byte aligned pointer to that TB combined
1167  * with additional information in its two least significant bits. The
1168  * additional information is encoded as follows:
1169  *  0, 1: the link between this TB and the next is via the specified
1170  *        TB index (0 or 1). That is, we left the TB via (the equivalent
1171  *        of) "goto_tb <index>". The main loop uses this to determine
1172  *        how to link the TB just executed to the next.
1173  *  2:    we are using instruction counting code generation, and we
1174  *        did not start executing this TB because the instruction counter
1175  *        would hit zero midway through it. In this case the pointer
1176  *        returned is the TB we were about to execute, and the caller must
1177  *        arrange to execute the remaining count of instructions.
1178  *  3:    we stopped because the CPU's exit_request flag was set
1179  *        (usually meaning that there is an interrupt that needs to be
1180  *        handled). The pointer returned is the TB we were about to execute
1181  *        when we noticed the pending exit request.
1182  *
1183  * If the bottom two bits indicate an exit-via-index then the CPU
1184  * state is correctly synchronised and ready for execution of the next
1185  * TB (and in particular the guest PC is the address to execute next).
1186  * Otherwise, we gave up on execution of this TB before it started, and
1187  * the caller must fix up the CPU state by calling the CPU's
1188  * synchronize_from_tb() method with the TB pointer we return (falling
1189  * back to calling the CPU's set_pc method with tb->pb if no
1190  * synchronize_from_tb() method exists).
1191  *
1192  * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
1193  * to this default (which just calls the prologue.code emitted by
1194  * tcg_target_qemu_prologue()).
1195  */
1196 #define TB_EXIT_MASK 3
1197 #define TB_EXIT_IDX0 0
1198 #define TB_EXIT_IDX1 1
1199 #define TB_EXIT_REQUESTED 3
1200
1201 #ifdef HAVE_TCG_QEMU_TB_EXEC
1202 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
1203 #else
1204 # define tcg_qemu_tb_exec(env, tb_ptr) \
1205     ((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_ptr)
1206 #endif
1207
1208 void tcg_register_jit(void *buf, size_t buf_size);
1209
1210 #if TCG_TARGET_MAYBE_vec
1211 /* Return zero if the tuple (opc, type, vece) is unsupportable;
1212    return > 0 if it is directly supportable;
1213    return < 0 if we must call tcg_expand_vec_op.  */
1214 int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned);
1215 #else
1216 static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve)
1217 {
1218     return 0;
1219 }
1220 #endif
1221
1222 /* Expand the tuple (opc, type, vece) on the given arguments.  */
1223 void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...);
1224
1225 /* Replicate a constant C accoring to the log2 of the element size.  */
1226 uint64_t dup_const(unsigned vece, uint64_t c);
1227
1228 #define dup_const(VECE, C)                                         \
1229     (__builtin_constant_p(VECE)                                    \
1230      ? (  (VECE) == MO_8  ? 0x0101010101010101ull * (uint8_t)(C)   \
1231         : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C)  \
1232         : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C)  \
1233         : dup_const(VECE, C))                                      \
1234      : dup_const(VECE, C))
1235
1236
1237 /*
1238  * Memory helpers that will be used by TCG generated code.
1239  */
1240 #ifdef CONFIG_SOFTMMU
1241 /* Value zero-extended to tcg register size.  */
1242 tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
1243                                      TCGMemOpIdx oi, uintptr_t retaddr);
1244 tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
1245                                     TCGMemOpIdx oi, uintptr_t retaddr);
1246 tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
1247                                     TCGMemOpIdx oi, uintptr_t retaddr);
1248 uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
1249                            TCGMemOpIdx oi, uintptr_t retaddr);
1250 tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
1251                                     TCGMemOpIdx oi, uintptr_t retaddr);
1252 tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
1253                                     TCGMemOpIdx oi, uintptr_t retaddr);
1254 uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
1255                            TCGMemOpIdx oi, uintptr_t retaddr);
1256
1257 /* Value sign-extended to tcg register size.  */
1258 tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
1259                                      TCGMemOpIdx oi, uintptr_t retaddr);
1260 tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
1261                                     TCGMemOpIdx oi, uintptr_t retaddr);
1262 tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
1263                                     TCGMemOpIdx oi, uintptr_t retaddr);
1264 tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
1265                                     TCGMemOpIdx oi, uintptr_t retaddr);
1266 tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
1267                                     TCGMemOpIdx oi, uintptr_t retaddr);
1268
1269 void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
1270                         TCGMemOpIdx oi, uintptr_t retaddr);
1271 void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1272                        TCGMemOpIdx oi, uintptr_t retaddr);
1273 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1274                        TCGMemOpIdx oi, uintptr_t retaddr);
1275 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1276                        TCGMemOpIdx oi, uintptr_t retaddr);
1277 void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1278                        TCGMemOpIdx oi, uintptr_t retaddr);
1279 void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1280                        TCGMemOpIdx oi, uintptr_t retaddr);
1281 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1282                        TCGMemOpIdx oi, uintptr_t retaddr);
1283
1284 uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
1285                             TCGMemOpIdx oi, uintptr_t retaddr);
1286 uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
1287                             TCGMemOpIdx oi, uintptr_t retaddr);
1288 uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
1289                             TCGMemOpIdx oi, uintptr_t retaddr);
1290 uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
1291                             TCGMemOpIdx oi, uintptr_t retaddr);
1292 uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
1293                             TCGMemOpIdx oi, uintptr_t retaddr);
1294 uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
1295                             TCGMemOpIdx oi, uintptr_t retaddr);
1296 uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
1297                             TCGMemOpIdx oi, uintptr_t retaddr);
1298
1299 /* Temporary aliases until backends are converted.  */
1300 #ifdef TARGET_WORDS_BIGENDIAN
1301 # define helper_ret_ldsw_mmu  helper_be_ldsw_mmu
1302 # define helper_ret_lduw_mmu  helper_be_lduw_mmu
1303 # define helper_ret_ldsl_mmu  helper_be_ldsl_mmu
1304 # define helper_ret_ldul_mmu  helper_be_ldul_mmu
1305 # define helper_ret_ldl_mmu   helper_be_ldul_mmu
1306 # define helper_ret_ldq_mmu   helper_be_ldq_mmu
1307 # define helper_ret_stw_mmu   helper_be_stw_mmu
1308 # define helper_ret_stl_mmu   helper_be_stl_mmu
1309 # define helper_ret_stq_mmu   helper_be_stq_mmu
1310 # define helper_ret_ldw_cmmu  helper_be_ldw_cmmu
1311 # define helper_ret_ldl_cmmu  helper_be_ldl_cmmu
1312 # define helper_ret_ldq_cmmu  helper_be_ldq_cmmu
1313 #else
1314 # define helper_ret_ldsw_mmu  helper_le_ldsw_mmu
1315 # define helper_ret_lduw_mmu  helper_le_lduw_mmu
1316 # define helper_ret_ldsl_mmu  helper_le_ldsl_mmu
1317 # define helper_ret_ldul_mmu  helper_le_ldul_mmu
1318 # define helper_ret_ldl_mmu   helper_le_ldul_mmu
1319 # define helper_ret_ldq_mmu   helper_le_ldq_mmu
1320 # define helper_ret_stw_mmu   helper_le_stw_mmu
1321 # define helper_ret_stl_mmu   helper_le_stl_mmu
1322 # define helper_ret_stq_mmu   helper_le_stq_mmu
1323 # define helper_ret_ldw_cmmu  helper_le_ldw_cmmu
1324 # define helper_ret_ldl_cmmu  helper_le_ldl_cmmu
1325 # define helper_ret_ldq_cmmu  helper_le_ldq_cmmu
1326 #endif
1327
1328 uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
1329                                     uint32_t cmpv, uint32_t newv,
1330                                     TCGMemOpIdx oi, uintptr_t retaddr);
1331 uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr,
1332                                        uint32_t cmpv, uint32_t newv,
1333                                        TCGMemOpIdx oi, uintptr_t retaddr);
1334 uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr,
1335                                        uint32_t cmpv, uint32_t newv,
1336                                        TCGMemOpIdx oi, uintptr_t retaddr);
1337 uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr,
1338                                        uint64_t cmpv, uint64_t newv,
1339                                        TCGMemOpIdx oi, uintptr_t retaddr);
1340 uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr,
1341                                        uint32_t cmpv, uint32_t newv,
1342                                        TCGMemOpIdx oi, uintptr_t retaddr);
1343 uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr,
1344                                        uint32_t cmpv, uint32_t newv,
1345                                        TCGMemOpIdx oi, uintptr_t retaddr);
1346 uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr,
1347                                        uint64_t cmpv, uint64_t newv,
1348                                        TCGMemOpIdx oi, uintptr_t retaddr);
1349
1350 #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX)         \
1351 TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu         \
1352     (CPUArchState *env, target_ulong addr, TYPE val,  \
1353      TCGMemOpIdx oi, uintptr_t retaddr);
1354
1355 #ifdef CONFIG_ATOMIC64
1356 #define GEN_ATOMIC_HELPER_ALL(NAME)          \
1357     GEN_ATOMIC_HELPER(NAME, uint32_t, b)     \
1358     GEN_ATOMIC_HELPER(NAME, uint32_t, w_le)  \
1359     GEN_ATOMIC_HELPER(NAME, uint32_t, w_be)  \
1360     GEN_ATOMIC_HELPER(NAME, uint32_t, l_le)  \
1361     GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)  \
1362     GEN_ATOMIC_HELPER(NAME, uint64_t, q_le)  \
1363     GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
1364 #else
1365 #define GEN_ATOMIC_HELPER_ALL(NAME)          \
1366     GEN_ATOMIC_HELPER(NAME, uint32_t, b)     \
1367     GEN_ATOMIC_HELPER(NAME, uint32_t, w_le)  \
1368     GEN_ATOMIC_HELPER(NAME, uint32_t, w_be)  \
1369     GEN_ATOMIC_HELPER(NAME, uint32_t, l_le)  \
1370     GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)
1371 #endif
1372
1373 GEN_ATOMIC_HELPER_ALL(fetch_add)
1374 GEN_ATOMIC_HELPER_ALL(fetch_sub)
1375 GEN_ATOMIC_HELPER_ALL(fetch_and)
1376 GEN_ATOMIC_HELPER_ALL(fetch_or)
1377 GEN_ATOMIC_HELPER_ALL(fetch_xor)
1378
1379 GEN_ATOMIC_HELPER_ALL(add_fetch)
1380 GEN_ATOMIC_HELPER_ALL(sub_fetch)
1381 GEN_ATOMIC_HELPER_ALL(and_fetch)
1382 GEN_ATOMIC_HELPER_ALL(or_fetch)
1383 GEN_ATOMIC_HELPER_ALL(xor_fetch)
1384
1385 GEN_ATOMIC_HELPER_ALL(xchg)
1386
1387 #undef GEN_ATOMIC_HELPER_ALL
1388 #undef GEN_ATOMIC_HELPER
1389 #endif /* CONFIG_SOFTMMU */
1390
1391 #ifdef CONFIG_ATOMIC128
1392 #include "qemu/int128.h"
1393
1394 /* These aren't really a "proper" helpers because TCG cannot manage Int128.
1395    However, use the same format as the others, for use by the backends. */
1396 Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr,
1397                                      Int128 cmpv, Int128 newv,
1398                                      TCGMemOpIdx oi, uintptr_t retaddr);
1399 Int128 helper_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr,
1400                                      Int128 cmpv, Int128 newv,
1401                                      TCGMemOpIdx oi, uintptr_t retaddr);
1402
1403 Int128 helper_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr,
1404                                 TCGMemOpIdx oi, uintptr_t retaddr);
1405 Int128 helper_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr,
1406                                 TCGMemOpIdx oi, uintptr_t retaddr);
1407 void helper_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1408                               TCGMemOpIdx oi, uintptr_t retaddr);
1409 void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1410                               TCGMemOpIdx oi, uintptr_t retaddr);
1411
1412 #endif /* CONFIG_ATOMIC128 */
1413
1414 #endif /* TCG_H */