2 * CFI parallel flash with Intel command set emulation
4 * Copyright (c) 2006 Thorsten Zitterell
5 * Copyright (c) 2005 Jocelyn Mayer
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
23 * Supported commands/modes are:
30 * It does not support timings
31 * It does not support flash interleaving
32 * It does not implement software data protection as found in many real chips
33 * It does not implement erase suspend/resume commands
34 * It does not implement multiple sectors erase
36 * It does not implement much more ...
39 #include "qemu/osdep.h"
40 #include "hw/block/block.h"
41 #include "hw/block/flash.h"
42 #include "hw/qdev-properties.h"
43 #include "hw/qdev-properties-system.h"
44 #include "sysemu/block-backend.h"
45 #include "qapi/error.h"
46 #include "qemu/error-report.h"
47 #include "qemu/bitops.h"
48 #include "qemu/host-utils.h"
50 #include "qemu/module.h"
51 #include "qemu/option.h"
52 #include "hw/sysbus.h"
53 #include "migration/vmstate.h"
54 #include "sysemu/blockdev.h"
55 #include "sysemu/runstate.h"
59 #define PFLASH_SECURE 1
63 SysBusDevice parent_obj
;
70 uint8_t device_width
; /* If 0, device width not specified. */
71 uint8_t max_device_width
; /* max device width in bytes */
73 uint8_t wcycle
; /* if 0, the flash is read normally */
81 uint8_t cfi_table
[0x52];
83 uint32_t writeblock_size
;
87 VMChangeStateEntry
*vmstate
;
88 bool old_multiple_chip_handling
;
90 /* block update buffer */
91 unsigned char *blk_bytes
;
95 static int pflash_post_load(void *opaque
, int version_id
);
97 static bool pflash_blk_write_state_needed(void *opaque
)
99 PFlashCFI01
*pfl
= opaque
;
101 return (pfl
->blk_offset
!= -1);
104 static const VMStateDescription vmstate_pflash_blk_write
= {
105 .name
= "pflash_cfi01_blk_write",
107 .minimum_version_id
= 1,
108 .needed
= pflash_blk_write_state_needed
,
109 .fields
= (const VMStateField
[]) {
110 VMSTATE_VBUFFER_UINT32(blk_bytes
, PFlashCFI01
, 0, NULL
, writeblock_size
),
111 VMSTATE_UINT32(blk_offset
, PFlashCFI01
),
112 VMSTATE_END_OF_LIST()
116 static const VMStateDescription vmstate_pflash
= {
117 .name
= "pflash_cfi01",
119 .minimum_version_id
= 1,
120 .post_load
= pflash_post_load
,
121 .fields
= (const VMStateField
[]) {
122 VMSTATE_UINT8(wcycle
, PFlashCFI01
),
123 VMSTATE_UINT8(cmd
, PFlashCFI01
),
124 VMSTATE_UINT8(status
, PFlashCFI01
),
125 VMSTATE_UINT64(counter
, PFlashCFI01
),
126 VMSTATE_END_OF_LIST()
128 .subsections
= (const VMStateDescription
* const []) {
129 &vmstate_pflash_blk_write
,
135 * Perform a CFI query based on the bank width of the flash.
136 * If this code is called we know we have a device_width set for
139 static uint32_t pflash_cfi_query(PFlashCFI01
*pfl
, hwaddr offset
)
146 * Adjust incoming offset to match expected device-width
147 * addressing. CFI query addresses are always specified in terms of
148 * the maximum supported width of the device. This means that x8
149 * devices and x8/x16 devices in x8 mode behave differently. For
150 * devices that are not used at their max width, we will be
151 * provided with addresses that use higher address bits than
152 * expected (based on the max width), so we will shift them lower
153 * so that they will match the addresses used when
154 * device_width==max_device_width.
156 boff
= offset
>> (ctz32(pfl
->bank_width
) +
157 ctz32(pfl
->max_device_width
) - ctz32(pfl
->device_width
));
159 if (boff
>= sizeof(pfl
->cfi_table
)) {
163 * Now we will construct the CFI response generated by a single
164 * device, then replicate that for all devices that make up the
165 * bus. For wide parts used in x8 mode, CFI query responses
166 * are different than native byte-wide parts.
168 resp
= pfl
->cfi_table
[boff
];
169 if (pfl
->device_width
!= pfl
->max_device_width
) {
170 /* The only case currently supported is x8 mode for a
173 if (pfl
->device_width
!= 1 || pfl
->bank_width
> 4) {
174 trace_pflash_unsupported_device_configuration(pfl
->name
,
175 pfl
->device_width
, pfl
->max_device_width
);
178 /* CFI query data is repeated, rather than zero padded for
179 * wide devices used in x8 mode.
181 for (i
= 1; i
< pfl
->max_device_width
; i
++) {
182 resp
= deposit32(resp
, 8 * i
, 8, pfl
->cfi_table
[boff
]);
185 /* Replicate responses for each device in bank. */
186 if (pfl
->device_width
< pfl
->bank_width
) {
187 for (i
= pfl
->device_width
;
188 i
< pfl
->bank_width
; i
+= pfl
->device_width
) {
189 resp
= deposit32(resp
, 8 * i
, 8 * pfl
->device_width
, resp
);
198 /* Perform a device id query based on the bank width of the flash. */
199 static uint32_t pflash_devid_query(PFlashCFI01
*pfl
, hwaddr offset
)
206 * Adjust incoming offset to match expected device-width
207 * addressing. Device ID read addresses are always specified in
208 * terms of the maximum supported width of the device. This means
209 * that x8 devices and x8/x16 devices in x8 mode behave
210 * differently. For devices that are not used at their max width,
211 * we will be provided with addresses that use higher address bits
212 * than expected (based on the max width), so we will shift them
213 * lower so that they will match the addresses used when
214 * device_width==max_device_width.
216 boff
= offset
>> (ctz32(pfl
->bank_width
) +
217 ctz32(pfl
->max_device_width
) - ctz32(pfl
->device_width
));
220 * Mask off upper bits which may be used in to query block
221 * or sector lock status at other addresses.
222 * Offsets 2/3 are block lock status, is not emulated.
224 switch (boff
& 0xFF) {
227 trace_pflash_manufacturer_id(pfl
->name
, resp
);
231 trace_pflash_device_id(pfl
->name
, resp
);
234 trace_pflash_device_info(pfl
->name
, offset
);
237 /* Replicate responses for each device in bank. */
238 if (pfl
->device_width
< pfl
->bank_width
) {
239 for (i
= pfl
->device_width
;
240 i
< pfl
->bank_width
; i
+= pfl
->device_width
) {
241 resp
= deposit32(resp
, 8 * i
, 8 * pfl
->device_width
, resp
);
248 static uint32_t pflash_data_read(PFlashCFI01
*pfl
, hwaddr offset
,
256 ret
= ldn_be_p(p
+ offset
, width
);
258 ret
= ldn_le_p(p
+ offset
, width
);
260 trace_pflash_data_read(pfl
->name
, offset
, width
, ret
);
264 static uint32_t pflash_read(PFlashCFI01
*pfl
, hwaddr offset
,
273 /* This should never happen : reset state & treat it as a read */
274 trace_pflash_read_unknown_state(pfl
->name
, pfl
->cmd
);
277 * The command 0x00 is not assigned by the CFI open standard,
278 * but QEMU historically uses it for the READ_ARRAY command (0xff).
281 /* fall through to read code */
282 case 0x00: /* This model reset value for READ_ARRAY (not CFI compliant) */
283 /* Flash area read */
284 ret
= pflash_data_read(pfl
, offset
, width
, be
);
286 case 0x10: /* Single byte program */
287 case 0x20: /* Block erase */
288 case 0x28: /* Block erase */
289 case 0x40: /* single byte program */
290 case 0x50: /* Clear status register */
291 case 0x60: /* Block /un)lock */
292 case 0x70: /* Status Register */
293 case 0xe8: /* Write block */
295 * Status register read. Return status from each device in
299 if (pfl
->device_width
&& width
> pfl
->device_width
) {
300 int shift
= pfl
->device_width
* 8;
301 while (shift
+ pfl
->device_width
* 8 <= width
* 8) {
302 ret
|= pfl
->status
<< shift
;
303 shift
+= pfl
->device_width
* 8;
305 } else if (!pfl
->device_width
&& width
> 2) {
307 * Handle 32 bit flash cases where device width is not
308 * set. (Existing behavior before device width added.)
310 ret
|= pfl
->status
<< 16;
312 trace_pflash_read_status(pfl
->name
, ret
);
315 if (!pfl
->device_width
) {
316 /* Preserve old behavior if device width not specified */
317 boff
= offset
& 0xFF;
318 if (pfl
->bank_width
== 2) {
320 } else if (pfl
->bank_width
== 4) {
326 ret
= pfl
->ident0
<< 8 | pfl
->ident1
;
327 trace_pflash_manufacturer_id(pfl
->name
, ret
);
330 ret
= pfl
->ident2
<< 8 | pfl
->ident3
;
331 trace_pflash_device_id(pfl
->name
, ret
);
334 trace_pflash_device_info(pfl
->name
, boff
);
340 * If we have a read larger than the bank_width, combine multiple
341 * manufacturer/device ID queries into a single response.
344 for (i
= 0; i
< width
; i
+= pfl
->bank_width
) {
345 ret
= deposit32(ret
, i
* 8, pfl
->bank_width
* 8,
346 pflash_devid_query(pfl
,
347 offset
+ i
* pfl
->bank_width
));
351 case 0x98: /* Query mode */
352 if (!pfl
->device_width
) {
353 /* Preserve old behavior if device width not specified */
354 boff
= offset
& 0xFF;
355 if (pfl
->bank_width
== 2) {
357 } else if (pfl
->bank_width
== 4) {
361 if (boff
< sizeof(pfl
->cfi_table
)) {
362 ret
= pfl
->cfi_table
[boff
];
368 * If we have a read larger than the bank_width, combine multiple
369 * CFI queries into a single response.
372 for (i
= 0; i
< width
; i
+= pfl
->bank_width
) {
373 ret
= deposit32(ret
, i
* 8, pfl
->bank_width
* 8,
374 pflash_cfi_query(pfl
,
375 offset
+ i
* pfl
->bank_width
));
381 trace_pflash_io_read(pfl
->name
, offset
, width
, ret
, pfl
->cmd
, pfl
->wcycle
);
386 /* update flash content on disk */
387 static void pflash_update(PFlashCFI01
*pfl
, int offset
,
393 offset_end
= offset
+ size
;
394 /* widen to sector boundaries */
395 offset
= QEMU_ALIGN_DOWN(offset
, BDRV_SECTOR_SIZE
);
396 offset_end
= QEMU_ALIGN_UP(offset_end
, BDRV_SECTOR_SIZE
);
397 ret
= blk_pwrite(pfl
->blk
, offset
, offset_end
- offset
,
398 pfl
->storage
+ offset
, 0);
400 /* TODO set error bit in status */
401 error_report("Could not update PFLASH: %s", strerror(-ret
));
406 /* copy current flash content to block update buffer */
407 static void pflash_blk_write_start(PFlashCFI01
*pfl
, hwaddr offset
)
409 hwaddr mask
= ~(pfl
->writeblock_size
- 1);
411 trace_pflash_write_block_start(pfl
->name
, pfl
->counter
);
412 pfl
->blk_offset
= offset
& mask
;
413 memcpy(pfl
->blk_bytes
, pfl
->storage
+ pfl
->blk_offset
,
414 pfl
->writeblock_size
);
417 /* commit block update buffer changes */
418 static void pflash_blk_write_flush(PFlashCFI01
*pfl
)
420 g_assert(pfl
->blk_offset
!= -1);
421 trace_pflash_write_block_flush(pfl
->name
);
422 memcpy(pfl
->storage
+ pfl
->blk_offset
, pfl
->blk_bytes
,
423 pfl
->writeblock_size
);
424 pflash_update(pfl
, pfl
->blk_offset
, pfl
->writeblock_size
);
425 pfl
->blk_offset
= -1;
428 /* discard block update buffer changes */
429 static void pflash_blk_write_abort(PFlashCFI01
*pfl
)
431 trace_pflash_write_block_abort(pfl
->name
);
432 pfl
->blk_offset
= -1;
435 static inline void pflash_data_write(PFlashCFI01
*pfl
, hwaddr offset
,
436 uint32_t value
, int width
, int be
)
440 if (pfl
->blk_offset
!= -1) {
441 /* block write: redirect writes to block update buffer */
442 if ((offset
< pfl
->blk_offset
) ||
443 (offset
+ width
> pfl
->blk_offset
+ pfl
->writeblock_size
)) {
444 pfl
->status
|= 0x10; /* Programming error */
447 trace_pflash_data_write_block(pfl
->name
, offset
, width
, value
,
449 p
= pfl
->blk_bytes
+ (offset
- pfl
->blk_offset
);
451 /* write directly to storage */
452 trace_pflash_data_write(pfl
->name
, offset
, width
, value
);
453 p
= pfl
->storage
+ offset
;
457 stn_be_p(p
, width
, value
);
459 stn_le_p(p
, width
, value
);
463 static void pflash_write(PFlashCFI01
*pfl
, hwaddr offset
,
464 uint32_t value
, int width
, int be
)
471 trace_pflash_io_write(pfl
->name
, offset
, width
, value
, pfl
->wcycle
);
473 /* Set the device in I/O access mode */
474 memory_region_rom_device_set_romd(&pfl
->mem
, false);
477 switch (pfl
->wcycle
) {
481 case 0x00: /* This model reset value for READ_ARRAY (not CFI) */
482 goto mode_read_array
;
483 case 0x10: /* Single Byte Program */
484 case 0x40: /* Single Byte Program */
485 trace_pflash_write(pfl
->name
, "single byte program (0)");
487 case 0x20: /* Block erase */
489 offset
&= ~(pfl
->sector_len
- 1);
491 trace_pflash_write_block_erase(pfl
->name
, offset
, pfl
->sector_len
);
494 memset(p
+ offset
, 0xff, pfl
->sector_len
);
495 pflash_update(pfl
, offset
, pfl
->sector_len
);
497 pfl
->status
|= 0x20; /* Block erase error */
499 pfl
->status
|= 0x80; /* Ready! */
501 case 0x50: /* Clear status bits */
502 trace_pflash_write(pfl
->name
, "clear status bits");
504 goto mode_read_array
;
505 case 0x60: /* Block (un)lock */
506 trace_pflash_write(pfl
->name
, "block unlock");
508 case 0x70: /* Status Register */
509 trace_pflash_write(pfl
->name
, "read status register");
512 case 0x90: /* Read Device ID */
513 trace_pflash_write(pfl
->name
, "read device information");
516 case 0x98: /* CFI query */
517 trace_pflash_write(pfl
->name
, "CFI query");
519 case 0xe8: /* Write to buffer */
520 trace_pflash_write(pfl
->name
, "write to buffer");
521 /* FIXME should save @offset, @width for case 1+ */
522 qemu_log_mask(LOG_UNIMP
,
523 "%s: Write to buffer emulation is flawed\n",
525 pfl
->status
|= 0x80; /* Ready! */
527 case 0xf0: /* Probe for AMD flash */
528 trace_pflash_write(pfl
->name
, "probe for AMD flash");
529 goto mode_read_array
;
530 case 0xff: /* Read Array */
531 trace_pflash_write(pfl
->name
, "read array mode");
532 goto mode_read_array
;
541 case 0x10: /* Single Byte Program */
542 case 0x40: /* Single Byte Program */
543 trace_pflash_write(pfl
->name
, "single byte program (1)");
545 pflash_data_write(pfl
, offset
, value
, width
, be
);
546 pflash_update(pfl
, offset
, width
);
548 pfl
->status
|= 0x10; /* Programming error */
550 pfl
->status
|= 0x80; /* Ready! */
553 case 0x20: /* Block erase */
555 if (cmd
== 0xd0) { /* confirm */
558 } else if (cmd
== 0xff) { /* Read Array */
559 goto mode_read_array
;
566 * Mask writeblock size based on device width, or bank width if
567 * device width not specified.
569 /* FIXME check @offset, @width */
570 if (pfl
->device_width
) {
571 value
= extract32(value
, 0, pfl
->device_width
* 8);
573 value
= extract32(value
, 0, pfl
->bank_width
* 8);
575 pfl
->counter
= value
;
577 pflash_blk_write_start(pfl
, offset
);
583 } else if (cmd
== 0x01) {
586 } else if (cmd
== 0xff) { /* Read Array */
587 goto mode_read_array
;
589 trace_pflash_write(pfl
->name
, "unknown (un)locking command");
590 goto mode_read_array
;
594 if (cmd
== 0xff) { /* Read Array */
595 goto mode_read_array
;
597 trace_pflash_write(pfl
->name
, "leaving query mode");
606 case 0xe8: /* Block write */
607 /* FIXME check @offset, @width */
608 if (!pfl
->ro
&& (pfl
->blk_offset
!= -1)) {
609 pflash_data_write(pfl
, offset
, value
, width
, be
);
611 pfl
->status
|= 0x10; /* Programming error */
617 trace_pflash_write(pfl
->name
, "block write finished");
627 case 3: /* Confirm mode */
629 case 0xe8: /* Block write */
630 if ((cmd
== 0xd0) && !(pfl
->status
& 0x10)) {
631 pflash_blk_write_flush(pfl
);
635 pflash_blk_write_abort(pfl
);
636 goto mode_read_array
;
640 pflash_blk_write_abort(pfl
);
645 /* Should never happen */
646 trace_pflash_write(pfl
->name
, "invalid write state");
647 goto mode_read_array
;
652 qemu_log_mask(LOG_UNIMP
, "%s: Unimplemented flash cmd sequence "
653 "(offset " HWADDR_FMT_plx
", wcycle 0x%x cmd 0x%x value 0x%x)"
654 "\n", __func__
, offset
, pfl
->wcycle
, pfl
->cmd
, value
);
657 trace_pflash_mode_read_array(pfl
->name
);
658 memory_region_rom_device_set_romd(&pfl
->mem
, true);
660 pfl
->cmd
= 0x00; /* This model reset value for READ_ARRAY (not CFI) */
664 static MemTxResult
pflash_mem_read_with_attrs(void *opaque
, hwaddr addr
, uint64_t *value
,
665 unsigned len
, MemTxAttrs attrs
)
667 PFlashCFI01
*pfl
= opaque
;
668 bool be
= !!(pfl
->features
& (1 << PFLASH_BE
));
670 if ((pfl
->features
& (1 << PFLASH_SECURE
)) && !attrs
.secure
) {
671 *value
= pflash_data_read(opaque
, addr
, len
, be
);
673 *value
= pflash_read(opaque
, addr
, len
, be
);
678 static MemTxResult
pflash_mem_write_with_attrs(void *opaque
, hwaddr addr
, uint64_t value
,
679 unsigned len
, MemTxAttrs attrs
)
681 PFlashCFI01
*pfl
= opaque
;
682 bool be
= !!(pfl
->features
& (1 << PFLASH_BE
));
684 if ((pfl
->features
& (1 << PFLASH_SECURE
)) && !attrs
.secure
) {
687 pflash_write(opaque
, addr
, value
, len
, be
);
692 static const MemoryRegionOps pflash_cfi01_ops
= {
693 .read_with_attrs
= pflash_mem_read_with_attrs
,
694 .write_with_attrs
= pflash_mem_write_with_attrs
,
695 .endianness
= DEVICE_NATIVE_ENDIAN
,
698 static void pflash_cfi01_fill_cfi_table(PFlashCFI01
*pfl
)
700 uint64_t blocks_per_device
, sector_len_per_device
, device_len
;
704 * These are only used to expose the parameters of each device
705 * in the cfi_table[].
707 num_devices
= pfl
->device_width
? (pfl
->bank_width
/ pfl
->device_width
) : 1;
708 if (pfl
->old_multiple_chip_handling
) {
709 blocks_per_device
= pfl
->nb_blocs
/ num_devices
;
710 sector_len_per_device
= pfl
->sector_len
;
712 blocks_per_device
= pfl
->nb_blocs
;
713 sector_len_per_device
= pfl
->sector_len
/ num_devices
;
715 device_len
= sector_len_per_device
* blocks_per_device
;
717 /* Hardcoded CFI table */
718 /* Standard "QRY" string */
719 pfl
->cfi_table
[0x10] = 'Q';
720 pfl
->cfi_table
[0x11] = 'R';
721 pfl
->cfi_table
[0x12] = 'Y';
722 /* Command set (Intel) */
723 pfl
->cfi_table
[0x13] = 0x01;
724 pfl
->cfi_table
[0x14] = 0x00;
725 /* Primary extended table address (none) */
726 pfl
->cfi_table
[0x15] = 0x31;
727 pfl
->cfi_table
[0x16] = 0x00;
728 /* Alternate command set (none) */
729 pfl
->cfi_table
[0x17] = 0x00;
730 pfl
->cfi_table
[0x18] = 0x00;
731 /* Alternate extended table (none) */
732 pfl
->cfi_table
[0x19] = 0x00;
733 pfl
->cfi_table
[0x1A] = 0x00;
735 pfl
->cfi_table
[0x1B] = 0x45;
737 pfl
->cfi_table
[0x1C] = 0x55;
738 /* Vpp min (no Vpp pin) */
739 pfl
->cfi_table
[0x1D] = 0x00;
740 /* Vpp max (no Vpp pin) */
741 pfl
->cfi_table
[0x1E] = 0x00;
743 pfl
->cfi_table
[0x1F] = 0x07;
744 /* Timeout for min size buffer write */
745 pfl
->cfi_table
[0x20] = 0x07;
746 /* Typical timeout for block erase */
747 pfl
->cfi_table
[0x21] = 0x0a;
748 /* Typical timeout for full chip erase (4096 ms) */
749 pfl
->cfi_table
[0x22] = 0x00;
751 pfl
->cfi_table
[0x23] = 0x04;
752 /* Max timeout for buffer write */
753 pfl
->cfi_table
[0x24] = 0x04;
754 /* Max timeout for block erase */
755 pfl
->cfi_table
[0x25] = 0x04;
756 /* Max timeout for chip erase */
757 pfl
->cfi_table
[0x26] = 0x00;
759 pfl
->cfi_table
[0x27] = ctz32(device_len
); /* + 1; */
760 /* Flash device interface (8 & 16 bits) */
761 pfl
->cfi_table
[0x28] = 0x02;
762 pfl
->cfi_table
[0x29] = 0x00;
763 /* Max number of bytes in multi-bytes write */
764 if (pfl
->bank_width
== 1) {
765 pfl
->cfi_table
[0x2A] = 0x08;
767 pfl
->cfi_table
[0x2A] = 0x0B;
769 pfl
->writeblock_size
= 1 << pfl
->cfi_table
[0x2A];
770 if (!pfl
->old_multiple_chip_handling
&& num_devices
> 1) {
771 pfl
->writeblock_size
*= num_devices
;
774 pfl
->cfi_table
[0x2B] = 0x00;
775 /* Number of erase block regions (uniform) */
776 pfl
->cfi_table
[0x2C] = 0x01;
777 /* Erase block region 1 */
778 pfl
->cfi_table
[0x2D] = blocks_per_device
- 1;
779 pfl
->cfi_table
[0x2E] = (blocks_per_device
- 1) >> 8;
780 pfl
->cfi_table
[0x2F] = sector_len_per_device
>> 8;
781 pfl
->cfi_table
[0x30] = sector_len_per_device
>> 16;
784 pfl
->cfi_table
[0x31] = 'P';
785 pfl
->cfi_table
[0x32] = 'R';
786 pfl
->cfi_table
[0x33] = 'I';
788 pfl
->cfi_table
[0x34] = '1';
789 pfl
->cfi_table
[0x35] = '0';
791 pfl
->cfi_table
[0x36] = 0x00;
792 pfl
->cfi_table
[0x37] = 0x00;
793 pfl
->cfi_table
[0x38] = 0x00;
794 pfl
->cfi_table
[0x39] = 0x00;
796 pfl
->cfi_table
[0x3a] = 0x00;
798 pfl
->cfi_table
[0x3b] = 0x00;
799 pfl
->cfi_table
[0x3c] = 0x00;
801 pfl
->cfi_table
[0x3f] = 0x01; /* Number of protection fields */
804 static void pflash_cfi01_realize(DeviceState
*dev
, Error
**errp
)
807 PFlashCFI01
*pfl
= PFLASH_CFI01(dev
);
811 if (pfl
->sector_len
== 0) {
812 error_setg(errp
, "attribute \"sector-length\" not specified or zero.");
815 if (pfl
->nb_blocs
== 0) {
816 error_setg(errp
, "attribute \"num-blocks\" not specified or zero.");
819 if (pfl
->name
== NULL
) {
820 error_setg(errp
, "attribute \"name\" not specified.");
824 total_len
= pfl
->sector_len
* pfl
->nb_blocs
;
826 memory_region_init_rom_device(
827 &pfl
->mem
, OBJECT(dev
),
830 pfl
->name
, total_len
, errp
);
835 pfl
->storage
= memory_region_get_ram_ptr(&pfl
->mem
);
836 sysbus_init_mmio(SYS_BUS_DEVICE(dev
), &pfl
->mem
);
840 pfl
->ro
= !blk_supports_write_perm(pfl
->blk
);
841 perm
= BLK_PERM_CONSISTENT_READ
| (pfl
->ro
? 0 : BLK_PERM_WRITE
);
842 ret
= blk_set_perm(pfl
->blk
, perm
, BLK_PERM_ALL
, errp
);
851 if (!blk_check_size_and_read_all(pfl
->blk
, pfl
->storage
, total_len
,
853 vmstate_unregister_ram(&pfl
->mem
, DEVICE(pfl
));
859 * Default to devices being used at their maximum device width. This was
860 * assumed before the device_width support was added.
862 if (!pfl
->max_device_width
) {
863 pfl
->max_device_width
= pfl
->device_width
;
868 * The command 0x00 is not assigned by the CFI open standard,
869 * but QEMU historically uses it for the READ_ARRAY command (0xff).
872 pfl
->status
= 0x80; /* WSM ready */
873 pflash_cfi01_fill_cfi_table(pfl
);
875 pfl
->blk_bytes
= g_malloc(pfl
->writeblock_size
);
876 pfl
->blk_offset
= -1;
879 static void pflash_cfi01_system_reset(DeviceState
*dev
)
881 PFlashCFI01
*pfl
= PFLASH_CFI01(dev
);
883 trace_pflash_reset(pfl
->name
);
885 * The command 0x00 is not assigned by the CFI open standard,
886 * but QEMU historically uses it for the READ_ARRAY command (0xff).
890 memory_region_rom_device_set_romd(&pfl
->mem
, true);
892 * The WSM ready timer occurs at most 150ns after system reset.
893 * This model deliberately ignores this delay.
897 pfl
->blk_offset
= -1;
900 static Property pflash_cfi01_properties
[] = {
901 DEFINE_PROP_DRIVE("drive", PFlashCFI01
, blk
),
902 /* num-blocks is the number of blocks actually visible to the guest,
903 * ie the total size of the device divided by the sector length.
904 * If we're emulating flash devices wired in parallel the actual
905 * number of blocks per individual device will differ.
907 DEFINE_PROP_UINT32("num-blocks", PFlashCFI01
, nb_blocs
, 0),
908 DEFINE_PROP_UINT64("sector-length", PFlashCFI01
, sector_len
, 0),
909 /* width here is the overall width of this QEMU device in bytes.
910 * The QEMU device may be emulating a number of flash devices
911 * wired up in parallel; the width of each individual flash
912 * device should be specified via device-width. If the individual
913 * devices have a maximum width which is greater than the width
914 * they are being used for, this maximum width should be set via
915 * max-device-width (which otherwise defaults to device-width).
916 * So for instance a 32-bit wide QEMU flash device made from four
917 * 16-bit flash devices used in 8-bit wide mode would be configured
918 * with width = 4, device-width = 1, max-device-width = 2.
920 * If device-width is not specified we default to backwards
921 * compatible behaviour which is a bad emulation of two
922 * 16 bit devices making up a 32 bit wide QEMU device. This
923 * is deprecated for new uses of this device.
925 DEFINE_PROP_UINT8("width", PFlashCFI01
, bank_width
, 0),
926 DEFINE_PROP_UINT8("device-width", PFlashCFI01
, device_width
, 0),
927 DEFINE_PROP_UINT8("max-device-width", PFlashCFI01
, max_device_width
, 0),
928 DEFINE_PROP_BIT("big-endian", PFlashCFI01
, features
, PFLASH_BE
, 0),
929 DEFINE_PROP_BIT("secure", PFlashCFI01
, features
, PFLASH_SECURE
, 0),
930 DEFINE_PROP_UINT16("id0", PFlashCFI01
, ident0
, 0),
931 DEFINE_PROP_UINT16("id1", PFlashCFI01
, ident1
, 0),
932 DEFINE_PROP_UINT16("id2", PFlashCFI01
, ident2
, 0),
933 DEFINE_PROP_UINT16("id3", PFlashCFI01
, ident3
, 0),
934 DEFINE_PROP_STRING("name", PFlashCFI01
, name
),
935 DEFINE_PROP_BOOL("old-multiple-chip-handling", PFlashCFI01
,
936 old_multiple_chip_handling
, false),
937 DEFINE_PROP_END_OF_LIST(),
940 static void pflash_cfi01_class_init(ObjectClass
*klass
, void *data
)
942 DeviceClass
*dc
= DEVICE_CLASS(klass
);
944 dc
->reset
= pflash_cfi01_system_reset
;
945 dc
->realize
= pflash_cfi01_realize
;
946 device_class_set_props(dc
, pflash_cfi01_properties
);
947 dc
->vmsd
= &vmstate_pflash
;
948 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
952 static const TypeInfo pflash_cfi01_info
= {
953 .name
= TYPE_PFLASH_CFI01
,
954 .parent
= TYPE_SYS_BUS_DEVICE
,
955 .instance_size
= sizeof(PFlashCFI01
),
956 .class_init
= pflash_cfi01_class_init
,
959 static void pflash_cfi01_register_types(void)
961 type_register_static(&pflash_cfi01_info
);
964 type_init(pflash_cfi01_register_types
)
966 PFlashCFI01
*pflash_cfi01_register(hwaddr base
,
972 uint16_t id0
, uint16_t id1
,
973 uint16_t id2
, uint16_t id3
,
976 DeviceState
*dev
= qdev_new(TYPE_PFLASH_CFI01
);
979 qdev_prop_set_drive(dev
, "drive", blk
);
981 assert(QEMU_IS_ALIGNED(size
, sector_len
));
982 qdev_prop_set_uint32(dev
, "num-blocks", size
/ sector_len
);
983 qdev_prop_set_uint64(dev
, "sector-length", sector_len
);
984 qdev_prop_set_uint8(dev
, "width", bank_width
);
985 qdev_prop_set_bit(dev
, "big-endian", !!be
);
986 qdev_prop_set_uint16(dev
, "id0", id0
);
987 qdev_prop_set_uint16(dev
, "id1", id1
);
988 qdev_prop_set_uint16(dev
, "id2", id2
);
989 qdev_prop_set_uint16(dev
, "id3", id3
);
990 qdev_prop_set_string(dev
, "name", name
);
991 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
993 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
994 return PFLASH_CFI01(dev
);
997 BlockBackend
*pflash_cfi01_get_blk(PFlashCFI01
*fl
)
1002 MemoryRegion
*pflash_cfi01_get_memory(PFlashCFI01
*fl
)
1008 * Handle -drive if=pflash for machines that use properties.
1009 * If @dinfo is null, do nothing.
1010 * Else if @fl's property "drive" is already set, fatal error.
1011 * Else set it to the BlockBackend with @dinfo.
1013 void pflash_cfi01_legacy_drive(PFlashCFI01
*fl
, DriveInfo
*dinfo
)
1021 loc_push_none(&loc
);
1022 qemu_opts_loc_restore(dinfo
->opts
);
1024 error_report("clashes with -machine");
1027 qdev_prop_set_drive_err(DEVICE(fl
), "drive", blk_by_legacy_dinfo(dinfo
),
1032 static void postload_update_cb(void *opaque
, bool running
, RunState state
)
1034 PFlashCFI01
*pfl
= opaque
;
1036 /* This is called after bdrv_activate_all. */
1037 qemu_del_vm_change_state_handler(pfl
->vmstate
);
1038 pfl
->vmstate
= NULL
;
1040 trace_pflash_postload_cb(pfl
->name
);
1041 pflash_update(pfl
, 0, pfl
->sector_len
* pfl
->nb_blocs
);
1044 static int pflash_post_load(void *opaque
, int version_id
)
1046 PFlashCFI01
*pfl
= opaque
;
1049 pfl
->vmstate
= qemu_add_vm_change_state_handler(postload_update_cb
,