hw/ppc/pnv_core.c

   1 /*
   2  * QEMU PowerPC PowerNV CPU Core model
   3  *
   4  * Copyright (c) 2016, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public License
   8  * as published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "sysemu/reset.h"
  22 #include "qapi/error.h"
  23 #include "qemu/log.h"
  24 #include "qemu/module.h"
  25 #include "target/ppc/cpu.h"
  26 #include "hw/ppc/ppc.h"
  27 #include "hw/ppc/pnv.h"
  28 #include "hw/ppc/pnv_core.h"
  29 #include "hw/ppc/pnv_xscom.h"
  30 #include "hw/ppc/xics.h"
  31 #include "hw/qdev-properties.h"
  32
  33 static const char *pnv_core_cpu_typename(PnvCore *pc)
  34 {
  35     const char *core_type = object_class_get_name(object_get_class(OBJECT(pc)));
  36     int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX);
  37     char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type);
  38     const char *cpu_type = object_class_get_name(object_class_by_name(s));
  39     g_free(s);
  40     return cpu_type;
  41 }
  42
  43 static void pnv_cpu_reset(void *opaque)
  44 {
  45     PowerPCCPU *cpu = opaque;
  46     CPUState *cs = CPU(cpu);
  47     CPUPPCState *env = &cpu->env;
  48
  49     cpu_reset(cs);
  50
  51     /*
  52      * the skiboot firmware elects a primary thread to initialize the
  53      * system and it can be any.
  54      */
  55     env->gpr[3] = PNV_FDT_ADDR;
  56     env->nip = 0x10;
  57     env->msr |= MSR_HVB; /* Hypervisor mode */
  58 }
  59
  60 /*
  61  * These values are read by the PowerNV HW monitors under Linux
  62  */
  63 #define PNV_XSCOM_EX_DTS_RESULT0     0x50000
  64 #define PNV_XSCOM_EX_DTS_RESULT1     0x50001
  65
  66 static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr,
  67                                            unsigned int width)
  68 {
  69     uint32_t offset = addr >> 3;
  70     uint64_t val = 0;
  71
  72     /* The result should be 38 C */
  73     switch (offset) {
  74     case PNV_XSCOM_EX_DTS_RESULT0:
  75         val = 0x26f024f023f0000ull;
  76         break;
  77     case PNV_XSCOM_EX_DTS_RESULT1:
  78         val = 0x24f000000000000ull;
  79         break;
  80     default:
  81         qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
  82                   addr);
  83     }
  84
  85     return val;
  86 }
  87
  88 static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val,
  89                                         unsigned int width)
  90 {
  91     qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
  92                   addr);
  93 }
  94
  95 static const MemoryRegionOps pnv_core_power8_xscom_ops = {
  96     .read = pnv_core_power8_xscom_read,
  97     .write = pnv_core_power8_xscom_write,
  98     .valid.min_access_size = 8,
  99     .valid.max_access_size = 8,
 100     .impl.min_access_size = 8,
 101     .impl.max_access_size = 8,
 102     .endianness = DEVICE_BIG_ENDIAN,
 103 };
 104
 105
 106 /*
 107  * POWER9 core controls
 108  */
 109 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d
 110 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a
 111
 112 static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
 113                                            unsigned int width)
 114 {
 115     uint32_t offset = addr >> 3;
 116     uint64_t val = 0;
 117
 118     /* The result should be 38 C */
 119     switch (offset) {
 120     case PNV_XSCOM_EX_DTS_RESULT0:
 121         val = 0x26f024f023f0000ull;
 122         break;
 123     case PNV_XSCOM_EX_DTS_RESULT1:
 124         val = 0x24f000000000000ull;
 125         break;
 126     case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
 127     case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
 128         val = 0x0;
 129         break;
 130     default:
 131         qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
 132                   addr);
 133     }
 134
 135     return val;
 136 }
 137
 138 static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val,
 139                                         unsigned int width)
 140 {
 141     uint32_t offset = addr >> 3;
 142
 143     switch (offset) {
 144     case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
 145     case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
 146         break;
 147     default:
 148         qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
 149                       addr);
 150     }
 151 }
 152
 153 static const MemoryRegionOps pnv_core_power9_xscom_ops = {
 154     .read = pnv_core_power9_xscom_read,
 155     .write = pnv_core_power9_xscom_write,
 156     .valid.min_access_size = 8,
 157     .valid.max_access_size = 8,
 158     .impl.min_access_size = 8,
 159     .impl.max_access_size = 8,
 160     .endianness = DEVICE_BIG_ENDIAN,
 161 };
 162
 163 static void pnv_realize_vcpu(PowerPCCPU *cpu, PnvChip *chip, Error **errp)
 164 {
 165     CPUPPCState *env = &cpu->env;
 166     int core_pir;
 167     int thread_index = 0; /* TODO: TCG supports only one thread */
 168     ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
 169     Error *local_err = NULL;
 170     PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
 171
 172     object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
 173     if (local_err) {
 174         error_propagate(errp, local_err);
 175         return;
 176     }
 177
 178     pcc->intc_create(chip, cpu, &local_err);
 179     if (local_err) {
 180         error_propagate(errp, local_err);
 181         return;
 182     }
 183
 184     core_pir = object_property_get_uint(OBJECT(cpu), "core-pir", &error_abort);
 185
 186     /*
 187      * The PIR of a thread is the core PIR + the thread index. We will
 188      * need to find a way to get the thread index when TCG supports
 189      * more than 1. We could use the object name ?
 190      */
 191     pir->default_value = core_pir + thread_index;
 192
 193     /* Set time-base frequency to 512 MHz */
 194     cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
 195
 196     qemu_register_reset(pnv_cpu_reset, cpu);
 197 }
 198
 199 static void pnv_core_realize(DeviceState *dev, Error **errp)
 200 {
 201     PnvCore *pc = PNV_CORE(OBJECT(dev));
 202     PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc);
 203     CPUCore *cc = CPU_CORE(OBJECT(dev));
 204     const char *typename = pnv_core_cpu_typename(pc);
 205     Error *local_err = NULL;
 206     void *obj;
 207     int i, j;
 208     char name[32];
 209     Object *chip;
 210
 211     chip = object_property_get_link(OBJECT(dev), "chip", &local_err);
 212     if (!chip) {
 213         error_propagate_prepend(errp, local_err,
 214                                 "required link 'chip' not found: ");
 215         return;
 216     }
 217
 218     pc->threads = g_new(PowerPCCPU *, cc->nr_threads);
 219     for (i = 0; i < cc->nr_threads; i++) {
 220         PowerPCCPU *cpu;
 221
 222         obj = object_new(typename);
 223         cpu = POWERPC_CPU(obj);
 224
 225         pc->threads[i] = POWERPC_CPU(obj);
 226
 227         snprintf(name, sizeof(name), "thread[%d]", i);
 228         object_property_add_child(OBJECT(pc), name, obj, &error_abort);
 229         object_property_add_alias(obj, "core-pir", OBJECT(pc),
 230                                   "pir", &error_abort);
 231
 232         cpu->machine_data = g_new0(PnvCPUState, 1);
 233
 234         object_unref(obj);
 235     }
 236
 237     for (j = 0; j < cc->nr_threads; j++) {
 238         pnv_realize_vcpu(pc->threads[j], PNV_CHIP(chip), &local_err);
 239         if (local_err) {
 240             goto err;
 241         }
 242     }
 243
 244     snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
 245     pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops,
 246                           pc, name, PNV_XSCOM_EX_SIZE);
 247     return;
 248
 249 err:
 250     while (--i >= 0) {
 251         obj = OBJECT(pc->threads[i]);
 252         object_unparent(obj);
 253     }
 254     g_free(pc->threads);
 255     error_propagate(errp, local_err);
 256 }
 257
 258 static void pnv_unrealize_vcpu(PowerPCCPU *cpu)
 259 {
 260     PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
 261
 262     qemu_unregister_reset(pnv_cpu_reset, cpu);
 263     object_unparent(OBJECT(pnv_cpu_state(cpu)->intc));
 264     cpu_remove_sync(CPU(cpu));
 265     cpu->machine_data = NULL;
 266     g_free(pnv_cpu);
 267     object_unparent(OBJECT(cpu));
 268 }
 269
 270 static void pnv_core_unrealize(DeviceState *dev, Error **errp)
 271 {
 272     PnvCore *pc = PNV_CORE(dev);
 273     CPUCore *cc = CPU_CORE(dev);
 274     int i;
 275
 276     for (i = 0; i < cc->nr_threads; i++) {
 277         pnv_unrealize_vcpu(pc->threads[i]);
 278     }
 279     g_free(pc->threads);
 280 }
 281
 282 static Property pnv_core_properties[] = {
 283     DEFINE_PROP_UINT32("pir", PnvCore, pir, 0),
 284     DEFINE_PROP_END_OF_LIST(),
 285 };
 286
 287 static void pnv_core_power8_class_init(ObjectClass *oc, void *data)
 288 {
 289     PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
 290
 291     pcc->xscom_ops = &pnv_core_power8_xscom_ops;
 292 }
 293
 294 static void pnv_core_power9_class_init(ObjectClass *oc, void *data)
 295 {
 296     PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
 297
 298     pcc->xscom_ops = &pnv_core_power9_xscom_ops;
 299 }
 300
 301 static void pnv_core_class_init(ObjectClass *oc, void *data)
 302 {
 303     DeviceClass *dc = DEVICE_CLASS(oc);
 304
 305     dc->realize = pnv_core_realize;
 306     dc->unrealize = pnv_core_unrealize;
 307     dc->props = pnv_core_properties;
 308 }
 309
 310 #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \
 311     {                                           \
 312         .parent = TYPE_PNV_CORE,                \
 313         .name = PNV_CORE_TYPE_NAME(cpu_model),  \
 314         .class_init = pnv_core_##family##_class_init, \
 315     }
 316
 317 static const TypeInfo pnv_core_infos[] = {
 318     {
 319         .name           = TYPE_PNV_CORE,
 320         .parent         = TYPE_CPU_CORE,
 321         .instance_size  = sizeof(PnvCore),
 322         .class_size     = sizeof(PnvCoreClass),
 323         .class_init = pnv_core_class_init,
 324         .abstract       = true,
 325     },
 326     DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"),
 327     DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"),
 328     DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
 329     DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"),
 330 };
 331
 332 DEFINE_TYPES(pnv_core_infos)
 333
 334 /*
 335  * POWER9 Quads
 336  */
 337
 338 #define P9X_EX_NCU_SPEC_BAR                     0x11010
 339
 340 static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
 341                                     unsigned int width)
 342 {
 343     uint32_t offset = addr >> 3;
 344     uint64_t val = -1;
 345
 346     switch (offset) {
 347     case P9X_EX_NCU_SPEC_BAR:
 348     case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
 349         val = 0;
 350         break;
 351     default:
 352         qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
 353                       offset);
 354     }
 355
 356     return val;
 357 }
 358
 359 static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
 360                                  unsigned int width)
 361 {
 362     uint32_t offset = addr >> 3;
 363
 364     switch (offset) {
 365     case P9X_EX_NCU_SPEC_BAR:
 366     case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
 367         break;
 368     default:
 369         qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
 370                   offset);
 371     }
 372 }
 373
 374 static const MemoryRegionOps pnv_quad_xscom_ops = {
 375     .read = pnv_quad_xscom_read,
 376     .write = pnv_quad_xscom_write,
 377     .valid.min_access_size = 8,
 378     .valid.max_access_size = 8,
 379     .impl.min_access_size = 8,
 380     .impl.max_access_size = 8,
 381     .endianness = DEVICE_BIG_ENDIAN,
 382 };
 383
 384 static void pnv_quad_realize(DeviceState *dev, Error **errp)
 385 {
 386     PnvQuad *eq = PNV_QUAD(dev);
 387     char name[32];
 388
 389     snprintf(name, sizeof(name), "xscom-quad.%d", eq->id);
 390     pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops,
 391                           eq, name, PNV9_XSCOM_EQ_SIZE);
 392 }
 393
 394 static Property pnv_quad_properties[] = {
 395     DEFINE_PROP_UINT32("id", PnvQuad, id, 0),
 396     DEFINE_PROP_END_OF_LIST(),
 397 };
 398
 399 static void pnv_quad_class_init(ObjectClass *oc, void *data)
 400 {
 401     DeviceClass *dc = DEVICE_CLASS(oc);
 402
 403     dc->realize = pnv_quad_realize;
 404     dc->props = pnv_quad_properties;
 405 }
 406
 407 static const TypeInfo pnv_quad_info = {
 408     .name          = TYPE_PNV_QUAD,
 409     .parent        = TYPE_DEVICE,
 410     .instance_size = sizeof(PnvQuad),
 411     .class_init    = pnv_quad_class_init,
 412 };
 413
 414 static void pnv_core_register_types(void)
 415 {
 416     type_register_static(&pnv_quad_info);
 417 }
 418
 419 type_init(pnv_core_register_types)