2 * QEMU PowerPC PowerNV CPU Core model
4 * Copyright (c) 2016, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public License
8 * as published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "sysemu/reset.h"
22 #include "qapi/error.h"
24 #include "qemu/module.h"
25 #include "target/ppc/cpu.h"
26 #include "hw/ppc/ppc.h"
27 #include "hw/ppc/pnv.h"
28 #include "hw/ppc/pnv_core.h"
29 #include "hw/ppc/pnv_xscom.h"
30 #include "hw/ppc/xics.h"
31 #include "hw/qdev-properties.h"
33 static const char *pnv_core_cpu_typename(PnvCore
*pc
)
35 const char *core_type
= object_class_get_name(object_get_class(OBJECT(pc
)));
36 int len
= strlen(core_type
) - strlen(PNV_CORE_TYPE_SUFFIX
);
37 char *s
= g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len
, core_type
);
38 const char *cpu_type
= object_class_get_name(object_class_by_name(s
));
43 static void pnv_cpu_reset(void *opaque
)
45 PowerPCCPU
*cpu
= opaque
;
46 CPUState
*cs
= CPU(cpu
);
47 CPUPPCState
*env
= &cpu
->env
;
52 * the skiboot firmware elects a primary thread to initialize the
53 * system and it can be any.
55 env
->gpr
[3] = PNV_FDT_ADDR
;
57 env
->msr
|= MSR_HVB
; /* Hypervisor mode */
61 * These values are read by the PowerNV HW monitors under Linux
63 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000
64 #define PNV_XSCOM_EX_DTS_RESULT1 0x50001
66 static uint64_t pnv_core_power8_xscom_read(void *opaque
, hwaddr addr
,
69 uint32_t offset
= addr
>> 3;
72 /* The result should be 38 C */
74 case PNV_XSCOM_EX_DTS_RESULT0
:
75 val
= 0x26f024f023f0000ull
;
77 case PNV_XSCOM_EX_DTS_RESULT1
:
78 val
= 0x24f000000000000ull
;
81 qemu_log_mask(LOG_UNIMP
, "Warning: reading reg=0x%" HWADDR_PRIx
"\n",
88 static void pnv_core_power8_xscom_write(void *opaque
, hwaddr addr
, uint64_t val
,
91 qemu_log_mask(LOG_UNIMP
, "Warning: writing to reg=0x%" HWADDR_PRIx
"\n",
95 static const MemoryRegionOps pnv_core_power8_xscom_ops
= {
96 .read
= pnv_core_power8_xscom_read
,
97 .write
= pnv_core_power8_xscom_write
,
98 .valid
.min_access_size
= 8,
99 .valid
.max_access_size
= 8,
100 .impl
.min_access_size
= 8,
101 .impl
.max_access_size
= 8,
102 .endianness
= DEVICE_BIG_ENDIAN
,
107 * POWER9 core controls
109 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d
110 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a
112 static uint64_t pnv_core_power9_xscom_read(void *opaque
, hwaddr addr
,
115 uint32_t offset
= addr
>> 3;
118 /* The result should be 38 C */
120 case PNV_XSCOM_EX_DTS_RESULT0
:
121 val
= 0x26f024f023f0000ull
;
123 case PNV_XSCOM_EX_DTS_RESULT1
:
124 val
= 0x24f000000000000ull
;
126 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP
:
127 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR
:
131 qemu_log_mask(LOG_UNIMP
, "Warning: reading reg=0x%" HWADDR_PRIx
"\n",
138 static void pnv_core_power9_xscom_write(void *opaque
, hwaddr addr
, uint64_t val
,
141 uint32_t offset
= addr
>> 3;
144 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP
:
145 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR
:
148 qemu_log_mask(LOG_UNIMP
, "Warning: writing to reg=0x%" HWADDR_PRIx
"\n",
153 static const MemoryRegionOps pnv_core_power9_xscom_ops
= {
154 .read
= pnv_core_power9_xscom_read
,
155 .write
= pnv_core_power9_xscom_write
,
156 .valid
.min_access_size
= 8,
157 .valid
.max_access_size
= 8,
158 .impl
.min_access_size
= 8,
159 .impl
.max_access_size
= 8,
160 .endianness
= DEVICE_BIG_ENDIAN
,
163 static void pnv_realize_vcpu(PowerPCCPU
*cpu
, PnvChip
*chip
, Error
**errp
)
165 CPUPPCState
*env
= &cpu
->env
;
167 int thread_index
= 0; /* TODO: TCG supports only one thread */
168 ppc_spr_t
*pir
= &env
->spr_cb
[SPR_PIR
];
169 Error
*local_err
= NULL
;
170 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
172 object_property_set_bool(OBJECT(cpu
), true, "realized", &local_err
);
174 error_propagate(errp
, local_err
);
178 pcc
->intc_create(chip
, cpu
, &local_err
);
180 error_propagate(errp
, local_err
);
184 core_pir
= object_property_get_uint(OBJECT(cpu
), "core-pir", &error_abort
);
187 * The PIR of a thread is the core PIR + the thread index. We will
188 * need to find a way to get the thread index when TCG supports
189 * more than 1. We could use the object name ?
191 pir
->default_value
= core_pir
+ thread_index
;
193 /* Set time-base frequency to 512 MHz */
194 cpu_ppc_tb_init(env
, PNV_TIMEBASE_FREQ
);
196 qemu_register_reset(pnv_cpu_reset
, cpu
);
199 static void pnv_core_realize(DeviceState
*dev
, Error
**errp
)
201 PnvCore
*pc
= PNV_CORE(OBJECT(dev
));
202 PnvCoreClass
*pcc
= PNV_CORE_GET_CLASS(pc
);
203 CPUCore
*cc
= CPU_CORE(OBJECT(dev
));
204 const char *typename
= pnv_core_cpu_typename(pc
);
205 Error
*local_err
= NULL
;
211 chip
= object_property_get_link(OBJECT(dev
), "chip", &local_err
);
213 error_propagate_prepend(errp
, local_err
,
214 "required link 'chip' not found: ");
218 pc
->threads
= g_new(PowerPCCPU
*, cc
->nr_threads
);
219 for (i
= 0; i
< cc
->nr_threads
; i
++) {
222 obj
= object_new(typename
);
223 cpu
= POWERPC_CPU(obj
);
225 pc
->threads
[i
] = POWERPC_CPU(obj
);
227 snprintf(name
, sizeof(name
), "thread[%d]", i
);
228 object_property_add_child(OBJECT(pc
), name
, obj
, &error_abort
);
229 object_property_add_alias(obj
, "core-pir", OBJECT(pc
),
230 "pir", &error_abort
);
232 cpu
->machine_data
= g_new0(PnvCPUState
, 1);
237 for (j
= 0; j
< cc
->nr_threads
; j
++) {
238 pnv_realize_vcpu(pc
->threads
[j
], PNV_CHIP(chip
), &local_err
);
244 snprintf(name
, sizeof(name
), "xscom-core.%d", cc
->core_id
);
245 pnv_xscom_region_init(&pc
->xscom_regs
, OBJECT(dev
), pcc
->xscom_ops
,
246 pc
, name
, PNV_XSCOM_EX_SIZE
);
251 obj
= OBJECT(pc
->threads
[i
]);
252 object_unparent(obj
);
255 error_propagate(errp
, local_err
);
258 static void pnv_unrealize_vcpu(PowerPCCPU
*cpu
)
260 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
262 qemu_unregister_reset(pnv_cpu_reset
, cpu
);
263 object_unparent(OBJECT(pnv_cpu_state(cpu
)->intc
));
264 cpu_remove_sync(CPU(cpu
));
265 cpu
->machine_data
= NULL
;
267 object_unparent(OBJECT(cpu
));
270 static void pnv_core_unrealize(DeviceState
*dev
, Error
**errp
)
272 PnvCore
*pc
= PNV_CORE(dev
);
273 CPUCore
*cc
= CPU_CORE(dev
);
276 for (i
= 0; i
< cc
->nr_threads
; i
++) {
277 pnv_unrealize_vcpu(pc
->threads
[i
]);
282 static Property pnv_core_properties
[] = {
283 DEFINE_PROP_UINT32("pir", PnvCore
, pir
, 0),
284 DEFINE_PROP_END_OF_LIST(),
287 static void pnv_core_power8_class_init(ObjectClass
*oc
, void *data
)
289 PnvCoreClass
*pcc
= PNV_CORE_CLASS(oc
);
291 pcc
->xscom_ops
= &pnv_core_power8_xscom_ops
;
294 static void pnv_core_power9_class_init(ObjectClass
*oc
, void *data
)
296 PnvCoreClass
*pcc
= PNV_CORE_CLASS(oc
);
298 pcc
->xscom_ops
= &pnv_core_power9_xscom_ops
;
301 static void pnv_core_class_init(ObjectClass
*oc
, void *data
)
303 DeviceClass
*dc
= DEVICE_CLASS(oc
);
305 dc
->realize
= pnv_core_realize
;
306 dc
->unrealize
= pnv_core_unrealize
;
307 dc
->props
= pnv_core_properties
;
310 #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \
312 .parent = TYPE_PNV_CORE, \
313 .name = PNV_CORE_TYPE_NAME(cpu_model), \
314 .class_init = pnv_core_##family##_class_init, \
317 static const TypeInfo pnv_core_infos
[] = {
319 .name
= TYPE_PNV_CORE
,
320 .parent
= TYPE_CPU_CORE
,
321 .instance_size
= sizeof(PnvCore
),
322 .class_size
= sizeof(PnvCoreClass
),
323 .class_init
= pnv_core_class_init
,
326 DEFINE_PNV_CORE_TYPE(power8
, "power8e_v2.1"),
327 DEFINE_PNV_CORE_TYPE(power8
, "power8_v2.0"),
328 DEFINE_PNV_CORE_TYPE(power8
, "power8nvl_v1.0"),
329 DEFINE_PNV_CORE_TYPE(power9
, "power9_v2.0"),
332 DEFINE_TYPES(pnv_core_infos
)
338 #define P9X_EX_NCU_SPEC_BAR 0x11010
340 static uint64_t pnv_quad_xscom_read(void *opaque
, hwaddr addr
,
343 uint32_t offset
= addr
>> 3;
347 case P9X_EX_NCU_SPEC_BAR
:
348 case P9X_EX_NCU_SPEC_BAR
+ 0x400: /* Second EX */
352 qemu_log_mask(LOG_UNIMP
, "%s: writing @0x%08x\n", __func__
,
359 static void pnv_quad_xscom_write(void *opaque
, hwaddr addr
, uint64_t val
,
362 uint32_t offset
= addr
>> 3;
365 case P9X_EX_NCU_SPEC_BAR
:
366 case P9X_EX_NCU_SPEC_BAR
+ 0x400: /* Second EX */
369 qemu_log_mask(LOG_UNIMP
, "%s: writing @0x%08x\n", __func__
,
374 static const MemoryRegionOps pnv_quad_xscom_ops
= {
375 .read
= pnv_quad_xscom_read
,
376 .write
= pnv_quad_xscom_write
,
377 .valid
.min_access_size
= 8,
378 .valid
.max_access_size
= 8,
379 .impl
.min_access_size
= 8,
380 .impl
.max_access_size
= 8,
381 .endianness
= DEVICE_BIG_ENDIAN
,
384 static void pnv_quad_realize(DeviceState
*dev
, Error
**errp
)
386 PnvQuad
*eq
= PNV_QUAD(dev
);
389 snprintf(name
, sizeof(name
), "xscom-quad.%d", eq
->id
);
390 pnv_xscom_region_init(&eq
->xscom_regs
, OBJECT(dev
), &pnv_quad_xscom_ops
,
391 eq
, name
, PNV9_XSCOM_EQ_SIZE
);
394 static Property pnv_quad_properties
[] = {
395 DEFINE_PROP_UINT32("id", PnvQuad
, id
, 0),
396 DEFINE_PROP_END_OF_LIST(),
399 static void pnv_quad_class_init(ObjectClass
*oc
, void *data
)
401 DeviceClass
*dc
= DEVICE_CLASS(oc
);
403 dc
->realize
= pnv_quad_realize
;
404 dc
->props
= pnv_quad_properties
;
407 static const TypeInfo pnv_quad_info
= {
408 .name
= TYPE_PNV_QUAD
,
409 .parent
= TYPE_DEVICE
,
410 .instance_size
= sizeof(PnvQuad
),
411 .class_init
= pnv_quad_class_init
,
414 static void pnv_core_register_types(void)
416 type_register_static(&pnv_quad_info
);
419 type_init(pnv_core_register_types
)