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ppc/pnv: Add a XIVE2 controller to the POWER10 chip
[qemu/kevin.git] / hw / ppc / pnv.c
blobf486fdfb5c72b2174b2cecccdf43f6796f1e9e5a
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qemu/datadir.h"
23 #include "qemu/units.h"
24 #include "qemu/cutils.h"
25 #include "qapi/error.h"
26 #include "sysemu/qtest.h"
27 #include "sysemu/sysemu.h"
28 #include "sysemu/numa.h"
29 #include "sysemu/reset.h"
30 #include "sysemu/runstate.h"
31 #include "sysemu/cpus.h"
32 #include "sysemu/device_tree.h"
33 #include "sysemu/hw_accel.h"
34 #include "target/ppc/cpu.h"
35 #include "hw/ppc/fdt.h"
36 #include "hw/ppc/ppc.h"
37 #include "hw/ppc/pnv.h"
38 #include "hw/ppc/pnv_core.h"
39 #include "hw/loader.h"
40 #include "hw/nmi.h"
41 #include "qapi/visitor.h"
42 #include "monitor/monitor.h"
43 #include "hw/intc/intc.h"
44 #include "hw/ipmi/ipmi.h"
45 #include "target/ppc/mmu-hash64.h"
46 #include "hw/pci/msi.h"
47
48 #include "hw/ppc/xics.h"
49 #include "hw/qdev-properties.h"
50 #include "hw/ppc/pnv_xscom.h"
51 #include "hw/ppc/pnv_pnor.h"
52
53 #include "hw/isa/isa.h"
54 #include "hw/char/serial.h"
55 #include "hw/rtc/mc146818rtc.h"
56
57 #include <libfdt.h>
58
59 #define FDT_MAX_SIZE (1 * MiB)
60
61 #define FW_FILE_NAME "skiboot.lid"
62 #define FW_LOAD_ADDR 0x0
63 #define FW_MAX_SIZE (16 * MiB)
64
65 #define KERNEL_LOAD_ADDR 0x20000000
66 #define KERNEL_MAX_SIZE (128 * MiB)
67 #define INITRD_LOAD_ADDR 0x28000000
68 #define INITRD_MAX_SIZE (128 * MiB)
69
70 static const char *pnv_chip_core_typename(const PnvChip *o)
71 {
72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
75 const char *core_type = object_class_get_name(object_class_by_name(s));
76 g_free(s);
77 return core_type;
78 }
79
80 /*
81 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
82 * 4 * 4 sockets * 12 cores * 8 threads = 1536
83 * Let's make it 2^11
84 */
85 #define MAX_CPUS 2048
86
87 /*
88 * Memory nodes are created by hostboot, one for each range of memory
89 * that has a different "affinity". In practice, it means one range
90 * per chip.
91 */
92 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
93 {
94 char *mem_name;
95 uint64_t mem_reg_property[2];
96 int off;
97
98 mem_reg_property[0] = cpu_to_be64(start);
99 mem_reg_property[1] = cpu_to_be64(size);
100
101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
102 off = fdt_add_subnode(fdt, 0, mem_name);
103 g_free(mem_name);
104
105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
107 sizeof(mem_reg_property))));
108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
109 }
110
111 static int get_cpus_node(void *fdt)
112 {
113 int cpus_offset = fdt_path_offset(fdt, "/cpus");
114
115 if (cpus_offset < 0) {
116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
117 if (cpus_offset) {
118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
120 }
121 }
122 _FDT(cpus_offset);
123 return cpus_offset;
124 }
125
126 /*
127 * The PowerNV cores (and threads) need to use real HW ids and not an
128 * incremental index like it has been done on other platforms. This HW
129 * id is stored in the CPU PIR, it is used to create cpu nodes in the
130 * device tree, used in XSCOM to address cores and in interrupt
131 * servers.
132 */
133 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
134 {
135 PowerPCCPU *cpu = pc->threads[0];
136 CPUState *cs = CPU(cpu);
137 DeviceClass *dc = DEVICE_GET_CLASS(cs);
138 int smt_threads = CPU_CORE(pc)->nr_threads;
139 CPUPPCState *env = &cpu->env;
140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
141 uint32_t servers_prop[smt_threads];
142 int i;
143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
144 0xffffffff, 0xffffffff};
145 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
146 uint32_t cpufreq = 1000000000;
147 uint32_t page_sizes_prop[64];
148 size_t page_sizes_prop_size;
149 const uint8_t pa_features[] = { 24, 0,
150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
154 int offset;
155 char *nodename;
156 int cpus_offset = get_cpus_node(fdt);
157
158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
159 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
160 _FDT(offset);
161 g_free(nodename);
162
163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
164
165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
168
169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
171 env->dcache_line_size)));
172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
173 env->dcache_line_size)));
174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
175 env->icache_line_size)));
176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
177 env->icache_line_size)));
178
179 if (pcc->l1_dcache_size) {
180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
181 pcc->l1_dcache_size)));
182 } else {
183 warn_report("Unknown L1 dcache size for cpu");
184 }
185 if (pcc->l1_icache_size) {
186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
187 pcc->l1_icache_size)));
188 } else {
189 warn_report("Unknown L1 icache size for cpu");
190 }
191
192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size",
195 cpu->hash64_opts->slb_size)));
196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
198
199 if (ppc_has_spr(cpu, SPR_PURR)) {
200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
201 }
202
203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
205 segs, sizeof(segs))));
206 }
207
208 /*
209 * Advertise VMX/VSX (vector extensions) if available
210 * 0 / no property == no vector extensions
211 * 1 == VMX / Altivec available
212 * 2 == VSX available
213 */
214 if (env->insns_flags & PPC_ALTIVEC) {
215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
216
217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
218 }
219
220 /*
221 * Advertise DFP (Decimal Floating Point) if available
222 * 0 / no property == no DFP
223 * 1 == DFP available
224 */
225 if (env->insns_flags2 & PPC2_DFP) {
226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
227 }
228
229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
230 sizeof(page_sizes_prop));
231 if (page_sizes_prop_size) {
232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
233 page_sizes_prop, page_sizes_prop_size)));
234 }
235
236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
237 pa_features, sizeof(pa_features))));
238
239 /* Build interrupt servers properties */
240 for (i = 0; i < smt_threads; i++) {
241 servers_prop[i] = cpu_to_be32(pc->pir + i);
242 }
243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
244 servers_prop, sizeof(servers_prop))));
245 }
246
247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
248 uint32_t nr_threads)
249 {
250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
251 char *name;
252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
253 uint32_t irange[2], i, rsize;
254 uint64_t *reg;
255 int offset;
256
257 irange[0] = cpu_to_be32(pir);
258 irange[1] = cpu_to_be32(nr_threads);
259
260 rsize = sizeof(uint64_t) * 2 * nr_threads;
261 reg = g_malloc(rsize);
262 for (i = 0; i < nr_threads; i++) {
263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
264 reg[i * 2 + 1] = cpu_to_be64(0x1000);
265 }
266
267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
268 offset = fdt_add_subnode(fdt, 0, name);
269 _FDT(offset);
270 g_free(name);
271
272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
274 _FDT((fdt_setprop_string(fdt, offset, "device_type",
275 "PowerPC-External-Interrupt-Presentation")));
276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
278 irange, sizeof(irange))));
279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
281 g_free(reg);
282 }
283
284 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
285 {
286 static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
287 int i;
288
289 pnv_dt_xscom(chip, fdt, 0,
290 cpu_to_be64(PNV_XSCOM_BASE(chip)),
291 cpu_to_be64(PNV_XSCOM_SIZE),
292 compat, sizeof(compat));
293
294 for (i = 0; i < chip->nr_cores; i++) {
295 PnvCore *pnv_core = chip->cores[i];
296
297 pnv_dt_core(chip, pnv_core, fdt);
298
299 /* Interrupt Control Presenters (ICP). One per core. */
300 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
301 }
302
303 if (chip->ram_size) {
304 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
305 }
306 }
307
308 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
309 {
310 static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
311 int i;
312
313 pnv_dt_xscom(chip, fdt, 0,
314 cpu_to_be64(PNV9_XSCOM_BASE(chip)),
315 cpu_to_be64(PNV9_XSCOM_SIZE),
316 compat, sizeof(compat));
317
318 for (i = 0; i < chip->nr_cores; i++) {
319 PnvCore *pnv_core = chip->cores[i];
320
321 pnv_dt_core(chip, pnv_core, fdt);
322 }
323
324 if (chip->ram_size) {
325 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
326 }
327
328 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
329 }
330
331 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
332 {
333 static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
334 int i;
335
336 pnv_dt_xscom(chip, fdt, 0,
337 cpu_to_be64(PNV10_XSCOM_BASE(chip)),
338 cpu_to_be64(PNV10_XSCOM_SIZE),
339 compat, sizeof(compat));
340
341 for (i = 0; i < chip->nr_cores; i++) {
342 PnvCore *pnv_core = chip->cores[i];
343
344 pnv_dt_core(chip, pnv_core, fdt);
345 }
346
347 if (chip->ram_size) {
348 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
349 }
350
351 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
352 }
353
354 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
355 {
356 uint32_t io_base = d->ioport_id;
357 uint32_t io_regs[] = {
358 cpu_to_be32(1),
359 cpu_to_be32(io_base),
360 cpu_to_be32(2)
361 };
362 char *name;
363 int node;
364
365 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
366 node = fdt_add_subnode(fdt, lpc_off, name);
367 _FDT(node);
368 g_free(name);
369
370 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
371 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
372 }
373
374 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
375 {
376 const char compatible[] = "ns16550\0pnpPNP,501";
377 uint32_t io_base = d->ioport_id;
378 uint32_t io_regs[] = {
379 cpu_to_be32(1),
380 cpu_to_be32(io_base),
381 cpu_to_be32(8)
382 };
383 uint32_t irq;
384 char *name;
385 int node;
386
387 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal);
388
389 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
390 node = fdt_add_subnode(fdt, lpc_off, name);
391 _FDT(node);
392 g_free(name);
393
394 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
395 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
396 sizeof(compatible))));
397
398 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
399 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
400 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
401 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
402 fdt_get_phandle(fdt, lpc_off))));
403
404 /* This is needed by Linux */
405 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
406 }
407
408 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
409 {
410 const char compatible[] = "bt\0ipmi-bt";
411 uint32_t io_base;
412 uint32_t io_regs[] = {
413 cpu_to_be32(1),
414 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
415 cpu_to_be32(3)
416 };
417 uint32_t irq;
418 char *name;
419 int node;
420
421 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
422 io_regs[1] = cpu_to_be32(io_base);
423
424 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
425
426 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
427 node = fdt_add_subnode(fdt, lpc_off, name);
428 _FDT(node);
429 g_free(name);
430
431 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
432 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
433 sizeof(compatible))));
434
435 /* Mark it as reserved to avoid Linux trying to claim it */
436 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
437 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
438 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
439 fdt_get_phandle(fdt, lpc_off))));
440 }
441
442 typedef struct ForeachPopulateArgs {
443 void *fdt;
444 int offset;
445 } ForeachPopulateArgs;
446
447 static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
448 {
449 ForeachPopulateArgs *args = opaque;
450 ISADevice *d = ISA_DEVICE(dev);
451
452 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
453 pnv_dt_rtc(d, args->fdt, args->offset);
454 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
455 pnv_dt_serial(d, args->fdt, args->offset);
456 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
457 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
458 } else {
459 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
460 d->ioport_id);
461 }
462
463 return 0;
464 }
465
466 /*
467 * The default LPC bus of a multichip system is on chip 0. It's
468 * recognized by the firmware (skiboot) using a "primary" property.
469 */
470 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
471 {
472 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
473 ForeachPopulateArgs args = {
474 .fdt = fdt,
475 .offset = isa_offset,
476 };
477 uint32_t phandle;
478
479 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
480
481 phandle = qemu_fdt_alloc_phandle(fdt);
482 assert(phandle > 0);
483 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));
484
485 /*
486 * ISA devices are not necessarily parented to the ISA bus so we
487 * can not use object_child_foreach()
488 */
489 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
490 &args);
491 }
492
493 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt)
494 {
495 int off;
496
497 off = fdt_add_subnode(fdt, 0, "ibm,opal");
498 off = fdt_add_subnode(fdt, off, "power-mgt");
499
500 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
501 }
502
503 static void *pnv_dt_create(MachineState *machine)
504 {
505 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
506 PnvMachineState *pnv = PNV_MACHINE(machine);
507 void *fdt;
508 char *buf;
509 int off;
510 int i;
511
512 fdt = g_malloc0(FDT_MAX_SIZE);
513 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
514
515 /* /qemu node */
516 _FDT((fdt_add_subnode(fdt, 0, "qemu")));
517
518 /* Root node */
519 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
520 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
521 _FDT((fdt_setprop_string(fdt, 0, "model",
522 "IBM PowerNV (emulated by qemu)")));
523 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size)));
524
525 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
526 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
527 if (qemu_uuid_set) {
528 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf)));
529 }
530 g_free(buf);
531
532 off = fdt_add_subnode(fdt, 0, "chosen");
533 if (machine->kernel_cmdline) {
534 _FDT((fdt_setprop_string(fdt, off, "bootargs",
535 machine->kernel_cmdline)));
536 }
537
538 if (pnv->initrd_size) {
539 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
540 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
541
542 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
543 &start_prop, sizeof(start_prop))));
544 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
545 &end_prop, sizeof(end_prop))));
546 }
547
548 /* Populate device tree for each chip */
549 for (i = 0; i < pnv->num_chips; i++) {
550 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
551 }
552
553 /* Populate ISA devices on chip 0 */
554 pnv_dt_isa(pnv, fdt);
555
556 if (pnv->bmc) {
557 pnv_dt_bmc_sensors(pnv->bmc, fdt);
558 }
559
560 /* Create an extra node for power management on machines that support it */
561 if (pmc->dt_power_mgt) {
562 pmc->dt_power_mgt(pnv, fdt);
563 }
564
565 return fdt;
566 }
567
568 static void pnv_powerdown_notify(Notifier *n, void *opaque)
569 {
570 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier);
571
572 if (pnv->bmc) {
573 pnv_bmc_powerdown(pnv->bmc);
574 }
575 }
576
577 static void pnv_reset(MachineState *machine)
578 {
579 PnvMachineState *pnv = PNV_MACHINE(machine);
580 IPMIBmc *bmc;
581 void *fdt;
582
583 qemu_devices_reset();
584
585 /*
586 * The machine should provide by default an internal BMC simulator.
587 * If not, try to use the BMC device that was provided on the command
588 * line.
589 */
590 bmc = pnv_bmc_find(&error_fatal);
591 if (!pnv->bmc) {
592 if (!bmc) {
593 if (!qtest_enabled()) {
594 warn_report("machine has no BMC device. Use '-device "
595 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
596 "to define one");
597 }
598 } else {
599 pnv_bmc_set_pnor(bmc, pnv->pnor);
600 pnv->bmc = bmc;
601 }
602 }
603
604 fdt = pnv_dt_create(machine);
605
606 /* Pack resulting tree */
607 _FDT((fdt_pack(fdt)));
608
609 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
610 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
611
612 g_free(fdt);
613 }
614
615 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
616 {
617 Pnv8Chip *chip8 = PNV8_CHIP(chip);
618 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
619 }
620
621 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
622 {
623 Pnv8Chip *chip8 = PNV8_CHIP(chip);
624 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
625 }
626
627 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
628 {
629 Pnv9Chip *chip9 = PNV9_CHIP(chip);
630 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
631 }
632
633 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
634 {
635 Pnv10Chip *chip10 = PNV10_CHIP(chip);
636 return pnv_lpc_isa_create(&chip10->lpc, false, errp);
637 }
638
639 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
640 {
641 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
642 }
643
644 static int pnv_chip_power8_pic_print_info_child(Object *child, void *opaque)
645 {
646 Monitor *mon = opaque;
647 PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3);
648
649 if (phb3) {
650 pnv_phb3_msi_pic_print_info(&phb3->msis, mon);
651 ics_pic_print_info(&phb3->lsis, mon);
652 }
653 return 0;
654 }
655
656 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
657 {
658 Pnv8Chip *chip8 = PNV8_CHIP(chip);
659
660 ics_pic_print_info(&chip8->psi.ics, mon);
661 object_child_foreach(OBJECT(chip),
662 pnv_chip_power8_pic_print_info_child, mon);
663 }
664
665 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque)
666 {
667 Monitor *mon = opaque;
668 PnvPHB4 *phb4 = (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4);
669
670 if (phb4) {
671 pnv_phb4_pic_print_info(phb4, mon);
672 }
673 return 0;
674 }
675
676 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
677 {
678 Pnv9Chip *chip9 = PNV9_CHIP(chip);
679
680 pnv_xive_pic_print_info(&chip9->xive, mon);
681 pnv_psi_pic_print_info(&chip9->psi, mon);
682
683 object_child_foreach_recursive(OBJECT(chip),
684 pnv_chip_power9_pic_print_info_child, mon);
685 }
686
687 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
688 uint32_t core_id)
689 {
690 return PNV_XSCOM_EX_BASE(core_id);
691 }
692
693 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip,
694 uint32_t core_id)
695 {
696 return PNV9_XSCOM_EC_BASE(core_id);
697 }
698
699 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip,
700 uint32_t core_id)
701 {
702 return PNV10_XSCOM_EC_BASE(core_id);
703 }
704
705 static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
706 {
707 PowerPCCPUClass *ppc_default =
708 POWERPC_CPU_CLASS(object_class_by_name(default_type));
709 PowerPCCPUClass *ppc =
710 POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
711
712 return ppc_default->pvr_match(ppc_default, ppc->pvr);
713 }
714
715 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
716 {
717 ISADevice *dev = isa_new("isa-ipmi-bt");
718
719 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal);
720 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal);
721 isa_realize_and_unref(dev, bus, &error_fatal);
722 }
723
724 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
725 {
726 Pnv10Chip *chip10 = PNV10_CHIP(chip);
727
728 pnv_xive2_pic_print_info(&chip10->xive, mon);
729 pnv_psi_pic_print_info(&chip10->psi, mon);
730 }
731
732 /* Always give the first 1GB to chip 0 else we won't boot */
733 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id)
734 {
735 MachineState *machine = MACHINE(pnv);
736 uint64_t ram_per_chip;
737
738 assert(machine->ram_size >= 1 * GiB);
739
740 ram_per_chip = machine->ram_size / pnv->num_chips;
741 if (ram_per_chip >= 1 * GiB) {
742 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
743 }
744
745 assert(pnv->num_chips > 1);
746
747 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1);
748 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
749 }
750
751 static void pnv_init(MachineState *machine)
752 {
753 const char *bios_name = machine->firmware ?: FW_FILE_NAME;
754 PnvMachineState *pnv = PNV_MACHINE(machine);
755 MachineClass *mc = MACHINE_GET_CLASS(machine);
756 char *fw_filename;
757 long fw_size;
758 uint64_t chip_ram_start = 0;
759 int i;
760 char *chip_typename;
761 DriveInfo *pnor = drive_get(IF_MTD, 0, 0);
762 DeviceState *dev;
763
764 if (kvm_enabled()) {
765 error_report("The powernv machine does not work with KVM acceleration");
766 exit(EXIT_FAILURE);
767 }
768
769 /* allocate RAM */
770 if (machine->ram_size < mc->default_ram_size) {
771 char *sz = size_to_str(mc->default_ram_size);
772 error_report("Invalid RAM size, should be bigger than %s", sz);
773 g_free(sz);
774 exit(EXIT_FAILURE);
775 }
776 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
777
778 /*
779 * Create our simple PNOR device
780 */
781 dev = qdev_new(TYPE_PNV_PNOR);
782 if (pnor) {
783 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor));
784 }
785 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
786 pnv->pnor = PNV_PNOR(dev);
787
788 /* load skiboot firmware */
789 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
790 if (!fw_filename) {
791 error_report("Could not find OPAL firmware '%s'", bios_name);
792 exit(1);
793 }
794
795 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE);
796 if (fw_size < 0) {
797 error_report("Could not load OPAL firmware '%s'", fw_filename);
798 exit(1);
799 }
800 g_free(fw_filename);
801
802 /* load kernel */
803 if (machine->kernel_filename) {
804 long kernel_size;
805
806 kernel_size = load_image_targphys(machine->kernel_filename,
807 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
808 if (kernel_size < 0) {
809 error_report("Could not load kernel '%s'",
810 machine->kernel_filename);
811 exit(1);
812 }
813 }
814
815 /* load initrd */
816 if (machine->initrd_filename) {
817 pnv->initrd_base = INITRD_LOAD_ADDR;
818 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
819 pnv->initrd_base, INITRD_MAX_SIZE);
820 if (pnv->initrd_size < 0) {
821 error_report("Could not load initial ram disk '%s'",
822 machine->initrd_filename);
823 exit(1);
824 }
825 }
826
827 /* MSIs are supported on this platform */
828 msi_nonbroken = true;
829
830 /*
831 * Check compatibility of the specified CPU with the machine
832 * default.
833 */
834 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
835 error_report("invalid CPU model '%s' for %s machine",
836 machine->cpu_type, mc->name);
837 exit(1);
838 }
839
840 /* Create the processor chips */
841 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
842 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
843 i, machine->cpu_type);
844 if (!object_class_by_name(chip_typename)) {
845 error_report("invalid chip model '%.*s' for %s machine",
846 i, machine->cpu_type, mc->name);
847 exit(1);
848 }
849
850 pnv->num_chips =
851 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
852 /*
853 * TODO: should we decide on how many chips we can create based
854 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
855 */
856 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) {
857 error_report("invalid number of chips: '%d'", pnv->num_chips);
858 error_printf(
859 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n");
860 exit(1);
861 }
862
863 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
864 for (i = 0; i < pnv->num_chips; i++) {
865 char chip_name[32];
866 Object *chip = OBJECT(qdev_new(chip_typename));
867 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i);
868
869 pnv->chips[i] = PNV_CHIP(chip);
870
871 /* Distribute RAM among the chips */
872 object_property_set_int(chip, "ram-start", chip_ram_start,
873 &error_fatal);
874 object_property_set_int(chip, "ram-size", chip_ram_size,
875 &error_fatal);
876 chip_ram_start += chip_ram_size;
877
878 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i);
879 object_property_add_child(OBJECT(pnv), chip_name, chip);
880 object_property_set_int(chip, "chip-id", i, &error_fatal);
881 object_property_set_int(chip, "nr-cores", machine->smp.cores,
882 &error_fatal);
883 object_property_set_int(chip, "nr-threads", machine->smp.threads,
884 &error_fatal);
885 /*
886 * The POWER8 machine use the XICS interrupt interface.
887 * Propagate the XICS fabric to the chip and its controllers.
888 */
889 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) {
890 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort);
891 }
892 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) {
893 object_property_set_link(chip, "xive-fabric", OBJECT(pnv),
894 &error_abort);
895 }
896 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal);
897 }
898 g_free(chip_typename);
899
900 /* Instantiate ISA bus on chip 0 */
901 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
902
903 /* Create serial port */
904 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
905
906 /* Create an RTC ISA device too */
907 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
908
909 /*
910 * Create the machine BMC simulator and the IPMI BT device for
911 * communication with the BMC
912 */
913 if (defaults_enabled()) {
914 pnv->bmc = pnv_bmc_create(pnv->pnor);
915 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
916 }
917
918 /*
919 * The PNOR is mapped on the LPC FW address space by the BMC.
920 * Since we can not reach the remote BMC machine with LPC memops,
921 * map it always for now.
922 */
923 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET,
924 &pnv->pnor->mmio);
925
926 /*
927 * OpenPOWER systems use a IPMI SEL Event message to notify the
928 * host to powerdown
929 */
930 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
931 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
932 }
933
934 /*
935 * 0:21 Reserved - Read as zeros
936 * 22:24 Chip ID
937 * 25:28 Core number
938 * 29:31 Thread ID
939 */
940 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
941 {
942 return (chip->chip_id << 7) | (core_id << 3);
943 }
944
945 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
946 Error **errp)
947 {
948 Pnv8Chip *chip8 = PNV8_CHIP(chip);
949 Error *local_err = NULL;
950 Object *obj;
951 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
952
953 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err);
954 if (local_err) {
955 error_propagate(errp, local_err);
956 return;
957 }
958
959 pnv_cpu->intc = obj;
960 }
961
962
963 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
964 {
965 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
966
967 icp_reset(ICP(pnv_cpu->intc));
968 }
969
970 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
971 {
972 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
973
974 icp_destroy(ICP(pnv_cpu->intc));
975 pnv_cpu->intc = NULL;
976 }
977
978 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
979 Monitor *mon)
980 {
981 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
982 }
983
984 /*
985 * 0:48 Reserved - Read as zeroes
986 * 49:52 Node ID
987 * 53:55 Chip ID
988 * 56 Reserved - Read as zero
989 * 57:61 Core number
990 * 62:63 Thread ID
991 *
992 * We only care about the lower bits. uint32_t is fine for the moment.
993 */
994 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
995 {
996 return (chip->chip_id << 8) | (core_id << 2);
997 }
998
999 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
1000 {
1001 return (chip->chip_id << 8) | (core_id << 2);
1002 }
1003
1004 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1005 Error **errp)
1006 {
1007 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1008 Error *local_err = NULL;
1009 Object *obj;
1010 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1011
1012 /*
1013 * The core creates its interrupt presenter but the XIVE interrupt
1014 * controller object is initialized afterwards. Hopefully, it's
1015 * only used at runtime.
1016 */
1017 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive),
1018 &local_err);
1019 if (local_err) {
1020 error_propagate(errp, local_err);
1021 return;
1022 }
1023
1024 pnv_cpu->intc = obj;
1025 }
1026
1027 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1028 {
1029 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1030
1031 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1032 }
1033
1034 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1035 {
1036 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1037
1038 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1039 pnv_cpu->intc = NULL;
1040 }
1041
1042 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1043 Monitor *mon)
1044 {
1045 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1046 }
1047
1048 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1049 Error **errp)
1050 {
1051 Pnv10Chip *chip10 = PNV10_CHIP(chip);
1052 Error *local_err = NULL;
1053 Object *obj;
1054 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1055
1056 /*
1057 * The core creates its interrupt presenter but the XIVE2 interrupt
1058 * controller object is initialized afterwards. Hopefully, it's
1059 * only used at runtime.
1060 */
1061 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive),
1062 &local_err);
1063 if (local_err) {
1064 error_propagate(errp, local_err);
1065 return;
1066 }
1067
1068 pnv_cpu->intc = obj;
1069 }
1070
1071 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1072 {
1073 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1074
1075 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1076 }
1077
1078 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1079 {
1080 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1081
1082 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1083 pnv_cpu->intc = NULL;
1084 }
1085
1086 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1087 Monitor *mon)
1088 {
1089 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1090 }
1091
1092 /*
1093 * Allowed core identifiers on a POWER8 Processor Chip :
1094 *
1095 * <EX0 reserved>
1096 * EX1 - Venice only
1097 * EX2 - Venice only
1098 * EX3 - Venice only
1099 * EX4
1100 * EX5
1101 * EX6
1102 * <EX7,8 reserved> <reserved>
1103 * EX9 - Venice only
1104 * EX10 - Venice only
1105 * EX11 - Venice only
1106 * EX12
1107 * EX13
1108 * EX14
1109 * <EX15 reserved>
1110 */
1111 #define POWER8E_CORE_MASK (0x7070ull)
1112 #define POWER8_CORE_MASK (0x7e7eull)
1113
1114 /*
1115 * POWER9 has 24 cores, ids starting at 0x0
1116 */
1117 #define POWER9_CORE_MASK (0xffffffffffffffull)
1118
1119
1120 #define POWER10_CORE_MASK (0xffffffffffffffull)
1121
1122 static void pnv_chip_power8_instance_init(Object *obj)
1123 {
1124 Pnv8Chip *chip8 = PNV8_CHIP(obj);
1125 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1126 int i;
1127
1128 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
1129 (Object **)&chip8->xics,
1130 object_property_allow_set_link,
1131 OBJ_PROP_LINK_STRONG);
1132
1133 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI);
1134
1135 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC);
1136
1137 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC);
1138
1139 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER);
1140
1141 if (defaults_enabled()) {
1142 chip8->num_phbs = pcc->num_phbs;
1143 }
1144
1145 for (i = 0; i < chip8->num_phbs; i++) {
1146 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3);
1147 }
1148
1149 }
1150
1151 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
1152 {
1153 PnvChip *chip = PNV_CHIP(chip8);
1154 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1155 int i, j;
1156 char *name;
1157
1158 name = g_strdup_printf("icp-%x", chip->chip_id);
1159 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
1160 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
1161 g_free(name);
1162
1163 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
1164
1165 /* Map the ICP registers for each thread */
1166 for (i = 0; i < chip->nr_cores; i++) {
1167 PnvCore *pnv_core = chip->cores[i];
1168 int core_hwid = CPU_CORE(pnv_core)->core_id;
1169
1170 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
1171 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
1172 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
1173
1174 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
1175 &icp->mmio);
1176 }
1177 }
1178 }
1179
1180 /* Attach a root port device */
1181 void pnv_phb_attach_root_port(PCIHostState *pci, const char *name)
1182 {
1183 PCIDevice *root = pci_new(PCI_DEVFN(0, 0), name);
1184
1185 pci_realize_and_unref(root, pci->bus, &error_fatal);
1186 }
1187
1188 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1189 {
1190 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1191 PnvChip *chip = PNV_CHIP(dev);
1192 Pnv8Chip *chip8 = PNV8_CHIP(dev);
1193 Pnv8Psi *psi8 = &chip8->psi;
1194 Error *local_err = NULL;
1195 int i;
1196
1197 assert(chip8->xics);
1198
1199 /* XSCOM bridge is first */
1200 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
1201 if (local_err) {
1202 error_propagate(errp, local_err);
1203 return;
1204 }
1205 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
1206
1207 pcc->parent_realize(dev, &local_err);
1208 if (local_err) {
1209 error_propagate(errp, local_err);
1210 return;
1211 }
1212
1213 /* Processor Service Interface (PSI) Host Bridge */
1214 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip),
1215 &error_fatal);
1216 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS,
1217 OBJECT(chip8->xics), &error_abort);
1218 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) {
1219 return;
1220 }
1221 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
1222 &PNV_PSI(psi8)->xscom_regs);
1223
1224 /* Create LPC controller */
1225 object_property_set_link(OBJECT(&chip8->lpc), "psi", OBJECT(&chip8->psi),
1226 &error_abort);
1227 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal);
1228 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
1229
1230 chip->fw_mr = &chip8->lpc.isa_fw;
1231 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
1232 (uint64_t) PNV_XSCOM_BASE(chip),
1233 PNV_XSCOM_LPC_BASE);
1234
1235 /*
1236 * Interrupt Management Area. This is the memory region holding
1237 * all the Interrupt Control Presenter (ICP) registers
1238 */
1239 pnv_chip_icp_realize(chip8, &local_err);
1240 if (local_err) {
1241 error_propagate(errp, local_err);
1242 return;
1243 }
1244
1245 /* Create the simplified OCC model */
1246 object_property_set_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi),
1247 &error_abort);
1248 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) {
1249 return;
1250 }
1251 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
1252
1253 /* OCC SRAM model */
1254 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
1255 &chip8->occ.sram_regs);
1256
1257 /* HOMER */
1258 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip),
1259 &error_abort);
1260 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) {
1261 return;
1262 }
1263 /* Homer Xscom region */
1264 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
1265
1266 /* Homer mmio region */
1267 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1268 &chip8->homer.regs);
1269
1270 /* PHB3 controllers */
1271 for (i = 0; i < chip8->num_phbs; i++) {
1272 PnvPHB3 *phb = &chip8->phbs[i];
1273
1274 object_property_set_int(OBJECT(phb), "index", i, &error_fatal);
1275 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id,
1276 &error_fatal);
1277 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip),
1278 &error_fatal);
1279 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
1280 return;
1281 }
1282 }
1283 }
1284
1285 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
1286 {
1287 addr &= (PNV_XSCOM_SIZE - 1);
1288 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
1289 }
1290
1291 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1292 {
1293 DeviceClass *dc = DEVICE_CLASS(klass);
1294 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1295
1296 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
1297 k->cores_mask = POWER8E_CORE_MASK;
1298 k->num_phbs = 3;
1299 k->core_pir = pnv_chip_core_pir_p8;
1300 k->intc_create = pnv_chip_power8_intc_create;
1301 k->intc_reset = pnv_chip_power8_intc_reset;
1302 k->intc_destroy = pnv_chip_power8_intc_destroy;
1303 k->intc_print_info = pnv_chip_power8_intc_print_info;
1304 k->isa_create = pnv_chip_power8_isa_create;
1305 k->dt_populate = pnv_chip_power8_dt_populate;
1306 k->pic_print_info = pnv_chip_power8_pic_print_info;
1307 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1308 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1309 dc->desc = "PowerNV Chip POWER8E";
1310
1311 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1312 &k->parent_realize);
1313 }
1314
1315 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1316 {
1317 DeviceClass *dc = DEVICE_CLASS(klass);
1318 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1319
1320 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
1321 k->cores_mask = POWER8_CORE_MASK;
1322 k->num_phbs = 3;
1323 k->core_pir = pnv_chip_core_pir_p8;
1324 k->intc_create = pnv_chip_power8_intc_create;
1325 k->intc_reset = pnv_chip_power8_intc_reset;
1326 k->intc_destroy = pnv_chip_power8_intc_destroy;
1327 k->intc_print_info = pnv_chip_power8_intc_print_info;
1328 k->isa_create = pnv_chip_power8_isa_create;
1329 k->dt_populate = pnv_chip_power8_dt_populate;
1330 k->pic_print_info = pnv_chip_power8_pic_print_info;
1331 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1332 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1333 dc->desc = "PowerNV Chip POWER8";
1334
1335 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1336 &k->parent_realize);
1337 }
1338
1339 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1340 {
1341 DeviceClass *dc = DEVICE_CLASS(klass);
1342 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1343
1344 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
1345 k->cores_mask = POWER8_CORE_MASK;
1346 k->num_phbs = 4;
1347 k->core_pir = pnv_chip_core_pir_p8;
1348 k->intc_create = pnv_chip_power8_intc_create;
1349 k->intc_reset = pnv_chip_power8_intc_reset;
1350 k->intc_destroy = pnv_chip_power8_intc_destroy;
1351 k->intc_print_info = pnv_chip_power8_intc_print_info;
1352 k->isa_create = pnv_chip_power8nvl_isa_create;
1353 k->dt_populate = pnv_chip_power8_dt_populate;
1354 k->pic_print_info = pnv_chip_power8_pic_print_info;
1355 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1356 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1357 dc->desc = "PowerNV Chip POWER8NVL";
1358
1359 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1360 &k->parent_realize);
1361 }
1362
1363 static void pnv_chip_power9_instance_init(Object *obj)
1364 {
1365 PnvChip *chip = PNV_CHIP(obj);
1366 Pnv9Chip *chip9 = PNV9_CHIP(obj);
1367 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1368 int i;
1369
1370 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE);
1371 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive),
1372 "xive-fabric");
1373
1374 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI);
1375
1376 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC);
1377
1378 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC);
1379
1380 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER);
1381
1382 /* Number of PECs is the chip default */
1383 chip->num_pecs = pcc->num_pecs;
1384
1385 for (i = 0; i < chip->num_pecs; i++) {
1386 object_initialize_child(obj, "pec[*]", &chip9->pecs[i],
1387 TYPE_PNV_PHB4_PEC);
1388 }
1389 }
1390
1391 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1392 {
1393 PnvChip *chip = PNV_CHIP(chip9);
1394 int i;
1395
1396 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1397 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1398
1399 for (i = 0; i < chip9->nr_quads; i++) {
1400 char eq_name[32];
1401 PnvQuad *eq = &chip9->quads[i];
1402 PnvCore *pnv_core = chip->cores[i * 4];
1403 int core_id = CPU_CORE(pnv_core)->core_id;
1404
1405 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
1406 object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
1407 sizeof(*eq), TYPE_PNV_QUAD,
1408 &error_fatal, NULL);
1409
1410 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
1411 qdev_realize(DEVICE(eq), NULL, &error_fatal);
1412
1413 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
1414 &eq->xscom_regs);
1415 }
1416 }
1417
1418 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp)
1419 {
1420 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1421 int i;
1422
1423 for (i = 0; i < chip->num_pecs; i++) {
1424 PnvPhb4PecState *pec = &chip9->pecs[i];
1425 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1426 uint32_t pec_nest_base;
1427 uint32_t pec_pci_base;
1428
1429 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
1430 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
1431 &error_fatal);
1432 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
1433 &error_fatal);
1434 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
1435 return;
1436 }
1437
1438 pec_nest_base = pecc->xscom_nest_base(pec);
1439 pec_pci_base = pecc->xscom_pci_base(pec);
1440
1441 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1442 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1443 }
1444 }
1445
1446 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1447 {
1448 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1449 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1450 PnvChip *chip = PNV_CHIP(dev);
1451 Pnv9Psi *psi9 = &chip9->psi;
1452 Error *local_err = NULL;
1453
1454 /* XSCOM bridge is first */
1455 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err);
1456 if (local_err) {
1457 error_propagate(errp, local_err);
1458 return;
1459 }
1460 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip));
1461
1462 pcc->parent_realize(dev, &local_err);
1463 if (local_err) {
1464 error_propagate(errp, local_err);
1465 return;
1466 }
1467
1468 pnv_chip_quad_realize(chip9, &local_err);
1469 if (local_err) {
1470 error_propagate(errp, local_err);
1471 return;
1472 }
1473
1474 /* XIVE interrupt controller (POWER9) */
1475 object_property_set_int(OBJECT(&chip9->xive), "ic-bar",
1476 PNV9_XIVE_IC_BASE(chip), &error_fatal);
1477 object_property_set_int(OBJECT(&chip9->xive), "vc-bar",
1478 PNV9_XIVE_VC_BASE(chip), &error_fatal);
1479 object_property_set_int(OBJECT(&chip9->xive), "pc-bar",
1480 PNV9_XIVE_PC_BASE(chip), &error_fatal);
1481 object_property_set_int(OBJECT(&chip9->xive), "tm-bar",
1482 PNV9_XIVE_TM_BASE(chip), &error_fatal);
1483 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip),
1484 &error_abort);
1485 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) {
1486 return;
1487 }
1488 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1489 &chip9->xive.xscom_regs);
1490
1491 /* Processor Service Interface (PSI) Host Bridge */
1492 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip),
1493 &error_fatal);
1494 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) {
1495 return;
1496 }
1497 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1498 &PNV_PSI(psi9)->xscom_regs);
1499
1500 /* LPC */
1501 object_property_set_link(OBJECT(&chip9->lpc), "psi", OBJECT(&chip9->psi),
1502 &error_abort);
1503 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) {
1504 return;
1505 }
1506 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1507 &chip9->lpc.xscom_regs);
1508
1509 chip->fw_mr = &chip9->lpc.isa_fw;
1510 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1511 (uint64_t) PNV9_LPCM_BASE(chip));
1512
1513 /* Create the simplified OCC model */
1514 object_property_set_link(OBJECT(&chip9->occ), "psi", OBJECT(&chip9->psi),
1515 &error_abort);
1516 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) {
1517 return;
1518 }
1519 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
1520
1521 /* OCC SRAM model */
1522 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
1523 &chip9->occ.sram_regs);
1524
1525 /* HOMER */
1526 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip),
1527 &error_abort);
1528 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) {
1529 return;
1530 }
1531 /* Homer Xscom region */
1532 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
1533
1534 /* Homer mmio region */
1535 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
1536 &chip9->homer.regs);
1537
1538 /* PEC PHBs */
1539 pnv_chip_power9_pec_realize(chip, &local_err);
1540 if (local_err) {
1541 error_propagate(errp, local_err);
1542 return;
1543 }
1544 }
1545
1546 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
1547 {
1548 addr &= (PNV9_XSCOM_SIZE - 1);
1549 return addr >> 3;
1550 }
1551
1552 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1553 {
1554 DeviceClass *dc = DEVICE_CLASS(klass);
1555 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1556
1557 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
1558 k->cores_mask = POWER9_CORE_MASK;
1559 k->core_pir = pnv_chip_core_pir_p9;
1560 k->intc_create = pnv_chip_power9_intc_create;
1561 k->intc_reset = pnv_chip_power9_intc_reset;
1562 k->intc_destroy = pnv_chip_power9_intc_destroy;
1563 k->intc_print_info = pnv_chip_power9_intc_print_info;
1564 k->isa_create = pnv_chip_power9_isa_create;
1565 k->dt_populate = pnv_chip_power9_dt_populate;
1566 k->pic_print_info = pnv_chip_power9_pic_print_info;
1567 k->xscom_core_base = pnv_chip_power9_xscom_core_base;
1568 k->xscom_pcba = pnv_chip_power9_xscom_pcba;
1569 dc->desc = "PowerNV Chip POWER9";
1570 k->num_pecs = PNV9_CHIP_MAX_PEC;
1571
1572 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1573 &k->parent_realize);
1574 }
1575
1576 static void pnv_chip_power10_instance_init(Object *obj)
1577 {
1578 Pnv10Chip *chip10 = PNV10_CHIP(obj);
1579
1580 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2);
1581 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive),
1582 "xive-fabric");
1583 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
1584 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
1585 }
1586
1587 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
1588 {
1589 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1590 PnvChip *chip = PNV_CHIP(dev);
1591 Pnv10Chip *chip10 = PNV10_CHIP(dev);
1592 Error *local_err = NULL;
1593
1594 /* XSCOM bridge is first */
1595 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err);
1596 if (local_err) {
1597 error_propagate(errp, local_err);
1598 return;
1599 }
1600 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip));
1601
1602 pcc->parent_realize(dev, &local_err);
1603 if (local_err) {
1604 error_propagate(errp, local_err);
1605 return;
1606 }
1607
1608 /* XIVE2 interrupt controller (POWER10) */
1609 object_property_set_int(OBJECT(&chip10->xive), "ic-bar",
1610 PNV10_XIVE2_IC_BASE(chip), &error_fatal);
1611 object_property_set_int(OBJECT(&chip10->xive), "esb-bar",
1612 PNV10_XIVE2_ESB_BASE(chip), &error_fatal);
1613 object_property_set_int(OBJECT(&chip10->xive), "end-bar",
1614 PNV10_XIVE2_END_BASE(chip), &error_fatal);
1615 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar",
1616 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal);
1617 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar",
1618 PNV10_XIVE2_NVC_BASE(chip), &error_fatal);
1619 object_property_set_int(OBJECT(&chip10->xive), "tm-bar",
1620 PNV10_XIVE2_TM_BASE(chip), &error_fatal);
1621 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip),
1622 &error_abort);
1623 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) {
1624 return;
1625 }
1626 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE,
1627 &chip10->xive.xscom_regs);
1628
1629 /* Processor Service Interface (PSI) Host Bridge */
1630 object_property_set_int(OBJECT(&chip10->psi), "bar",
1631 PNV10_PSIHB_BASE(chip), &error_fatal);
1632 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) {
1633 return;
1634 }
1635 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
1636 &PNV_PSI(&chip10->psi)->xscom_regs);
1637
1638 /* LPC */
1639 object_property_set_link(OBJECT(&chip10->lpc), "psi",
1640 OBJECT(&chip10->psi), &error_abort);
1641 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) {
1642 return;
1643 }
1644 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
1645 &chip10->lpc.xscom_regs);
1646
1647 chip->fw_mr = &chip10->lpc.isa_fw;
1648 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1649 (uint64_t) PNV10_LPCM_BASE(chip));
1650 }
1651
1652 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
1653 {
1654 addr &= (PNV10_XSCOM_SIZE - 1);
1655 return addr >> 3;
1656 }
1657
1658 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
1659 {
1660 DeviceClass *dc = DEVICE_CLASS(klass);
1661 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1662
1663 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
1664 k->cores_mask = POWER10_CORE_MASK;
1665 k->core_pir = pnv_chip_core_pir_p10;
1666 k->intc_create = pnv_chip_power10_intc_create;
1667 k->intc_reset = pnv_chip_power10_intc_reset;
1668 k->intc_destroy = pnv_chip_power10_intc_destroy;
1669 k->intc_print_info = pnv_chip_power10_intc_print_info;
1670 k->isa_create = pnv_chip_power10_isa_create;
1671 k->dt_populate = pnv_chip_power10_dt_populate;
1672 k->pic_print_info = pnv_chip_power10_pic_print_info;
1673 k->xscom_core_base = pnv_chip_power10_xscom_core_base;
1674 k->xscom_pcba = pnv_chip_power10_xscom_pcba;
1675 dc->desc = "PowerNV Chip POWER10";
1676
1677 device_class_set_parent_realize(dc, pnv_chip_power10_realize,
1678 &k->parent_realize);
1679 }
1680
1681 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1682 {
1683 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1684 int cores_max;
1685
1686 /*
1687 * No custom mask for this chip, let's use the default one from *
1688 * the chip class
1689 */
1690 if (!chip->cores_mask) {
1691 chip->cores_mask = pcc->cores_mask;
1692 }
1693
1694 /* filter alien core ids ! some are reserved */
1695 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1696 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1697 chip->cores_mask);
1698 return;
1699 }
1700 chip->cores_mask &= pcc->cores_mask;
1701
1702 /* now that we have a sane layout, let check the number of cores */
1703 cores_max = ctpop64(chip->cores_mask);
1704 if (chip->nr_cores > cores_max) {
1705 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1706 cores_max);
1707 return;
1708 }
1709 }
1710
1711 static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
1712 {
1713 Error *error = NULL;
1714 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1715 const char *typename = pnv_chip_core_typename(chip);
1716 int i, core_hwid;
1717 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
1718
1719 if (!object_class_by_name(typename)) {
1720 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1721 return;
1722 }
1723
1724 /* Cores */
1725 pnv_chip_core_sanitize(chip, &error);
1726 if (error) {
1727 error_propagate(errp, error);
1728 return;
1729 }
1730
1731 chip->cores = g_new0(PnvCore *, chip->nr_cores);
1732
1733 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1734 && (i < chip->nr_cores); core_hwid++) {
1735 char core_name[32];
1736 PnvCore *pnv_core;
1737 uint64_t xscom_core_base;
1738
1739 if (!(chip->cores_mask & (1ull << core_hwid))) {
1740 continue;
1741 }
1742
1743 pnv_core = PNV_CORE(object_new(typename));
1744
1745 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
1746 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core));
1747 chip->cores[i] = pnv_core;
1748 object_property_set_int(OBJECT(pnv_core), "nr-threads",
1749 chip->nr_threads, &error_fatal);
1750 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID,
1751 core_hwid, &error_fatal);
1752 object_property_set_int(OBJECT(pnv_core), "pir",
1753 pcc->core_pir(chip, core_hwid), &error_fatal);
1754 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr,
1755 &error_fatal);
1756 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip),
1757 &error_abort);
1758 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal);
1759
1760 /* Each core has an XSCOM MMIO region */
1761 xscom_core_base = pcc->xscom_core_base(chip, core_hwid);
1762
1763 pnv_xscom_add_subregion(chip, xscom_core_base,
1764 &pnv_core->xscom_regs);
1765 i++;
1766 }
1767 }
1768
1769 static void pnv_chip_realize(DeviceState *dev, Error **errp)
1770 {
1771 PnvChip *chip = PNV_CHIP(dev);
1772 Error *error = NULL;
1773
1774 /* Cores */
1775 pnv_chip_core_realize(chip, &error);
1776 if (error) {
1777 error_propagate(errp, error);
1778 return;
1779 }
1780 }
1781
1782 static Property pnv_chip_properties[] = {
1783 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1784 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
1785 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
1786 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
1787 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
1788 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
1789 DEFINE_PROP_END_OF_LIST(),
1790 };
1791
1792 static void pnv_chip_class_init(ObjectClass *klass, void *data)
1793 {
1794 DeviceClass *dc = DEVICE_CLASS(klass);
1795
1796 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
1797 dc->realize = pnv_chip_realize;
1798 device_class_set_props(dc, pnv_chip_properties);
1799 dc->desc = "PowerNV Chip";
1800 }
1801
1802 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
1803 {
1804 int i, j;
1805
1806 for (i = 0; i < chip->nr_cores; i++) {
1807 PnvCore *pc = chip->cores[i];
1808 CPUCore *cc = CPU_CORE(pc);
1809
1810 for (j = 0; j < cc->nr_threads; j++) {
1811 if (ppc_cpu_pir(pc->threads[j]) == pir) {
1812 return pc->threads[j];
1813 }
1814 }
1815 }
1816 return NULL;
1817 }
1818
1819 typedef struct ForeachPhb3Args {
1820 int irq;
1821 ICSState *ics;
1822 } ForeachPhb3Args;
1823
1824 static int pnv_ics_get_child(Object *child, void *opaque)
1825 {
1826 ForeachPhb3Args *args = opaque;
1827 PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3);
1828
1829 if (phb3) {
1830 if (ics_valid_irq(&phb3->lsis, args->irq)) {
1831 args->ics = &phb3->lsis;
1832 }
1833 if (ics_valid_irq(ICS(&phb3->msis), args->irq)) {
1834 args->ics = ICS(&phb3->msis);
1835 }
1836 }
1837 return args->ics ? 1 : 0;
1838 }
1839
1840 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1841 {
1842 PnvMachineState *pnv = PNV_MACHINE(xi);
1843 ForeachPhb3Args args = { irq, NULL };
1844 int i;
1845
1846 for (i = 0; i < pnv->num_chips; i++) {
1847 PnvChip *chip = pnv->chips[i];
1848 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1849
1850 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1851 return &chip8->psi.ics;
1852 }
1853
1854 object_child_foreach(OBJECT(chip), pnv_ics_get_child, &args);
1855 if (args.ics) {
1856 return args.ics;
1857 }
1858 }
1859 return NULL;
1860 }
1861
1862 void pnv_chip_parent_fixup(PnvChip *chip, Object *obj, int index)
1863 {
1864 Object *parent = OBJECT(chip);
1865 g_autofree char *default_id =
1866 g_strdup_printf("%s[%d]", object_get_typename(obj), index);
1867
1868 if (obj->parent == parent) {
1869 return;
1870 }
1871
1872 object_ref(obj);
1873 object_unparent(obj);
1874 object_property_add_child(
1875 parent, DEVICE(obj)->id ? DEVICE(obj)->id : default_id, obj);
1876 object_unref(obj);
1877 }
1878
1879 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id)
1880 {
1881 int i;
1882
1883 for (i = 0; i < pnv->num_chips; i++) {
1884 PnvChip *chip = pnv->chips[i];
1885 if (chip->chip_id == chip_id) {
1886 return chip;
1887 }
1888 }
1889 return NULL;
1890 }
1891
1892 static int pnv_ics_resend_child(Object *child, void *opaque)
1893 {
1894 PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3);
1895
1896 if (phb3) {
1897 ics_resend(&phb3->lsis);
1898 ics_resend(ICS(&phb3->msis));
1899 }
1900 return 0;
1901 }
1902
1903 static void pnv_ics_resend(XICSFabric *xi)
1904 {
1905 PnvMachineState *pnv = PNV_MACHINE(xi);
1906 int i;
1907
1908 for (i = 0; i < pnv->num_chips; i++) {
1909 PnvChip *chip = pnv->chips[i];
1910 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1911
1912 ics_resend(&chip8->psi.ics);
1913 object_child_foreach(OBJECT(chip), pnv_ics_resend_child, NULL);
1914 }
1915 }
1916
1917 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
1918 {
1919 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
1920
1921 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
1922 }
1923
1924 static void pnv_pic_print_info(InterruptStatsProvider *obj,
1925 Monitor *mon)
1926 {
1927 PnvMachineState *pnv = PNV_MACHINE(obj);
1928 int i;
1929 CPUState *cs;
1930
1931 CPU_FOREACH(cs) {
1932 PowerPCCPU *cpu = POWERPC_CPU(cs);
1933
1934 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
1935 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu,
1936 mon);
1937 }
1938
1939 for (i = 0; i < pnv->num_chips; i++) {
1940 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
1941 }
1942 }
1943
1944 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
1945 uint8_t nvt_blk, uint32_t nvt_idx,
1946 bool cam_ignore, uint8_t priority,
1947 uint32_t logic_serv,
1948 XiveTCTXMatch *match)
1949 {
1950 PnvMachineState *pnv = PNV_MACHINE(xfb);
1951 int total_count = 0;
1952 int i;
1953
1954 for (i = 0; i < pnv->num_chips; i++) {
1955 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
1956 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
1957 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
1958 int count;
1959
1960 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
1961 priority, logic_serv, match);
1962
1963 if (count < 0) {
1964 return count;
1965 }
1966
1967 total_count += count;
1968 }
1969
1970 return total_count;
1971 }
1972
1973 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format,
1974 uint8_t nvt_blk, uint32_t nvt_idx,
1975 bool cam_ignore, uint8_t priority,
1976 uint32_t logic_serv,
1977 XiveTCTXMatch *match)
1978 {
1979 PnvMachineState *pnv = PNV_MACHINE(xfb);
1980 int total_count = 0;
1981 int i;
1982
1983 for (i = 0; i < pnv->num_chips; i++) {
1984 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]);
1985 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive);
1986 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
1987 int count;
1988
1989 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
1990 priority, logic_serv, match);
1991
1992 if (count < 0) {
1993 return count;
1994 }
1995
1996 total_count += count;
1997 }
1998
1999 return total_count;
2000 }
2001
2002 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
2003 {
2004 MachineClass *mc = MACHINE_CLASS(oc);
2005 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
2006 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2007 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
2008
2009 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
2010 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
2011
2012 xic->icp_get = pnv_icp_get;
2013 xic->ics_get = pnv_ics_get;
2014 xic->ics_resend = pnv_ics_resend;
2015
2016 pmc->compat = compat;
2017 pmc->compat_size = sizeof(compat);
2018
2019 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB3);
2020 }
2021
2022 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
2023 {
2024 MachineClass *mc = MACHINE_CLASS(oc);
2025 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
2026 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2027 static const char compat[] = "qemu,powernv9\0ibm,powernv";
2028
2029 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
2030 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
2031 xfc->match_nvt = pnv_match_nvt;
2032
2033 mc->alias = "powernv";
2034
2035 pmc->compat = compat;
2036 pmc->compat_size = sizeof(compat);
2037 pmc->dt_power_mgt = pnv_dt_power_mgt;
2038
2039 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB4);
2040 }
2041
2042 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
2043 {
2044 MachineClass *mc = MACHINE_CLASS(oc);
2045 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2046 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
2047 static const char compat[] = "qemu,powernv10\0ibm,powernv";
2048
2049 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
2050 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
2051
2052 pmc->compat = compat;
2053 pmc->compat_size = sizeof(compat);
2054 pmc->dt_power_mgt = pnv_dt_power_mgt;
2055
2056 xfc->match_nvt = pnv10_xive_match_nvt;
2057 }
2058
2059 static bool pnv_machine_get_hb(Object *obj, Error **errp)
2060 {
2061 PnvMachineState *pnv = PNV_MACHINE(obj);
2062
2063 return !!pnv->fw_load_addr;
2064 }
2065
2066 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp)
2067 {
2068 PnvMachineState *pnv = PNV_MACHINE(obj);
2069
2070 if (value) {
2071 pnv->fw_load_addr = 0x8000000;
2072 }
2073 }
2074
2075 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
2076 {
2077 PowerPCCPU *cpu = POWERPC_CPU(cs);
2078 CPUPPCState *env = &cpu->env;
2079
2080 cpu_synchronize_state(cs);
2081 ppc_cpu_do_system_reset(cs);
2082 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) {
2083 /*
2084 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
2085 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
2086 * (PPC_BIT(43)).
2087 */
2088 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) {
2089 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
2090 env->spr[SPR_SRR1] |= SRR1_WAKERESET;
2091 }
2092 } else {
2093 /*
2094 * For non-powersave system resets, SRR1[42:45] are defined to be
2095 * implementation-dependent. The POWER9 User Manual specifies that
2096 * an external (SCOM driven, which may come from a BMC nmi command or
2097 * another CPU requesting a NMI IPI) system reset exception should be
2098 * 0b0010 (PPC_BIT(44)).
2099 */
2100 env->spr[SPR_SRR1] |= SRR1_WAKESCOM;
2101 }
2102 }
2103
2104 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
2105 {
2106 CPUState *cs;
2107
2108 CPU_FOREACH(cs) {
2109 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
2110 }
2111 }
2112
2113 static void pnv_machine_class_init(ObjectClass *oc, void *data)
2114 {
2115 MachineClass *mc = MACHINE_CLASS(oc);
2116 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
2117 NMIClass *nc = NMI_CLASS(oc);
2118
2119 mc->desc = "IBM PowerNV (Non-Virtualized)";
2120 mc->init = pnv_init;
2121 mc->reset = pnv_reset;
2122 mc->max_cpus = MAX_CPUS;
2123 /* Pnv provides a AHCI device for storage */
2124 mc->block_default_type = IF_IDE;
2125 mc->no_parallel = 1;
2126 mc->default_boot_order = NULL;
2127 /*
2128 * RAM defaults to less than 2048 for 32-bit hosts, and large
2129 * enough to fit the maximum initrd size at it's load address
2130 */
2131 mc->default_ram_size = 1 * GiB;
2132 mc->default_ram_id = "pnv.ram";
2133 ispc->print_info = pnv_pic_print_info;
2134 nc->nmi_monitor_handler = pnv_nmi;
2135
2136 object_class_property_add_bool(oc, "hb-mode",
2137 pnv_machine_get_hb, pnv_machine_set_hb);
2138 object_class_property_set_description(oc, "hb-mode",
2139 "Use a hostboot like boot loader");
2140 }
2141
2142 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
2143 { \
2144 .name = type, \
2145 .class_init = class_initfn, \
2146 .parent = TYPE_PNV8_CHIP, \
2147 }
2148
2149 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
2150 { \
2151 .name = type, \
2152 .class_init = class_initfn, \
2153 .parent = TYPE_PNV9_CHIP, \
2154 }
2155
2156 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
2157 { \
2158 .name = type, \
2159 .class_init = class_initfn, \
2160 .parent = TYPE_PNV10_CHIP, \
2161 }
2162
2163 static const TypeInfo types[] = {
2164 {
2165 .name = MACHINE_TYPE_NAME("powernv10"),
2166 .parent = TYPE_PNV_MACHINE,
2167 .class_init = pnv_machine_power10_class_init,
2168 .interfaces = (InterfaceInfo[]) {
2169 { TYPE_XIVE_FABRIC },
2170 { },
2171 },
2172 },
2173 {
2174 .name = MACHINE_TYPE_NAME("powernv9"),
2175 .parent = TYPE_PNV_MACHINE,
2176 .class_init = pnv_machine_power9_class_init,
2177 .interfaces = (InterfaceInfo[]) {
2178 { TYPE_XIVE_FABRIC },
2179 { },
2180 },
2181 },
2182 {
2183 .name = MACHINE_TYPE_NAME("powernv8"),
2184 .parent = TYPE_PNV_MACHINE,
2185 .class_init = pnv_machine_power8_class_init,
2186 .interfaces = (InterfaceInfo[]) {
2187 { TYPE_XICS_FABRIC },
2188 { },
2189 },
2190 },
2191 {
2192 .name = TYPE_PNV_MACHINE,
2193 .parent = TYPE_MACHINE,
2194 .abstract = true,
2195 .instance_size = sizeof(PnvMachineState),
2196 .class_init = pnv_machine_class_init,
2197 .class_size = sizeof(PnvMachineClass),
2198 .interfaces = (InterfaceInfo[]) {
2199 { TYPE_INTERRUPT_STATS_PROVIDER },
2200 { TYPE_NMI },
2201 { },
2202 },
2203 },
2204 {
2205 .name = TYPE_PNV_CHIP,
2206 .parent = TYPE_SYS_BUS_DEVICE,
2207 .class_init = pnv_chip_class_init,
2208 .instance_size = sizeof(PnvChip),
2209 .class_size = sizeof(PnvChipClass),
2210 .abstract = true,
2211 },
2212
2213 /*
2214 * P10 chip and variants
2215 */
2216 {
2217 .name = TYPE_PNV10_CHIP,
2218 .parent = TYPE_PNV_CHIP,
2219 .instance_init = pnv_chip_power10_instance_init,
2220 .instance_size = sizeof(Pnv10Chip),
2221 },
2222 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
2223
2224 /*
2225 * P9 chip and variants
2226 */
2227 {
2228 .name = TYPE_PNV9_CHIP,
2229 .parent = TYPE_PNV_CHIP,
2230 .instance_init = pnv_chip_power9_instance_init,
2231 .instance_size = sizeof(Pnv9Chip),
2232 },
2233 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
2234
2235 /*
2236 * P8 chip and variants
2237 */
2238 {
2239 .name = TYPE_PNV8_CHIP,
2240 .parent = TYPE_PNV_CHIP,
2241 .instance_init = pnv_chip_power8_instance_init,
2242 .instance_size = sizeof(Pnv8Chip),
2243 },
2244 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
2245 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
2246 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
2247 pnv_chip_power8nvl_class_init),
2248 };
2249
2250 DEFINE_TYPES(types)
Random patches