hw/ppce500_pci.c

   1 /*
   2  * QEMU PowerPC E500 embedded processors pci controller emulation
   3  *
   4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author: Yu Liu,     <yu.liu@freescale.com>
   7  *
   8  * This file is derived from hw/ppc4xx_pci.c,
   9  * the copyright for that material belongs to the original owners.
  10  *
  11  * This is free software; you can redistribute it and/or modify
  12  * it under the terms of  the GNU General  Public License as published by
  13  * the Free Software Foundation;  either version 2 of the  License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include "hw/hw.h"
  18 #include "hw/ppc/e500-ccsr.h"
  19 #include "hw/pci/pci.h"
  20 #include "hw/pci/pci_host.h"
  21 #include "qemu/bswap.h"
  22 #include "hw/ppce500_pci.h"
  23
  24 #ifdef DEBUG_PCI
  25 #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
  26 #else
  27 #define pci_debug(fmt, ...)
  28 #endif
  29
  30 #define PCIE500_CFGADDR       0x0
  31 #define PCIE500_CFGDATA       0x4
  32 #define PCIE500_REG_BASE      0xC00
  33 #define PCIE500_ALL_SIZE      0x1000
  34 #define PCIE500_REG_SIZE      (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
  35
  36 #define PCIE500_PCI_IOLEN     0x10000ULL
  37
  38 #define PPCE500_PCI_CONFIG_ADDR         0x0
  39 #define PPCE500_PCI_CONFIG_DATA         0x4
  40 #define PPCE500_PCI_INTACK              0x8
  41
  42 #define PPCE500_PCI_OW1                 (0xC20 - PCIE500_REG_BASE)
  43 #define PPCE500_PCI_OW2                 (0xC40 - PCIE500_REG_BASE)
  44 #define PPCE500_PCI_OW3                 (0xC60 - PCIE500_REG_BASE)
  45 #define PPCE500_PCI_OW4                 (0xC80 - PCIE500_REG_BASE)
  46 #define PPCE500_PCI_IW3                 (0xDA0 - PCIE500_REG_BASE)
  47 #define PPCE500_PCI_IW2                 (0xDC0 - PCIE500_REG_BASE)
  48 #define PPCE500_PCI_IW1                 (0xDE0 - PCIE500_REG_BASE)
  49
  50 #define PPCE500_PCI_GASKET_TIMR         (0xE20 - PCIE500_REG_BASE)
  51
  52 #define PCI_POTAR               0x0
  53 #define PCI_POTEAR              0x4
  54 #define PCI_POWBAR              0x8
  55 #define PCI_POWAR               0x10
  56
  57 #define PCI_PITAR               0x0
  58 #define PCI_PIWBAR              0x8
  59 #define PCI_PIWBEAR             0xC
  60 #define PCI_PIWAR               0x10
  61
  62 #define PPCE500_PCI_NR_POBS     5
  63 #define PPCE500_PCI_NR_PIBS     3
  64
  65 struct  pci_outbound {
  66     uint32_t potar;
  67     uint32_t potear;
  68     uint32_t powbar;
  69     uint32_t powar;
  70 };
  71
  72 struct pci_inbound {
  73     uint32_t pitar;
  74     uint32_t piwbar;
  75     uint32_t piwbear;
  76     uint32_t piwar;
  77 };
  78
  79 #define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost"
  80
  81 #define PPC_E500_PCI_HOST_BRIDGE(obj) \
  82     OBJECT_CHECK(PPCE500PCIState, (obj), TYPE_PPC_E500_PCI_HOST_BRIDGE)
  83
  84 struct PPCE500PCIState {
  85     PCIHostState parent_obj;
  86
  87     struct pci_outbound pob[PPCE500_PCI_NR_POBS];
  88     struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
  89     uint32_t gasket_time;
  90     qemu_irq irq[4];
  91     uint32_t first_slot;
  92     /* mmio maps */
  93     MemoryRegion container;
  94     MemoryRegion iomem;
  95     MemoryRegion pio;
  96 };
  97
  98 #define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge"
  99 #define PPC_E500_PCI_BRIDGE(obj) \
 100     OBJECT_CHECK(PPCE500PCIBridgeState, (obj), TYPE_PPC_E500_PCI_BRIDGE)
 101
 102 struct PPCE500PCIBridgeState {
 103     /*< private >*/
 104     PCIDevice parent;
 105     /*< public >*/
 106
 107     MemoryRegion bar0;
 108 };
 109
 110 typedef struct PPCE500PCIBridgeState PPCE500PCIBridgeState;
 111 typedef struct PPCE500PCIState PPCE500PCIState;
 112
 113 static uint64_t pci_reg_read4(void *opaque, hwaddr addr,
 114                               unsigned size)
 115 {
 116     PPCE500PCIState *pci = opaque;
 117     unsigned long win;
 118     uint32_t value = 0;
 119     int idx;
 120
 121     win = addr & 0xfe0;
 122
 123     switch (win) {
 124     case PPCE500_PCI_OW1:
 125     case PPCE500_PCI_OW2:
 126     case PPCE500_PCI_OW3:
 127     case PPCE500_PCI_OW4:
 128         idx = (addr >> 5) & 0x7;
 129         switch (addr & 0xC) {
 130         case PCI_POTAR:
 131             value = pci->pob[idx].potar;
 132             break;
 133         case PCI_POTEAR:
 134             value = pci->pob[idx].potear;
 135             break;
 136         case PCI_POWBAR:
 137             value = pci->pob[idx].powbar;
 138             break;
 139         case PCI_POWAR:
 140             value = pci->pob[idx].powar;
 141             break;
 142         default:
 143             break;
 144         }
 145         break;
 146
 147     case PPCE500_PCI_IW3:
 148     case PPCE500_PCI_IW2:
 149     case PPCE500_PCI_IW1:
 150         idx = ((addr >> 5) & 0x3) - 1;
 151         switch (addr & 0xC) {
 152         case PCI_PITAR:
 153             value = pci->pib[idx].pitar;
 154             break;
 155         case PCI_PIWBAR:
 156             value = pci->pib[idx].piwbar;
 157             break;
 158         case PCI_PIWBEAR:
 159             value = pci->pib[idx].piwbear;
 160             break;
 161         case PCI_PIWAR:
 162             value = pci->pib[idx].piwar;
 163             break;
 164         default:
 165             break;
 166         };
 167         break;
 168
 169     case PPCE500_PCI_GASKET_TIMR:
 170         value = pci->gasket_time;
 171         break;
 172
 173     default:
 174         break;
 175     }
 176
 177     pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
 178               win, addr, value);
 179     return value;
 180 }
 181
 182 static void pci_reg_write4(void *opaque, hwaddr addr,
 183                            uint64_t value, unsigned size)
 184 {
 185     PPCE500PCIState *pci = opaque;
 186     unsigned long win;
 187     int idx;
 188
 189     win = addr & 0xfe0;
 190
 191     pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
 192               __func__, (unsigned)value, win, addr);
 193
 194     switch (win) {
 195     case PPCE500_PCI_OW1:
 196     case PPCE500_PCI_OW2:
 197     case PPCE500_PCI_OW3:
 198     case PPCE500_PCI_OW4:
 199         idx = (addr >> 5) & 0x7;
 200         switch (addr & 0xC) {
 201         case PCI_POTAR:
 202             pci->pob[idx].potar = value;
 203             break;
 204         case PCI_POTEAR:
 205             pci->pob[idx].potear = value;
 206             break;
 207         case PCI_POWBAR:
 208             pci->pob[idx].powbar = value;
 209             break;
 210         case PCI_POWAR:
 211             pci->pob[idx].powar = value;
 212             break;
 213         default:
 214             break;
 215         };
 216         break;
 217
 218     case PPCE500_PCI_IW3:
 219     case PPCE500_PCI_IW2:
 220     case PPCE500_PCI_IW1:
 221         idx = ((addr >> 5) & 0x3) - 1;
 222         switch (addr & 0xC) {
 223         case PCI_PITAR:
 224             pci->pib[idx].pitar = value;
 225             break;
 226         case PCI_PIWBAR:
 227             pci->pib[idx].piwbar = value;
 228             break;
 229         case PCI_PIWBEAR:
 230             pci->pib[idx].piwbear = value;
 231             break;
 232         case PCI_PIWAR:
 233             pci->pib[idx].piwar = value;
 234             break;
 235         default:
 236             break;
 237         };
 238         break;
 239
 240     case PPCE500_PCI_GASKET_TIMR:
 241         pci->gasket_time = value;
 242         break;
 243
 244     default:
 245         break;
 246     };
 247 }
 248
 249 static const MemoryRegionOps e500_pci_reg_ops = {
 250     .read = pci_reg_read4,
 251     .write = pci_reg_write4,
 252     .endianness = DEVICE_BIG_ENDIAN,
 253 };
 254
 255 static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
 256 {
 257     int devno = pci_dev->devfn >> 3;
 258     int ret;
 259
 260     ret = ppce500_pci_map_irq_slot(devno, irq_num);
 261
 262     pci_debug("%s: devfn %x irq %d -> %d  devno:%x\n", __func__,
 263            pci_dev->devfn, irq_num, ret, devno);
 264
 265     return ret;
 266 }
 267
 268 static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
 269 {
 270     qemu_irq *pic = opaque;
 271
 272     pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
 273
 274     qemu_set_irq(pic[irq_num], level);
 275 }
 276
 277 static const VMStateDescription vmstate_pci_outbound = {
 278     .name = "pci_outbound",
 279     .version_id = 0,
 280     .minimum_version_id = 0,
 281     .minimum_version_id_old = 0,
 282     .fields      = (VMStateField[]) {
 283         VMSTATE_UINT32(potar, struct pci_outbound),
 284         VMSTATE_UINT32(potear, struct pci_outbound),
 285         VMSTATE_UINT32(powbar, struct pci_outbound),
 286         VMSTATE_UINT32(powar, struct pci_outbound),
 287         VMSTATE_END_OF_LIST()
 288     }
 289 };
 290
 291 static const VMStateDescription vmstate_pci_inbound = {
 292     .name = "pci_inbound",
 293     .version_id = 0,
 294     .minimum_version_id = 0,
 295     .minimum_version_id_old = 0,
 296     .fields      = (VMStateField[]) {
 297         VMSTATE_UINT32(pitar, struct pci_inbound),
 298         VMSTATE_UINT32(piwbar, struct pci_inbound),
 299         VMSTATE_UINT32(piwbear, struct pci_inbound),
 300         VMSTATE_UINT32(piwar, struct pci_inbound),
 301         VMSTATE_END_OF_LIST()
 302     }
 303 };
 304
 305 static const VMStateDescription vmstate_ppce500_pci = {
 306     .name = "ppce500_pci",
 307     .version_id = 1,
 308     .minimum_version_id = 1,
 309     .minimum_version_id_old = 1,
 310     .fields      = (VMStateField[]) {
 311         VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
 312                              vmstate_pci_outbound, struct pci_outbound),
 313         VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
 314                              vmstate_pci_outbound, struct pci_inbound),
 315         VMSTATE_UINT32(gasket_time, PPCE500PCIState),
 316         VMSTATE_END_OF_LIST()
 317     }
 318 };
 319
 320 #include "exec/address-spaces.h"
 321
 322 static int e500_pcihost_bridge_initfn(PCIDevice *d)
 323 {
 324     PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d);
 325     PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(),
 326                                   "/e500-ccsr"));
 327
 328     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
 329     d->config[PCI_HEADER_TYPE] =
 330         (d->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
 331         PCI_HEADER_TYPE_BRIDGE;
 332
 333     memory_region_init_alias(&b->bar0, "e500-pci-bar0", &ccsr->ccsr_space,
 334                              0, int128_get64(ccsr->ccsr_space.size));
 335     pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0);
 336
 337     return 0;
 338 }
 339
 340 static int e500_pcihost_initfn(SysBusDevice *dev)
 341 {
 342     PCIHostState *h;
 343     PPCE500PCIState *s;
 344     PCIBus *b;
 345     int i;
 346     MemoryRegion *address_space_mem = get_system_memory();
 347
 348     h = PCI_HOST_BRIDGE(dev);
 349     s = PPC_E500_PCI_HOST_BRIDGE(dev);
 350
 351     for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
 352         sysbus_init_irq(dev, &s->irq[i]);
 353     }
 354
 355     memory_region_init(&s->pio, "pci-pio", PCIE500_PCI_IOLEN);
 356
 357     b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq,
 358                          mpc85xx_pci_map_irq, s->irq, address_space_mem,
 359                          &s->pio, PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS);
 360     h->bus = b;
 361
 362     pci_create_simple(b, 0, "e500-host-bridge");
 363
 364     memory_region_init(&s->container, "pci-container", PCIE500_ALL_SIZE);
 365     memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h,
 366                           "pci-conf-idx", 4);
 367     memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
 368                           "pci-conf-data", 4);
 369     memory_region_init_io(&s->iomem, &e500_pci_reg_ops, s,
 370                           "pci.reg", PCIE500_REG_SIZE);
 371     memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem);
 372     memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
 373     memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
 374     sysbus_init_mmio(dev, &s->container);
 375     sysbus_init_mmio(dev, &s->pio);
 376
 377     return 0;
 378 }
 379
 380 static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
 381 {
 382     DeviceClass *dc = DEVICE_CLASS(klass);
 383     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 384
 385     k->init = e500_pcihost_bridge_initfn;
 386     k->vendor_id = PCI_VENDOR_ID_FREESCALE;
 387     k->device_id = PCI_DEVICE_ID_MPC8533E;
 388     k->class_id = PCI_CLASS_PROCESSOR_POWERPC;
 389     dc->desc = "Host bridge";
 390 }
 391
 392 static const TypeInfo e500_host_bridge_info = {
 393     .name          = "e500-host-bridge",
 394     .parent        = TYPE_PCI_DEVICE,
 395     .instance_size = sizeof(PPCE500PCIBridgeState),
 396     .class_init    = e500_host_bridge_class_init,
 397 };
 398
 399 static Property pcihost_properties[] = {
 400     DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11),
 401     DEFINE_PROP_END_OF_LIST(),
 402 };
 403
 404 static void e500_pcihost_class_init(ObjectClass *klass, void *data)
 405 {
 406     DeviceClass *dc = DEVICE_CLASS(klass);
 407     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 408
 409     k->init = e500_pcihost_initfn;
 410     dc->props = pcihost_properties;
 411     dc->vmsd = &vmstate_ppce500_pci;
 412 }
 413
 414 static const TypeInfo e500_pcihost_info = {
 415     .name          = TYPE_PPC_E500_PCI_HOST_BRIDGE,
 416     .parent        = TYPE_PCI_HOST_BRIDGE,
 417     .instance_size = sizeof(PPCE500PCIState),
 418     .class_init    = e500_pcihost_class_init,
 419 };
 420
 421 static void e500_pci_register_types(void)
 422 {
 423     type_register_static(&e500_pcihost_info);
 424     type_register_static(&e500_host_bridge_info);
 425 }
 426
 427 type_init(e500_pci_register_types)