hw/lm32_sys.c

   1 /*
   2  *  QEMU model of the LatticeMico32 system control block.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /*
  21  * This model is mainly intended for testing purposes and doesn't fit to any
  22  * real hardware. On the one hand it provides a control register (R_CTRL) on
  23  * the other hand it supports the lm32 tests.
  24  *
  25  * A write to the control register causes a system shutdown.
  26  * Tests first write the pointer to a test name to the test name register
  27  * (R_TESTNAME) and then write a zero to the pass/fail register (R_PASSFAIL) if
  28  * the test is passed or any non-zero value to it if the test is failed.
  29  */
  30
  31 #include "hw/hw.h"
  32 #include "hw/sysbus.h"
  33 #include "trace.h"
  34 #include "qemu/log.h"
  35 #include "qemu/error-report.h"
  36 #include "sysemu/sysemu.h"
  37 #include "qemu/log.h"
  38
  39 enum {
  40     R_CTRL = 0,
  41     R_PASSFAIL,
  42     R_TESTNAME,
  43     R_MAX
  44 };
  45
  46 #define MAX_TESTNAME_LEN 16
  47
  48 struct LM32SysState {
  49     SysBusDevice busdev;
  50     MemoryRegion iomem;
  51     uint32_t base;
  52     uint32_t regs[R_MAX];
  53     uint8_t testname[MAX_TESTNAME_LEN];
  54 };
  55 typedef struct LM32SysState LM32SysState;
  56
  57 static void copy_testname(LM32SysState *s)
  58 {
  59     cpu_physical_memory_read(s->regs[R_TESTNAME], s->testname,
  60             MAX_TESTNAME_LEN);
  61     s->testname[MAX_TESTNAME_LEN - 1] = '\0';
  62 }
  63
  64 static void sys_write(void *opaque, hwaddr addr,
  65                       uint64_t value, unsigned size)
  66 {
  67     LM32SysState *s = opaque;
  68     char *testname;
  69
  70     trace_lm32_sys_memory_write(addr, value);
  71
  72     addr >>= 2;
  73     switch (addr) {
  74     case R_CTRL:
  75         qemu_system_shutdown_request();
  76         break;
  77     case R_PASSFAIL:
  78         s->regs[addr] = value;
  79         testname = (char *)s->testname;
  80         qemu_log("TC  %-16s %s\n", testname, (value) ? "FAILED" : "OK");
  81         break;
  82     case R_TESTNAME:
  83         s->regs[addr] = value;
  84         copy_testname(s);
  85         break;
  86
  87     default:
  88         error_report("lm32_sys: write access to unknown register 0x"
  89                 TARGET_FMT_plx, addr << 2);
  90         break;
  91     }
  92 }
  93
  94 static bool sys_ops_accepts(void *opaque, hwaddr addr,
  95                             unsigned size, bool is_write)
  96 {
  97     return is_write && size == 4;
  98 }
  99
 100 static const MemoryRegionOps sys_ops = {
 101     .write = sys_write,
 102     .valid.accepts = sys_ops_accepts,
 103     .endianness = DEVICE_NATIVE_ENDIAN,
 104 };
 105
 106 static void sys_reset(DeviceState *d)
 107 {
 108     LM32SysState *s = container_of(d, LM32SysState, busdev.qdev);
 109     int i;
 110
 111     for (i = 0; i < R_MAX; i++) {
 112         s->regs[i] = 0;
 113     }
 114     memset(s->testname, 0, MAX_TESTNAME_LEN);
 115 }
 116
 117 static int lm32_sys_init(SysBusDevice *dev)
 118 {
 119     LM32SysState *s = FROM_SYSBUS(typeof(*s), dev);
 120
 121     memory_region_init_io(&s->iomem, &sys_ops , s, "sys", R_MAX * 4);
 122     sysbus_init_mmio(dev, &s->iomem);
 123
 124     /* Note: This device is not created in the board initialization,
 125      * instead it has to be added with the -device parameter. Therefore,
 126      * the device maps itself. */
 127     sysbus_mmio_map(dev, 0, s->base);
 128
 129     return 0;
 130 }
 131
 132 static const VMStateDescription vmstate_lm32_sys = {
 133     .name = "lm32-sys",
 134     .version_id = 1,
 135     .minimum_version_id = 1,
 136     .minimum_version_id_old = 1,
 137     .fields      = (VMStateField[]) {
 138         VMSTATE_UINT32_ARRAY(regs, LM32SysState, R_MAX),
 139         VMSTATE_BUFFER(testname, LM32SysState),
 140         VMSTATE_END_OF_LIST()
 141     }
 142 };
 143
 144 static Property lm32_sys_properties[] = {
 145     DEFINE_PROP_UINT32("base", LM32SysState, base, 0xffff0000),
 146     DEFINE_PROP_END_OF_LIST(),
 147 };
 148
 149 static void lm32_sys_class_init(ObjectClass *klass, void *data)
 150 {
 151     DeviceClass *dc = DEVICE_CLASS(klass);
 152     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 153
 154     k->init = lm32_sys_init;
 155     dc->reset = sys_reset;
 156     dc->vmsd = &vmstate_lm32_sys;
 157     dc->props = lm32_sys_properties;
 158 }
 159
 160 static const TypeInfo lm32_sys_info = {
 161     .name          = "lm32-sys",
 162     .parent        = TYPE_SYS_BUS_DEVICE,
 163     .instance_size = sizeof(LM32SysState),
 164     .class_init    = lm32_sys_class_init,
 165 };
 166
 167 static void lm32_sys_register_types(void)
 168 {
 169     type_register_static(&lm32_sys_info);
 170 }
 171
 172 type_init(lm32_sys_register_types)