hw/arm_gic_common.c

   1 /*
   2  * ARM GIC support - common bits of emulated and KVM kernel model
   3  *
   4  * Copyright (c) 2012 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation, either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "hw/arm_gic_internal.h"
  22
  23 static void gic_save(QEMUFile *f, void *opaque)
  24 {
  25     GICState *s = (GICState *)opaque;
  26     ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
  27     int i;
  28     int j;
  29
  30     if (c->pre_save) {
  31         c->pre_save(s);
  32     }
  33
  34     qemu_put_be32(f, s->enabled);
  35     for (i = 0; i < s->num_cpu; i++) {
  36         qemu_put_be32(f, s->cpu_enabled[i]);
  37         for (j = 0; j < GIC_INTERNAL; j++) {
  38             qemu_put_be32(f, s->priority1[j][i]);
  39         }
  40         for (j = 0; j < s->num_irq; j++) {
  41             qemu_put_be32(f, s->last_active[j][i]);
  42         }
  43         qemu_put_be32(f, s->priority_mask[i]);
  44         qemu_put_be32(f, s->running_irq[i]);
  45         qemu_put_be32(f, s->running_priority[i]);
  46         qemu_put_be32(f, s->current_pending[i]);
  47     }
  48     for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {
  49         qemu_put_be32(f, s->priority2[i]);
  50     }
  51     for (i = 0; i < s->num_irq; i++) {
  52         qemu_put_be32(f, s->irq_target[i]);
  53         qemu_put_byte(f, s->irq_state[i].enabled);
  54         qemu_put_byte(f, s->irq_state[i].pending);
  55         qemu_put_byte(f, s->irq_state[i].active);
  56         qemu_put_byte(f, s->irq_state[i].level);
  57         qemu_put_byte(f, s->irq_state[i].model);
  58         qemu_put_byte(f, s->irq_state[i].trigger);
  59     }
  60 }
  61
  62 static int gic_load(QEMUFile *f, void *opaque, int version_id)
  63 {
  64     GICState *s = (GICState *)opaque;
  65     ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
  66     int i;
  67     int j;
  68
  69     if (version_id != 3) {
  70         return -EINVAL;
  71     }
  72
  73     s->enabled = qemu_get_be32(f);
  74     for (i = 0; i < s->num_cpu; i++) {
  75         s->cpu_enabled[i] = qemu_get_be32(f);
  76         for (j = 0; j < GIC_INTERNAL; j++) {
  77             s->priority1[j][i] = qemu_get_be32(f);
  78         }
  79         for (j = 0; j < s->num_irq; j++) {
  80             s->last_active[j][i] = qemu_get_be32(f);
  81         }
  82         s->priority_mask[i] = qemu_get_be32(f);
  83         s->running_irq[i] = qemu_get_be32(f);
  84         s->running_priority[i] = qemu_get_be32(f);
  85         s->current_pending[i] = qemu_get_be32(f);
  86     }
  87     for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {
  88         s->priority2[i] = qemu_get_be32(f);
  89     }
  90     for (i = 0; i < s->num_irq; i++) {
  91         s->irq_target[i] = qemu_get_be32(f);
  92         s->irq_state[i].enabled = qemu_get_byte(f);
  93         s->irq_state[i].pending = qemu_get_byte(f);
  94         s->irq_state[i].active = qemu_get_byte(f);
  95         s->irq_state[i].level = qemu_get_byte(f);
  96         s->irq_state[i].model = qemu_get_byte(f);
  97         s->irq_state[i].trigger = qemu_get_byte(f);
  98     }
  99
 100     if (c->post_load) {
 101         c->post_load(s);
 102     }
 103
 104     return 0;
 105 }
 106
 107 static void arm_gic_common_realize(DeviceState *dev, Error **errp)
 108 {
 109     GICState *s = ARM_GIC_COMMON(dev);
 110     int num_irq = s->num_irq;
 111
 112     if (s->num_cpu > NCPU) {
 113         error_setg(errp, "requested %u CPUs exceeds GIC maximum %d",
 114                    s->num_cpu, NCPU);
 115         return;
 116     }
 117     s->num_irq += GIC_BASE_IRQ;
 118     if (s->num_irq > GIC_MAXIRQ) {
 119         error_setg(errp,
 120                    "requested %u interrupt lines exceeds GIC maximum %d",
 121                    num_irq, GIC_MAXIRQ);
 122         return;
 123     }
 124     /* ITLinesNumber is represented as (N / 32) - 1 (see
 125      * gic_dist_readb) so this is an implementation imposed
 126      * restriction, not an architectural one:
 127      */
 128     if (s->num_irq < 32 || (s->num_irq % 32)) {
 129         error_setg(errp,
 130                    "%d interrupt lines unsupported: not divisible by 32",
 131                    num_irq);
 132         return;
 133     }
 134
 135     register_savevm(NULL, "arm_gic", -1, 3, gic_save, gic_load, s);
 136 }
 137
 138 static void arm_gic_common_reset(DeviceState *dev)
 139 {
 140     GICState *s = FROM_SYSBUS(GICState, SYS_BUS_DEVICE(dev));
 141     int i;
 142     memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
 143     for (i = 0 ; i < s->num_cpu; i++) {
 144         if (s->revision == REV_11MPCORE) {
 145             s->priority_mask[i] = 0xf0;
 146         } else {
 147             s->priority_mask[i] = 0;
 148         }
 149         s->current_pending[i] = 1023;
 150         s->running_irq[i] = 1023;
 151         s->running_priority[i] = 0x100;
 152         s->cpu_enabled[i] = 0;
 153     }
 154     for (i = 0; i < 16; i++) {
 155         GIC_SET_ENABLED(i, ALL_CPU_MASK);
 156         GIC_SET_TRIGGER(i);
 157     }
 158     if (s->num_cpu == 1) {
 159         /* For uniprocessor GICs all interrupts always target the sole CPU */
 160         for (i = 0; i < GIC_MAXIRQ; i++) {
 161             s->irq_target[i] = 1;
 162         }
 163     }
 164     s->enabled = 0;
 165 }
 166
 167 static Property arm_gic_common_properties[] = {
 168     DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1),
 169     DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32),
 170     /* Revision can be 1 or 2 for GIC architecture specification
 171      * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC.
 172      * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".)
 173      */
 174     DEFINE_PROP_UINT32("revision", GICState, revision, 1),
 175     DEFINE_PROP_END_OF_LIST(),
 176 };
 177
 178 static void arm_gic_common_class_init(ObjectClass *klass, void *data)
 179 {
 180     DeviceClass *dc = DEVICE_CLASS(klass);
 181
 182     dc->reset = arm_gic_common_reset;
 183     dc->realize = arm_gic_common_realize;
 184     dc->props = arm_gic_common_properties;
 185     dc->no_user = 1;
 186 }
 187
 188 static const TypeInfo arm_gic_common_type = {
 189     .name = TYPE_ARM_GIC_COMMON,
 190     .parent = TYPE_SYS_BUS_DEVICE,
 191     .instance_size = sizeof(GICState),
 192     .class_size = sizeof(ARMGICCommonClass),
 193     .class_init = arm_gic_common_class_init,
 194     .abstract = true,
 195 };
 196
 197 static void register_types(void)
 198 {
 199     type_register_static(&arm_gic_common_type);
 200 }
 201
 202 type_init(register_types)