linux-headers/asm-arm64/kvm.h

   1 /*
   2  * Copyright (C) 2012,2013 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * Derived from arch/arm/include/uapi/asm/kvm.h:
   6  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
   7  * Author: Christoffer Dall <c.dall@virtualopensystems.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #ifndef __ARM_KVM_H__
  23 #define __ARM_KVM_H__
  24
  25 #define KVM_SPSR_EL1    0
  26 #define KVM_SPSR_SVC    KVM_SPSR_EL1
  27 #define KVM_SPSR_ABT    1
  28 #define KVM_SPSR_UND    2
  29 #define KVM_SPSR_IRQ    3
  30 #define KVM_SPSR_FIQ    4
  31 #define KVM_NR_SPSR     5
  32
  33 #ifndef __ASSEMBLY__
  34 #include <linux/psci.h>
  35 #include <asm/types.h>
  36 #include <asm/ptrace.h>
  37
  38 #define __KVM_HAVE_GUEST_DEBUG
  39 #define __KVM_HAVE_IRQ_LINE
  40
  41 #define KVM_REG_SIZE(id)                                                \
  42         (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
  43
  44 struct kvm_regs {
  45         struct user_pt_regs regs;       /* sp = sp_el0 */
  46
  47         __u64   sp_el1;
  48         __u64   elr_el1;
  49
  50         __u64   spsr[KVM_NR_SPSR];
  51
  52         struct user_fpsimd_state fp_regs;
  53 };
  54
  55 /* Supported Processor Types */
  56 #define KVM_ARM_TARGET_AEM_V8           0
  57 #define KVM_ARM_TARGET_FOUNDATION_V8    1
  58 #define KVM_ARM_TARGET_CORTEX_A57       2
  59 #define KVM_ARM_TARGET_XGENE_POTENZA    3
  60 #define KVM_ARM_TARGET_CORTEX_A53       4
  61
  62 #define KVM_ARM_NUM_TARGETS             5
  63
  64 /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
  65 #define KVM_ARM_DEVICE_TYPE_SHIFT       0
  66 #define KVM_ARM_DEVICE_TYPE_MASK        (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
  67 #define KVM_ARM_DEVICE_ID_SHIFT         16
  68 #define KVM_ARM_DEVICE_ID_MASK          (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
  69
  70 /* Supported device IDs */
  71 #define KVM_ARM_DEVICE_VGIC_V2          0
  72
  73 /* Supported VGIC address types  */
  74 #define KVM_VGIC_V2_ADDR_TYPE_DIST      0
  75 #define KVM_VGIC_V2_ADDR_TYPE_CPU       1
  76
  77 #define KVM_VGIC_V2_DIST_SIZE           0x1000
  78 #define KVM_VGIC_V2_CPU_SIZE            0x2000
  79
  80 #define KVM_ARM_VCPU_POWER_OFF          0 /* CPU is started in OFF state */
  81 #define KVM_ARM_VCPU_EL1_32BIT          1 /* CPU running a 32bit VM */
  82 #define KVM_ARM_VCPU_PSCI_0_2           2 /* CPU uses PSCI v0.2 */
  83
  84 struct kvm_vcpu_init {
  85         __u32 target;
  86         __u32 features[7];
  87 };
  88
  89 struct kvm_sregs {
  90 };
  91
  92 struct kvm_fpu {
  93 };
  94
  95 struct kvm_guest_debug_arch {
  96 };
  97
  98 struct kvm_debug_exit_arch {
  99 };
 100
 101 struct kvm_sync_regs {
 102 };
 103
 104 struct kvm_arch_memory_slot {
 105 };
 106
 107 /* If you need to interpret the index values, here is the key: */
 108 #define KVM_REG_ARM_COPROC_MASK         0x000000000FFF0000
 109 #define KVM_REG_ARM_COPROC_SHIFT        16
 110
 111 /* Normal registers are mapped as coprocessor 16. */
 112 #define KVM_REG_ARM_CORE                (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
 113 #define KVM_REG_ARM_CORE_REG(name)      (offsetof(struct kvm_regs, name) / sizeof(__u32))
 114
 115 /* Some registers need more space to represent values. */
 116 #define KVM_REG_ARM_DEMUX               (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
 117 #define KVM_REG_ARM_DEMUX_ID_MASK       0x000000000000FF00
 118 #define KVM_REG_ARM_DEMUX_ID_SHIFT      8
 119 #define KVM_REG_ARM_DEMUX_ID_CCSIDR     (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
 120 #define KVM_REG_ARM_DEMUX_VAL_MASK      0x00000000000000FF
 121 #define KVM_REG_ARM_DEMUX_VAL_SHIFT     0
 122
 123 /* AArch64 system registers */
 124 #define KVM_REG_ARM64_SYSREG            (0x0013 << KVM_REG_ARM_COPROC_SHIFT)
 125 #define KVM_REG_ARM64_SYSREG_OP0_MASK   0x000000000000c000
 126 #define KVM_REG_ARM64_SYSREG_OP0_SHIFT  14
 127 #define KVM_REG_ARM64_SYSREG_OP1_MASK   0x0000000000003800
 128 #define KVM_REG_ARM64_SYSREG_OP1_SHIFT  11
 129 #define KVM_REG_ARM64_SYSREG_CRN_MASK   0x0000000000000780
 130 #define KVM_REG_ARM64_SYSREG_CRN_SHIFT  7
 131 #define KVM_REG_ARM64_SYSREG_CRM_MASK   0x0000000000000078
 132 #define KVM_REG_ARM64_SYSREG_CRM_SHIFT  3
 133 #define KVM_REG_ARM64_SYSREG_OP2_MASK   0x0000000000000007
 134 #define KVM_REG_ARM64_SYSREG_OP2_SHIFT  0
 135
 136 #define ARM64_SYS_REG_SHIFT_MASK(x,n) \
 137         (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \
 138         KVM_REG_ARM64_SYSREG_ ## n ## _MASK)
 139
 140 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
 141         (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \
 142         ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
 143         ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
 144         ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
 145         ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
 146         ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
 147
 148 #define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)
 149
 150 #define KVM_REG_ARM_TIMER_CTL           ARM64_SYS_REG(3, 3, 14, 3, 1)
 151 #define KVM_REG_ARM_TIMER_CNT           ARM64_SYS_REG(3, 3, 14, 3, 2)
 152 #define KVM_REG_ARM_TIMER_CVAL          ARM64_SYS_REG(3, 3, 14, 0, 2)
 153
 154 /* Device Control API: ARM VGIC */
 155 #define KVM_DEV_ARM_VGIC_GRP_ADDR       0
 156 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS  1
 157 #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS   2
 158 #define   KVM_DEV_ARM_VGIC_CPUID_SHIFT  32
 159 #define   KVM_DEV_ARM_VGIC_CPUID_MASK   (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
 160 #define   KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
 161 #define   KVM_DEV_ARM_VGIC_OFFSET_MASK  (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
 162
 163 /* KVM_IRQ_LINE irq field index values */
 164 #define KVM_ARM_IRQ_TYPE_SHIFT          24
 165 #define KVM_ARM_IRQ_TYPE_MASK           0xff
 166 #define KVM_ARM_IRQ_VCPU_SHIFT          16
 167 #define KVM_ARM_IRQ_VCPU_MASK           0xff
 168 #define KVM_ARM_IRQ_NUM_SHIFT           0
 169 #define KVM_ARM_IRQ_NUM_MASK            0xffff
 170
 171 /* irq_type field */
 172 #define KVM_ARM_IRQ_TYPE_CPU            0
 173 #define KVM_ARM_IRQ_TYPE_SPI            1
 174 #define KVM_ARM_IRQ_TYPE_PPI            2
 175
 176 /* out-of-kernel GIC cpu interrupt injection irq_number field */
 177 #define KVM_ARM_IRQ_CPU_IRQ             0
 178 #define KVM_ARM_IRQ_CPU_FIQ             1
 179
 180 /* Highest supported SPI, from VGIC_NR_IRQS */
 181 #define KVM_ARM_IRQ_GIC_MAX             127
 182
 183 /* PSCI interface */
 184 #define KVM_PSCI_FN_BASE                0x95c1ba5e
 185 #define KVM_PSCI_FN(n)                  (KVM_PSCI_FN_BASE + (n))
 186
 187 #define KVM_PSCI_FN_CPU_SUSPEND         KVM_PSCI_FN(0)
 188 #define KVM_PSCI_FN_CPU_OFF             KVM_PSCI_FN(1)
 189 #define KVM_PSCI_FN_CPU_ON              KVM_PSCI_FN(2)
 190 #define KVM_PSCI_FN_MIGRATE             KVM_PSCI_FN(3)
 191
 192 #define KVM_PSCI_RET_SUCCESS            PSCI_RET_SUCCESS
 193 #define KVM_PSCI_RET_NI                 PSCI_RET_NOT_SUPPORTED
 194 #define KVM_PSCI_RET_INVAL              PSCI_RET_INVALID_PARAMS
 195 #define KVM_PSCI_RET_DENIED             PSCI_RET_DENIED
 196
 197 #endif
 198
 199 #endif /* __ARM_KVM_H__ */