?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
migration-test: Make sure that multifd and cancel works
[qemu/kevin.git] / target / mips / op_helper.c
blob79d44da6fadf7a6d5a315e73c416a40400454b2b
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu/main-loop.h"
21 #include "cpu.h"
22 #include "internal.h"
23 #include "qemu/host-utils.h"
24 #include "exec/helper-proto.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
27 #include "exec/memop.h"
28 #include "sysemu/kvm.h"
29 #include "fpu/softfloat.h"
30
31 /*****************************************************************************/
32 /* Exceptions processing helpers */
33
34 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
35 int error_code)
36 {
37 do_raise_exception_err(env, exception, error_code, 0);
38 }
39
40 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
41 {
42 do_raise_exception(env, exception, GETPC());
43 }
44
45 void helper_raise_exception_debug(CPUMIPSState *env)
46 {
47 do_raise_exception(env, EXCP_DEBUG, 0);
48 }
49
50 static void raise_exception(CPUMIPSState *env, uint32_t exception)
51 {
52 do_raise_exception(env, exception, 0);
53 }
54
55 /* 64 bits arithmetic for 32 bits hosts */
56 static inline uint64_t get_HILO(CPUMIPSState *env)
57 {
58 return ((uint64_t)(env->active_tc.HI[0]) << 32) |
59 (uint32_t)env->active_tc.LO[0];
60 }
61
62 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
63 {
64 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
65 return env->active_tc.HI[0] = (int32_t)(HILO >> 32);
66 }
67
68 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
69 {
70 target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
71 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
72 return tmp;
73 }
74
75 /* Multiplication variants of the vr54xx. */
76 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
77 target_ulong arg2)
78 {
79 return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
80 (int64_t)(int32_t)arg2));
81 }
82
83 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
84 target_ulong arg2)
85 {
86 return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
87 (uint64_t)(uint32_t)arg2);
88 }
89
90 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
91 target_ulong arg2)
92 {
93 return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
94 (int64_t)(int32_t)arg2);
95 }
96
97 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
98 target_ulong arg2)
99 {
100 return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
101 (int64_t)(int32_t)arg2);
102 }
103
104 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
105 target_ulong arg2)
106 {
107 return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
108 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
109 }
110
111 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
112 target_ulong arg2)
113 {
114 return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
115 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
116 }
117
118 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
119 target_ulong arg2)
120 {
121 return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
122 (int64_t)(int32_t)arg2);
123 }
124
125 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
126 target_ulong arg2)
127 {
128 return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
129 (int64_t)(int32_t)arg2);
130 }
131
132 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
133 target_ulong arg2)
134 {
135 return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
136 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
137 }
138
139 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
140 target_ulong arg2)
141 {
142 return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
143 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
144 }
145
146 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
147 target_ulong arg2)
148 {
149 return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
150 }
151
152 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
153 target_ulong arg2)
154 {
155 return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
156 (uint64_t)(uint32_t)arg2);
157 }
158
159 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
160 target_ulong arg2)
161 {
162 return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
163 (int64_t)(int32_t)arg2);
164 }
165
166 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
167 target_ulong arg2)
168 {
169 return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
170 (uint64_t)(uint32_t)arg2);
171 }
172
173 static inline target_ulong bitswap(target_ulong v)
174 {
175 v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
176 ((v & (target_ulong)0x5555555555555555ULL) << 1);
177 v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
178 ((v & (target_ulong)0x3333333333333333ULL) << 2);
179 v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
180 ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
181 return v;
182 }
183
184 #ifdef TARGET_MIPS64
185 target_ulong helper_dbitswap(target_ulong rt)
186 {
187 return bitswap(rt);
188 }
189 #endif
190
191 target_ulong helper_bitswap(target_ulong rt)
192 {
193 return (int32_t)bitswap(rt);
194 }
195
196 target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx,
197 uint32_t stripe)
198 {
199 int i;
200 uint64_t tmp0 = ((uint64_t)rs) << 32 | ((uint64_t)rs & 0xffffffff);
201 uint64_t tmp1 = tmp0;
202 for (i = 0; i <= 46; i++) {
203 int s;
204 if (i & 0x8) {
205 s = shift;
206 } else {
207 s = shiftx;
208 }
209
210 if (stripe != 0 && !(i & 0x4)) {
211 s = ~s;
212 }
213 if (s & 0x10) {
214 if (tmp0 & (1LL << (i + 16))) {
215 tmp1 |= 1LL << i;
216 } else {
217 tmp1 &= ~(1LL << i);
218 }
219 }
220 }
221
222 uint64_t tmp2 = tmp1;
223 for (i = 0; i <= 38; i++) {
224 int s;
225 if (i & 0x4) {
226 s = shift;
227 } else {
228 s = shiftx;
229 }
230
231 if (s & 0x8) {
232 if (tmp1 & (1LL << (i + 8))) {
233 tmp2 |= 1LL << i;
234 } else {
235 tmp2 &= ~(1LL << i);
236 }
237 }
238 }
239
240 uint64_t tmp3 = tmp2;
241 for (i = 0; i <= 34; i++) {
242 int s;
243 if (i & 0x2) {
244 s = shift;
245 } else {
246 s = shiftx;
247 }
248 if (s & 0x4) {
249 if (tmp2 & (1LL << (i + 4))) {
250 tmp3 |= 1LL << i;
251 } else {
252 tmp3 &= ~(1LL << i);
253 }
254 }
255 }
256
257 uint64_t tmp4 = tmp3;
258 for (i = 0; i <= 32; i++) {
259 int s;
260 if (i & 0x1) {
261 s = shift;
262 } else {
263 s = shiftx;
264 }
265 if (s & 0x2) {
266 if (tmp3 & (1LL << (i + 2))) {
267 tmp4 |= 1LL << i;
268 } else {
269 tmp4 &= ~(1LL << i);
270 }
271 }
272 }
273
274 uint64_t tmp5 = tmp4;
275 for (i = 0; i <= 31; i++) {
276 int s;
277 s = shift;
278 if (s & 0x1) {
279 if (tmp4 & (1LL << (i + 1))) {
280 tmp5 |= 1LL << i;
281 } else {
282 tmp5 &= ~(1LL << i);
283 }
284 }
285 }
286
287 return (int64_t)(int32_t)(uint32_t)tmp5;
288 }
289
290 #ifndef CONFIG_USER_ONLY
291
292 static inline hwaddr do_translate_address(CPUMIPSState *env,
293 target_ulong address,
294 int rw, uintptr_t retaddr)
295 {
296 hwaddr paddr;
297 CPUState *cs = env_cpu(env);
298
299 paddr = cpu_mips_translate_address(env, address, rw);
300
301 if (paddr == -1LL) {
302 cpu_loop_exit_restore(cs, retaddr);
303 } else {
304 return paddr;
305 }
306 }
307
308 #define HELPER_LD_ATOMIC(name, insn, almask) \
309 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
310 { \
311 if (arg & almask) { \
312 if (!(env->hflags & MIPS_HFLAG_DM)) { \
313 env->CP0_BadVAddr = arg; \
314 } \
315 do_raise_exception(env, EXCP_AdEL, GETPC()); \
316 } \
317 env->CP0_LLAddr = do_translate_address(env, arg, 0, GETPC()); \
318 env->lladdr = arg; \
319 env->llval = cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC()); \
320 return env->llval; \
321 }
322 HELPER_LD_ATOMIC(ll, ldl, 0x3)
323 #ifdef TARGET_MIPS64
324 HELPER_LD_ATOMIC(lld, ldq, 0x7)
325 #endif
326 #undef HELPER_LD_ATOMIC
327 #endif
328
329 #ifdef TARGET_WORDS_BIGENDIAN
330 #define GET_LMASK(v) ((v) & 3)
331 #define GET_OFFSET(addr, offset) (addr + (offset))
332 #else
333 #define GET_LMASK(v) (((v) & 3) ^ 3)
334 #define GET_OFFSET(addr, offset) (addr - (offset))
335 #endif
336
337 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
338 int mem_idx)
339 {
340 cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
341
342 if (GET_LMASK(arg2) <= 2) {
343 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16),
344 mem_idx, GETPC());
345 }
346
347 if (GET_LMASK(arg2) <= 1) {
348 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8),
349 mem_idx, GETPC());
350 }
351
352 if (GET_LMASK(arg2) == 0) {
353 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1,
354 mem_idx, GETPC());
355 }
356 }
357
358 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
359 int mem_idx)
360 {
361 cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
362
363 if (GET_LMASK(arg2) >= 1) {
364 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8),
365 mem_idx, GETPC());
366 }
367
368 if (GET_LMASK(arg2) >= 2) {
369 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16),
370 mem_idx, GETPC());
371 }
372
373 if (GET_LMASK(arg2) == 3) {
374 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24),
375 mem_idx, GETPC());
376 }
377 }
378
379 #if defined(TARGET_MIPS64)
380 /*
381 * "half" load and stores. We must do the memory access inline,
382 * or fault handling won't work.
383 */
384 #ifdef TARGET_WORDS_BIGENDIAN
385 #define GET_LMASK64(v) ((v) & 7)
386 #else
387 #define GET_LMASK64(v) (((v) & 7) ^ 7)
388 #endif
389
390 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
391 int mem_idx)
392 {
393 cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
394
395 if (GET_LMASK64(arg2) <= 6) {
396 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48),
397 mem_idx, GETPC());
398 }
399
400 if (GET_LMASK64(arg2) <= 5) {
401 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40),
402 mem_idx, GETPC());
403 }
404
405 if (GET_LMASK64(arg2) <= 4) {
406 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32),
407 mem_idx, GETPC());
408 }
409
410 if (GET_LMASK64(arg2) <= 3) {
411 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24),
412 mem_idx, GETPC());
413 }
414
415 if (GET_LMASK64(arg2) <= 2) {
416 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16),
417 mem_idx, GETPC());
418 }
419
420 if (GET_LMASK64(arg2) <= 1) {
421 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8),
422 mem_idx, GETPC());
423 }
424
425 if (GET_LMASK64(arg2) <= 0) {
426 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 7), (uint8_t)arg1,
427 mem_idx, GETPC());
428 }
429 }
430
431 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
432 int mem_idx)
433 {
434 cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
435
436 if (GET_LMASK64(arg2) >= 1) {
437 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8),
438 mem_idx, GETPC());
439 }
440
441 if (GET_LMASK64(arg2) >= 2) {
442 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16),
443 mem_idx, GETPC());
444 }
445
446 if (GET_LMASK64(arg2) >= 3) {
447 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24),
448 mem_idx, GETPC());
449 }
450
451 if (GET_LMASK64(arg2) >= 4) {
452 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32),
453 mem_idx, GETPC());
454 }
455
456 if (GET_LMASK64(arg2) >= 5) {
457 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40),
458 mem_idx, GETPC());
459 }
460
461 if (GET_LMASK64(arg2) >= 6) {
462 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48),
463 mem_idx, GETPC());
464 }
465
466 if (GET_LMASK64(arg2) == 7) {
467 cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56),
468 mem_idx, GETPC());
469 }
470 }
471 #endif /* TARGET_MIPS64 */
472
473 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
474
475 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
476 uint32_t mem_idx)
477 {
478 target_ulong base_reglist = reglist & 0xf;
479 target_ulong do_r31 = reglist & 0x10;
480
481 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
482 target_ulong i;
483
484 for (i = 0; i < base_reglist; i++) {
485 env->active_tc.gpr[multiple_regs[i]] =
486 (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());
487 addr += 4;
488 }
489 }
490
491 if (do_r31) {
492 env->active_tc.gpr[31] =
493 (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC());
494 }
495 }
496
497 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
498 uint32_t mem_idx)
499 {
500 target_ulong base_reglist = reglist & 0xf;
501 target_ulong do_r31 = reglist & 0x10;
502
503 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
504 target_ulong i;
505
506 for (i = 0; i < base_reglist; i++) {
507 cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],
508 mem_idx, GETPC());
509 addr += 4;
510 }
511 }
512
513 if (do_r31) {
514 cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
515 }
516 }
517
518 #if defined(TARGET_MIPS64)
519 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
520 uint32_t mem_idx)
521 {
522 target_ulong base_reglist = reglist & 0xf;
523 target_ulong do_r31 = reglist & 0x10;
524
525 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
526 target_ulong i;
527
528 for (i = 0; i < base_reglist; i++) {
529 env->active_tc.gpr[multiple_regs[i]] =
530 cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC());
531 addr += 8;
532 }
533 }
534
535 if (do_r31) {
536 env->active_tc.gpr[31] =
537 cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC());
538 }
539 }
540
541 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
542 uint32_t mem_idx)
543 {
544 target_ulong base_reglist = reglist & 0xf;
545 target_ulong do_r31 = reglist & 0x10;
546
547 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
548 target_ulong i;
549
550 for (i = 0; i < base_reglist; i++) {
551 cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],
552 mem_idx, GETPC());
553 addr += 8;
554 }
555 }
556
557 if (do_r31) {
558 cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
559 }
560 }
561 #endif
562
563 #ifndef CONFIG_USER_ONLY
564 /* SMP helpers. */
565 static bool mips_vpe_is_wfi(MIPSCPU *c)
566 {
567 CPUState *cpu = CPU(c);
568 CPUMIPSState *env = &c->env;
569
570 /*
571 * If the VPE is halted but otherwise active, it means it's waiting for
572 * an interrupt.\
573 */
574 return cpu->halted && mips_vpe_active(env);
575 }
576
577 static bool mips_vp_is_wfi(MIPSCPU *c)
578 {
579 CPUState *cpu = CPU(c);
580 CPUMIPSState *env = &c->env;
581
582 return cpu->halted && mips_vp_active(env);
583 }
584
585 static inline void mips_vpe_wake(MIPSCPU *c)
586 {
587 /*
588 * Don't set ->halted = 0 directly, let it be done via cpu_has_work
589 * because there might be other conditions that state that c should
590 * be sleeping.
591 */
592 qemu_mutex_lock_iothread();
593 cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
594 qemu_mutex_unlock_iothread();
595 }
596
597 static inline void mips_vpe_sleep(MIPSCPU *cpu)
598 {
599 CPUState *cs = CPU(cpu);
600
601 /*
602 * The VPE was shut off, really go to bed.
603 * Reset any old _WAKE requests.
604 */
605 cs->halted = 1;
606 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
607 }
608
609 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
610 {
611 CPUMIPSState *c = &cpu->env;
612
613 /* FIXME: TC reschedule. */
614 if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
615 mips_vpe_wake(cpu);
616 }
617 }
618
619 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
620 {
621 CPUMIPSState *c = &cpu->env;
622
623 /* FIXME: TC reschedule. */
624 if (!mips_vpe_active(c)) {
625 mips_vpe_sleep(cpu);
626 }
627 }
628
629 /**
630 * mips_cpu_map_tc:
631 * @env: CPU from which mapping is performed.
632 * @tc: Should point to an int with the value of the global TC index.
633 *
634 * This function will transform @tc into a local index within the
635 * returned #CPUMIPSState.
636 */
637
638 /*
639 * FIXME: This code assumes that all VPEs have the same number of TCs,
640 * which depends on runtime setup. Can probably be fixed by
641 * walking the list of CPUMIPSStates.
642 */
643 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
644 {
645 MIPSCPU *cpu;
646 CPUState *cs;
647 CPUState *other_cs;
648 int vpe_idx;
649 int tc_idx = *tc;
650
651 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
652 /* Not allowed to address other CPUs. */
653 *tc = env->current_tc;
654 return env;
655 }
656
657 cs = env_cpu(env);
658 vpe_idx = tc_idx / cs->nr_threads;
659 *tc = tc_idx % cs->nr_threads;
660 other_cs = qemu_get_cpu(vpe_idx);
661 if (other_cs == NULL) {
662 return env;
663 }
664 cpu = MIPS_CPU(other_cs);
665 return &cpu->env;
666 }
667
668 /*
669 * The per VPE CP0_Status register shares some fields with the per TC
670 * CP0_TCStatus registers. These fields are wired to the same registers,
671 * so changes to either of them should be reflected on both registers.
672 *
673 * Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
674 *
675 * These helper call synchronizes the regs for a given cpu.
676 */
677
678 /*
679 * Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c.
680 * static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
681 * int tc);
682 */
683
684 /* Called for updates to CP0_TCStatus. */
685 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
686 target_ulong v)
687 {
688 uint32_t status;
689 uint32_t tcu, tmx, tasid, tksu;
690 uint32_t mask = ((1U << CP0St_CU3)
691 | (1 << CP0St_CU2)
692 | (1 << CP0St_CU1)
693 | (1 << CP0St_CU0)
694 | (1 << CP0St_MX)
695 | (3 << CP0St_KSU));
696
697 tcu = (v >> CP0TCSt_TCU0) & 0xf;
698 tmx = (v >> CP0TCSt_TMX) & 0x1;
699 tasid = v & cpu->CP0_EntryHi_ASID_mask;
700 tksu = (v >> CP0TCSt_TKSU) & 0x3;
701
702 status = tcu << CP0St_CU0;
703 status |= tmx << CP0St_MX;
704 status |= tksu << CP0St_KSU;
705
706 cpu->CP0_Status &= ~mask;
707 cpu->CP0_Status |= status;
708
709 /* Sync the TASID with EntryHi. */
710 cpu->CP0_EntryHi &= ~cpu->CP0_EntryHi_ASID_mask;
711 cpu->CP0_EntryHi |= tasid;
712
713 compute_hflags(cpu);
714 }
715
716 /* Called for updates to CP0_EntryHi. */
717 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
718 {
719 int32_t *tcst;
720 uint32_t asid, v = cpu->CP0_EntryHi;
721
722 asid = v & cpu->CP0_EntryHi_ASID_mask;
723
724 if (tc == cpu->current_tc) {
725 tcst = &cpu->active_tc.CP0_TCStatus;
726 } else {
727 tcst = &cpu->tcs[tc].CP0_TCStatus;
728 }
729
730 *tcst &= ~cpu->CP0_EntryHi_ASID_mask;
731 *tcst |= asid;
732 }
733
734 /* CP0 helpers */
735 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
736 {
737 return env->mvp->CP0_MVPControl;
738 }
739
740 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
741 {
742 return env->mvp->CP0_MVPConf0;
743 }
744
745 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
746 {
747 return env->mvp->CP0_MVPConf1;
748 }
749
750 target_ulong helper_mfc0_random(CPUMIPSState *env)
751 {
752 return (int32_t)cpu_mips_get_random(env);
753 }
754
755 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
756 {
757 return env->active_tc.CP0_TCStatus;
758 }
759
760 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
761 {
762 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
763 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
764
765 if (other_tc == other->current_tc) {
766 return other->active_tc.CP0_TCStatus;
767 } else {
768 return other->tcs[other_tc].CP0_TCStatus;
769 }
770 }
771
772 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
773 {
774 return env->active_tc.CP0_TCBind;
775 }
776
777 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
778 {
779 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
780 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
781
782 if (other_tc == other->current_tc) {
783 return other->active_tc.CP0_TCBind;
784 } else {
785 return other->tcs[other_tc].CP0_TCBind;
786 }
787 }
788
789 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
790 {
791 return env->active_tc.PC;
792 }
793
794 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
795 {
796 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
797 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
798
799 if (other_tc == other->current_tc) {
800 return other->active_tc.PC;
801 } else {
802 return other->tcs[other_tc].PC;
803 }
804 }
805
806 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
807 {
808 return env->active_tc.CP0_TCHalt;
809 }
810
811 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
812 {
813 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
814 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
815
816 if (other_tc == other->current_tc) {
817 return other->active_tc.CP0_TCHalt;
818 } else {
819 return other->tcs[other_tc].CP0_TCHalt;
820 }
821 }
822
823 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
824 {
825 return env->active_tc.CP0_TCContext;
826 }
827
828 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
829 {
830 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
831 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
832
833 if (other_tc == other->current_tc) {
834 return other->active_tc.CP0_TCContext;
835 } else {
836 return other->tcs[other_tc].CP0_TCContext;
837 }
838 }
839
840 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
841 {
842 return env->active_tc.CP0_TCSchedule;
843 }
844
845 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
846 {
847 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
848 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
849
850 if (other_tc == other->current_tc) {
851 return other->active_tc.CP0_TCSchedule;
852 } else {
853 return other->tcs[other_tc].CP0_TCSchedule;
854 }
855 }
856
857 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
858 {
859 return env->active_tc.CP0_TCScheFBack;
860 }
861
862 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
863 {
864 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
865 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
866
867 if (other_tc == other->current_tc) {
868 return other->active_tc.CP0_TCScheFBack;
869 } else {
870 return other->tcs[other_tc].CP0_TCScheFBack;
871 }
872 }
873
874 target_ulong helper_mfc0_count(CPUMIPSState *env)
875 {
876 return (int32_t)cpu_mips_get_count(env);
877 }
878
879 target_ulong helper_mfc0_saar(CPUMIPSState *env)
880 {
881 if ((env->CP0_SAARI & 0x3f) < 2) {
882 return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f];
883 }
884 return 0;
885 }
886
887 target_ulong helper_mfhc0_saar(CPUMIPSState *env)
888 {
889 if ((env->CP0_SAARI & 0x3f) < 2) {
890 return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32;
891 }
892 return 0;
893 }
894
895 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
896 {
897 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
898 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
899
900 return other->CP0_EntryHi;
901 }
902
903 target_ulong helper_mftc0_cause(CPUMIPSState *env)
904 {
905 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
906 int32_t tccause;
907 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
908
909 if (other_tc == other->current_tc) {
910 tccause = other->CP0_Cause;
911 } else {
912 tccause = other->CP0_Cause;
913 }
914
915 return tccause;
916 }
917
918 target_ulong helper_mftc0_status(CPUMIPSState *env)
919 {
920 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
921 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
922
923 return other->CP0_Status;
924 }
925
926 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
927 {
928 return (int32_t)(env->CP0_LLAddr >> env->CP0_LLAddr_shift);
929 }
930
931 target_ulong helper_mfc0_maar(CPUMIPSState *env)
932 {
933 return (int32_t) env->CP0_MAAR[env->CP0_MAARI];
934 }
935
936 target_ulong helper_mfhc0_maar(CPUMIPSState *env)
937 {
938 return env->CP0_MAAR[env->CP0_MAARI] >> 32;
939 }
940
941 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
942 {
943 return (int32_t)env->CP0_WatchLo[sel];
944 }
945
946 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
947 {
948 return env->CP0_WatchHi[sel];
949 }
950
951 target_ulong helper_mfc0_debug(CPUMIPSState *env)
952 {
953 target_ulong t0 = env->CP0_Debug;
954 if (env->hflags & MIPS_HFLAG_DM) {
955 t0 |= 1 << CP0DB_DM;
956 }
957
958 return t0;
959 }
960
961 target_ulong helper_mftc0_debug(CPUMIPSState *env)
962 {
963 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
964 int32_t tcstatus;
965 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
966
967 if (other_tc == other->current_tc) {
968 tcstatus = other->active_tc.CP0_Debug_tcstatus;
969 } else {
970 tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
971 }
972
973 /* XXX: Might be wrong, check with EJTAG spec. */
974 return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
975 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
976 }
977
978 #if defined(TARGET_MIPS64)
979 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
980 {
981 return env->active_tc.PC;
982 }
983
984 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
985 {
986 return env->active_tc.CP0_TCHalt;
987 }
988
989 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
990 {
991 return env->active_tc.CP0_TCContext;
992 }
993
994 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
995 {
996 return env->active_tc.CP0_TCSchedule;
997 }
998
999 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
1000 {
1001 return env->active_tc.CP0_TCScheFBack;
1002 }
1003
1004 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
1005 {
1006 return env->CP0_LLAddr >> env->CP0_LLAddr_shift;
1007 }
1008
1009 target_ulong helper_dmfc0_maar(CPUMIPSState *env)
1010 {
1011 return env->CP0_MAAR[env->CP0_MAARI];
1012 }
1013
1014 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
1015 {
1016 return env->CP0_WatchLo[sel];
1017 }
1018
1019 target_ulong helper_dmfc0_saar(CPUMIPSState *env)
1020 {
1021 if ((env->CP0_SAARI & 0x3f) < 2) {
1022 return env->CP0_SAAR[env->CP0_SAARI & 0x3f];
1023 }
1024 return 0;
1025 }
1026 #endif /* TARGET_MIPS64 */
1027
1028 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
1029 {
1030 uint32_t index_p = env->CP0_Index & 0x80000000;
1031 uint32_t tlb_index = arg1 & 0x7fffffff;
1032 if (tlb_index < env->tlb->nb_tlb) {
1033 if (env->insn_flags & ISA_MIPS32R6) {
1034 index_p |= arg1 & 0x80000000;
1035 }
1036 env->CP0_Index = index_p | tlb_index;
1037 }
1038 }
1039
1040 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
1041 {
1042 uint32_t mask = 0;
1043 uint32_t newval;
1044
1045 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1046 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
1047 (1 << CP0MVPCo_EVP);
1048 }
1049 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
1050 mask |= (1 << CP0MVPCo_STLB);
1051 }
1052 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
1053
1054 /* TODO: Enable/disable shared TLB, enable/disable VPEs. */
1055
1056 env->mvp->CP0_MVPControl = newval;
1057 }
1058
1059 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1060 {
1061 uint32_t mask;
1062 uint32_t newval;
1063
1064 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1065 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1066 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
1067
1068 /*
1069 * Yield scheduler intercept not implemented.
1070 * Gating storage scheduler intercept not implemented.
1071 */
1072
1073 /* TODO: Enable/disable TCs. */
1074
1075 env->CP0_VPEControl = newval;
1076 }
1077
1078 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1079 {
1080 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1081 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1082 uint32_t mask;
1083 uint32_t newval;
1084
1085 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1086 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1087 newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1088
1089 /* TODO: Enable/disable TCs. */
1090
1091 other->CP0_VPEControl = newval;
1092 }
1093
1094 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1095 {
1096 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1097 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1098 /* FIXME: Mask away return zero on read bits. */
1099 return other->CP0_VPEControl;
1100 }
1101
1102 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1103 {
1104 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1105 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1106
1107 return other->CP0_VPEConf0;
1108 }
1109
1110 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1111 {
1112 uint32_t mask = 0;
1113 uint32_t newval;
1114
1115 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1116 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) {
1117 mask |= (0xff << CP0VPEC0_XTC);
1118 }
1119 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1120 }
1121 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1122
1123 /* TODO: TC exclusive handling due to ERL/EXL. */
1124
1125 env->CP0_VPEConf0 = newval;
1126 }
1127
1128 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1129 {
1130 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1131 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1132 uint32_t mask = 0;
1133 uint32_t newval;
1134
1135 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1136 newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1137
1138 /* TODO: TC exclusive handling due to ERL/EXL. */
1139 other->CP0_VPEConf0 = newval;
1140 }
1141
1142 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1143 {
1144 uint32_t mask = 0;
1145 uint32_t newval;
1146
1147 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1148 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1149 (0xff << CP0VPEC1_NCP1);
1150 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1151
1152 /* UDI not implemented. */
1153 /* CP2 not implemented. */
1154
1155 /* TODO: Handle FPU (CP1) binding. */
1156
1157 env->CP0_VPEConf1 = newval;
1158 }
1159
1160 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1161 {
1162 /* Yield qualifier inputs not implemented. */
1163 env->CP0_YQMask = 0x00000000;
1164 }
1165
1166 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1167 {
1168 env->CP0_VPEOpt = arg1 & 0x0000ffff;
1169 }
1170
1171 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1172
1173 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1174 {
1175 /* 1k pages not implemented */
1176 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1177 env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
1178 | (rxi << (CP0EnLo_XI - 30));
1179 }
1180
1181 #if defined(TARGET_MIPS64)
1182 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1183
1184 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1185 {
1186 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1187 env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1188 }
1189 #endif
1190
1191 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1192 {
1193 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1194 uint32_t newval;
1195
1196 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1197
1198 env->active_tc.CP0_TCStatus = newval;
1199 sync_c0_tcstatus(env, env->current_tc, newval);
1200 }
1201
1202 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1203 {
1204 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1205 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1206
1207 if (other_tc == other->current_tc) {
1208 other->active_tc.CP0_TCStatus = arg1;
1209 } else {
1210 other->tcs[other_tc].CP0_TCStatus = arg1;
1211 }
1212 sync_c0_tcstatus(other, other_tc, arg1);
1213 }
1214
1215 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1216 {
1217 uint32_t mask = (1 << CP0TCBd_TBE);
1218 uint32_t newval;
1219
1220 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
1221 mask |= (1 << CP0TCBd_CurVPE);
1222 }
1223 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1224 env->active_tc.CP0_TCBind = newval;
1225 }
1226
1227 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1228 {
1229 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1230 uint32_t mask = (1 << CP0TCBd_TBE);
1231 uint32_t newval;
1232 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1233
1234 if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
1235 mask |= (1 << CP0TCBd_CurVPE);
1236 }
1237 if (other_tc == other->current_tc) {
1238 newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1239 other->active_tc.CP0_TCBind = newval;
1240 } else {
1241 newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1242 other->tcs[other_tc].CP0_TCBind = newval;
1243 }
1244 }
1245
1246 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1247 {
1248 env->active_tc.PC = arg1;
1249 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1250 env->CP0_LLAddr = 0;
1251 env->lladdr = 0;
1252 /* MIPS16 not implemented. */
1253 }
1254
1255 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1256 {
1257 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1258 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1259
1260 if (other_tc == other->current_tc) {
1261 other->active_tc.PC = arg1;
1262 other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1263 other->CP0_LLAddr = 0;
1264 other->lladdr = 0;
1265 /* MIPS16 not implemented. */
1266 } else {
1267 other->tcs[other_tc].PC = arg1;
1268 other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1269 other->CP0_LLAddr = 0;
1270 other->lladdr = 0;
1271 /* MIPS16 not implemented. */
1272 }
1273 }
1274
1275 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1276 {
1277 MIPSCPU *cpu = env_archcpu(env);
1278
1279 env->active_tc.CP0_TCHalt = arg1 & 0x1;
1280
1281 /* TODO: Halt TC / Restart (if allocated+active) TC. */
1282 if (env->active_tc.CP0_TCHalt & 1) {
1283 mips_tc_sleep(cpu, env->current_tc);
1284 } else {
1285 mips_tc_wake(cpu, env->current_tc);
1286 }
1287 }
1288
1289 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1290 {
1291 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1292 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1293 MIPSCPU *other_cpu = env_archcpu(other);
1294
1295 /* TODO: Halt TC / Restart (if allocated+active) TC. */
1296
1297 if (other_tc == other->current_tc) {
1298 other->active_tc.CP0_TCHalt = arg1;
1299 } else {
1300 other->tcs[other_tc].CP0_TCHalt = arg1;
1301 }
1302
1303 if (arg1 & 1) {
1304 mips_tc_sleep(other_cpu, other_tc);
1305 } else {
1306 mips_tc_wake(other_cpu, other_tc);
1307 }
1308 }
1309
1310 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1311 {
1312 env->active_tc.CP0_TCContext = arg1;
1313 }
1314
1315 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1316 {
1317 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1318 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1319
1320 if (other_tc == other->current_tc) {
1321 other->active_tc.CP0_TCContext = arg1;
1322 } else {
1323 other->tcs[other_tc].CP0_TCContext = arg1;
1324 }
1325 }
1326
1327 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1328 {
1329 env->active_tc.CP0_TCSchedule = arg1;
1330 }
1331
1332 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1333 {
1334 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1335 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1336
1337 if (other_tc == other->current_tc) {
1338 other->active_tc.CP0_TCSchedule = arg1;
1339 } else {
1340 other->tcs[other_tc].CP0_TCSchedule = arg1;
1341 }
1342 }
1343
1344 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1345 {
1346 env->active_tc.CP0_TCScheFBack = arg1;
1347 }
1348
1349 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1350 {
1351 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1352 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1353
1354 if (other_tc == other->current_tc) {
1355 other->active_tc.CP0_TCScheFBack = arg1;
1356 } else {
1357 other->tcs[other_tc].CP0_TCScheFBack = arg1;
1358 }
1359 }
1360
1361 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1362 {
1363 /* 1k pages not implemented */
1364 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1365 env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
1366 | (rxi << (CP0EnLo_XI - 30));
1367 }
1368
1369 #if defined(TARGET_MIPS64)
1370 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1371 {
1372 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1373 env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1374 }
1375 #endif
1376
1377 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1378 {
1379 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1380 }
1381
1382 void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask)
1383 {
1384 uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1385 if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1386 (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1387 mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1388 mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1389 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1390 }
1391 }
1392
1393 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1394 {
1395 update_pagemask(env, arg1, &env->CP0_PageMask);
1396 }
1397
1398 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1399 {
1400 /* SmartMIPS not implemented */
1401 /* 1k pages not implemented */
1402 env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1403 (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1404 compute_hflags(env);
1405 restore_pamask(env);
1406 }
1407
1408 void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1)
1409 {
1410 CPUState *cs = env_cpu(env);
1411
1412 env->CP0_SegCtl0 = arg1 & CP0SC0_MASK;
1413 tlb_flush(cs);
1414 }
1415
1416 void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1)
1417 {
1418 CPUState *cs = env_cpu(env);
1419
1420 env->CP0_SegCtl1 = arg1 & CP0SC1_MASK;
1421 tlb_flush(cs);
1422 }
1423
1424 void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1)
1425 {
1426 CPUState *cs = env_cpu(env);
1427
1428 env->CP0_SegCtl2 = arg1 & CP0SC2_MASK;
1429 tlb_flush(cs);
1430 }
1431
1432 void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
1433 {
1434 #if defined(TARGET_MIPS64)
1435 uint64_t mask = 0x3F3FFFFFFFULL;
1436 uint32_t old_ptei = (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL;
1437 uint32_t new_ptei = (arg1 >> CP0PF_PTEI) & 0x3FULL;
1438
1439 if ((env->insn_flags & ISA_MIPS32R6)) {
1440 if (((arg1 >> CP0PF_BDI) & 0x3FULL) < 12) {
1441 mask &= ~(0x3FULL << CP0PF_BDI);
1442 }
1443 if (((arg1 >> CP0PF_GDI) & 0x3FULL) < 12) {
1444 mask &= ~(0x3FULL << CP0PF_GDI);
1445 }
1446 if (((arg1 >> CP0PF_UDI) & 0x3FULL) < 12) {
1447 mask &= ~(0x3FULL << CP0PF_UDI);
1448 }
1449 if (((arg1 >> CP0PF_MDI) & 0x3FULL) < 12) {
1450 mask &= ~(0x3FULL << CP0PF_MDI);
1451 }
1452 if (((arg1 >> CP0PF_PTI) & 0x3FULL) < 12) {
1453 mask &= ~(0x3FULL << CP0PF_PTI);
1454 }
1455 }
1456 env->CP0_PWField = arg1 & mask;
1457
1458 if ((new_ptei >= 32) ||
1459 ((env->insn_flags & ISA_MIPS32R6) &&
1460 (new_ptei == 0 || new_ptei == 1))) {
1461 env->CP0_PWField = (env->CP0_PWField & ~0x3FULL) |
1462 (old_ptei << CP0PF_PTEI);
1463 }
1464 #else
1465 uint32_t mask = 0x3FFFFFFF;
1466 uint32_t old_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
1467 uint32_t new_ptew = (arg1 >> CP0PF_PTEW) & 0x3F;
1468
1469 if ((env->insn_flags & ISA_MIPS32R6)) {
1470 if (((arg1 >> CP0PF_GDW) & 0x3F) < 12) {
1471 mask &= ~(0x3F << CP0PF_GDW);
1472 }
1473 if (((arg1 >> CP0PF_UDW) & 0x3F) < 12) {
1474 mask &= ~(0x3F << CP0PF_UDW);
1475 }
1476 if (((arg1 >> CP0PF_MDW) & 0x3F) < 12) {
1477 mask &= ~(0x3F << CP0PF_MDW);
1478 }
1479 if (((arg1 >> CP0PF_PTW) & 0x3F) < 12) {
1480 mask &= ~(0x3F << CP0PF_PTW);
1481 }
1482 }
1483 env->CP0_PWField = arg1 & mask;
1484
1485 if ((new_ptew >= 32) ||
1486 ((env->insn_flags & ISA_MIPS32R6) &&
1487 (new_ptew == 0 || new_ptew == 1))) {
1488 env->CP0_PWField = (env->CP0_PWField & ~0x3F) |
1489 (old_ptew << CP0PF_PTEW);
1490 }
1491 #endif
1492 }
1493
1494 void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1)
1495 {
1496 #if defined(TARGET_MIPS64)
1497 env->CP0_PWSize = arg1 & 0x3F7FFFFFFFULL;
1498 #else
1499 env->CP0_PWSize = arg1 & 0x3FFFFFFF;
1500 #endif
1501 }
1502
1503 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1504 {
1505 if (env->insn_flags & ISA_MIPS32R6) {
1506 if (arg1 < env->tlb->nb_tlb) {
1507 env->CP0_Wired = arg1;
1508 }
1509 } else {
1510 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1511 }
1512 }
1513
1514 void helper_mtc0_pwctl(CPUMIPSState *env, target_ulong arg1)
1515 {
1516 #if defined(TARGET_MIPS64)
1517 /* PWEn = 0. Hardware page table walking is not implemented. */
1518 env->CP0_PWCtl = (env->CP0_PWCtl & 0x000000C0) | (arg1 & 0x5C00003F);
1519 #else
1520 env->CP0_PWCtl = (arg1 & 0x800000FF);
1521 #endif
1522 }
1523
1524 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1525 {
1526 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1527 }
1528
1529 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1530 {
1531 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1532 }
1533
1534 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1535 {
1536 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1537 }
1538
1539 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1540 {
1541 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1542 }
1543
1544 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1545 {
1546 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1547 }
1548
1549 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1550 {
1551 uint32_t mask = 0x0000000F;
1552
1553 if ((env->CP0_Config1 & (1 << CP0C1_PC)) &&
1554 (env->insn_flags & ISA_MIPS32R6)) {
1555 mask |= (1 << 4);
1556 }
1557 if (env->insn_flags & ISA_MIPS32R6) {
1558 mask |= (1 << 5);
1559 }
1560 if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1561 mask |= (1 << 29);
1562
1563 if (arg1 & (1 << 29)) {
1564 env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1565 } else {
1566 env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1567 }
1568 }
1569
1570 env->CP0_HWREna = arg1 & mask;
1571 }
1572
1573 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1574 {
1575 cpu_mips_store_count(env, arg1);
1576 }
1577
1578 void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1)
1579 {
1580 uint32_t target = arg1 & 0x3f;
1581 if (target <= 1) {
1582 env->CP0_SAARI = target;
1583 }
1584 }
1585
1586 void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1)
1587 {
1588 uint32_t target = env->CP0_SAARI & 0x3f;
1589 if (target < 2) {
1590 env->CP0_SAAR[target] = arg1 & 0x00000ffffffff03fULL;
1591 switch (target) {
1592 case 0:
1593 if (env->itu) {
1594 itc_reconfigure(env->itu);
1595 }
1596 break;
1597 }
1598 }
1599 }
1600
1601 void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1)
1602 {
1603 uint32_t target = env->CP0_SAARI & 0x3f;
1604 if (target < 2) {
1605 env->CP0_SAAR[target] =
1606 (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) |
1607 (env->CP0_SAAR[target] & 0x00000000ffffffffULL);
1608 switch (target) {
1609 case 0:
1610 if (env->itu) {
1611 itc_reconfigure(env->itu);
1612 }
1613 break;
1614 }
1615 }
1616 }
1617
1618 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1619 {
1620 target_ulong old, val, mask;
1621 mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask;
1622 if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1623 mask |= 1 << CP0EnHi_EHINV;
1624 }
1625
1626 /* 1k pages not implemented */
1627 #if defined(TARGET_MIPS64)
1628 if (env->insn_flags & ISA_MIPS32R6) {
1629 int entryhi_r = extract64(arg1, 62, 2);
1630 int config0_at = extract32(env->CP0_Config0, 13, 2);
1631 bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1632 if ((entryhi_r == 2) ||
1633 (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1634 /* skip EntryHi.R field if new value is reserved */
1635 mask &= ~(0x3ull << 62);
1636 }
1637 }
1638 mask &= env->SEGMask;
1639 #endif
1640 old = env->CP0_EntryHi;
1641 val = (arg1 & mask) | (old & ~mask);
1642 env->CP0_EntryHi = val;
1643 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1644 sync_c0_entryhi(env, env->current_tc);
1645 }
1646 /* If the ASID changes, flush qemu's TLB. */
1647 if ((old & env->CP0_EntryHi_ASID_mask) !=
1648 (val & env->CP0_EntryHi_ASID_mask)) {
1649 tlb_flush(env_cpu(env));
1650 }
1651 }
1652
1653 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1654 {
1655 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1656 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1657
1658 other->CP0_EntryHi = arg1;
1659 sync_c0_entryhi(other, other_tc);
1660 }
1661
1662 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1663 {
1664 cpu_mips_store_compare(env, arg1);
1665 }
1666
1667 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1668 {
1669 uint32_t val, old;
1670
1671 old = env->CP0_Status;
1672 cpu_mips_store_status(env, arg1);
1673 val = env->CP0_Status;
1674
1675 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1676 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1677 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1678 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1679 env->CP0_Cause);
1680 switch (cpu_mmu_index(env, false)) {
1681 case 3:
1682 qemu_log(", ERL\n");
1683 break;
1684 case MIPS_HFLAG_UM:
1685 qemu_log(", UM\n");
1686 break;
1687 case MIPS_HFLAG_SM:
1688 qemu_log(", SM\n");
1689 break;
1690 case MIPS_HFLAG_KM:
1691 qemu_log("\n");
1692 break;
1693 default:
1694 cpu_abort(env_cpu(env), "Invalid MMU mode!\n");
1695 break;
1696 }
1697 }
1698 }
1699
1700 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1701 {
1702 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1703 uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1704 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1705
1706 other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1707 sync_c0_status(env, other, other_tc);
1708 }
1709
1710 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1711 {
1712 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1713 }
1714
1715 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1716 {
1717 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1718 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1719 }
1720
1721 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1722 {
1723 cpu_mips_store_cause(env, arg1);
1724 }
1725
1726 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1727 {
1728 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1729 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1730
1731 cpu_mips_store_cause(other, arg1);
1732 }
1733
1734 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1735 {
1736 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1737 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1738
1739 return other->CP0_EPC;
1740 }
1741
1742 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1743 {
1744 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1745 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1746
1747 return other->CP0_EBase;
1748 }
1749
1750 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1751 {
1752 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask;
1753 if (arg1 & env->CP0_EBaseWG_rw_bitmask) {
1754 mask |= ~0x3FFFFFFF;
1755 }
1756 env->CP0_EBase = (env->CP0_EBase & ~mask) | (arg1 & mask);
1757 }
1758
1759 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1760 {
1761 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1762 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1763 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask;
1764 if (arg1 & env->CP0_EBaseWG_rw_bitmask) {
1765 mask |= ~0x3FFFFFFF;
1766 }
1767 other->CP0_EBase = (other->CP0_EBase & ~mask) | (arg1 & mask);
1768 }
1769
1770 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1771 {
1772 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1773 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1774
1775 switch (idx) {
1776 case 0: return other->CP0_Config0;
1777 case 1: return other->CP0_Config1;
1778 case 2: return other->CP0_Config2;
1779 case 3: return other->CP0_Config3;
1780 /* 4 and 5 are reserved. */
1781 case 6: return other->CP0_Config6;
1782 case 7: return other->CP0_Config7;
1783 default:
1784 break;
1785 }
1786 return 0;
1787 }
1788
1789 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1790 {
1791 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1792 }
1793
1794 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1795 {
1796 /* tertiary/secondary caches not implemented */
1797 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1798 }
1799
1800 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1801 {
1802 if (env->insn_flags & ASE_MICROMIPS) {
1803 env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1804 (arg1 & (1 << CP0C3_ISA_ON_EXC));
1805 }
1806 }
1807
1808 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1809 {
1810 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1811 (arg1 & env->CP0_Config4_rw_bitmask);
1812 }
1813
1814 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1815 {
1816 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1817 (arg1 & env->CP0_Config5_rw_bitmask);
1818 compute_hflags(env);
1819 }
1820
1821 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1822 {
1823 target_long mask = env->CP0_LLAddr_rw_bitmask;
1824 arg1 = arg1 << env->CP0_LLAddr_shift;
1825 env->CP0_LLAddr = (env->CP0_LLAddr & ~mask) | (arg1 & mask);
1826 }
1827
1828 #define MTC0_MAAR_MASK(env) \
1829 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1830
1831 void helper_mtc0_maar(CPUMIPSState *env, target_ulong arg1)
1832 {
1833 env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env);
1834 }
1835
1836 void helper_mthc0_maar(CPUMIPSState *env, target_ulong arg1)
1837 {
1838 env->CP0_MAAR[env->CP0_MAARI] =
1839 (((uint64_t) arg1 << 32) & MTC0_MAAR_MASK(env)) |
1840 (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL);
1841 }
1842
1843 void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1)
1844 {
1845 int index = arg1 & 0x3f;
1846 if (index == 0x3f) {
1847 /*
1848 * Software may write all ones to INDEX to determine the
1849 * maximum value supported.
1850 */
1851 env->CP0_MAARI = MIPS_MAAR_MAX - 1;
1852 } else if (index < MIPS_MAAR_MAX) {
1853 env->CP0_MAARI = index;
1854 }
1855 /*
1856 * Other than the all ones, if the value written is not supported,
1857 * then INDEX is unchanged from its previous value.
1858 */
1859 }
1860
1861 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1862 {
1863 /*
1864 * Watch exceptions for instructions, data loads, data stores
1865 * not implemented.
1866 */
1867 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1868 }
1869
1870 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1871 {
1872 int mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
1873 env->CP0_WatchHi[sel] = arg1 & mask;
1874 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1875 }
1876
1877 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1878 {
1879 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1880 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1881 }
1882
1883 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1884 {
1885 env->CP0_Framemask = arg1; /* XXX */
1886 }
1887
1888 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1889 {
1890 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1891 if (arg1 & (1 << CP0DB_DM)) {
1892 env->hflags |= MIPS_HFLAG_DM;
1893 } else {
1894 env->hflags &= ~MIPS_HFLAG_DM;
1895 }
1896 }
1897
1898 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1899 {
1900 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1901 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1902 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1903
1904 /* XXX: Might be wrong, check with EJTAG spec. */
1905 if (other_tc == other->current_tc) {
1906 other->active_tc.CP0_Debug_tcstatus = val;
1907 } else {
1908 other->tcs[other_tc].CP0_Debug_tcstatus = val;
1909 }
1910 other->CP0_Debug = (other->CP0_Debug &
1911 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1912 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1913 }
1914
1915 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1916 {
1917 env->CP0_Performance0 = arg1 & 0x000007ff;
1918 }
1919
1920 void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1)
1921 {
1922 int32_t wst = arg1 & (1 << CP0EC_WST);
1923 int32_t spr = arg1 & (1 << CP0EC_SPR);
1924 int32_t itc = env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0;
1925
1926 env->CP0_ErrCtl = wst | spr | itc;
1927
1928 if (itc && !wst && !spr) {
1929 env->hflags |= MIPS_HFLAG_ITC_CACHE;
1930 } else {
1931 env->hflags &= ~MIPS_HFLAG_ITC_CACHE;
1932 }
1933 }
1934
1935 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1936 {
1937 if (env->hflags & MIPS_HFLAG_ITC_CACHE) {
1938 /*
1939 * If CACHE instruction is configured for ITC tags then make all
1940 * CP0.TagLo bits writable. The actual write to ITC Configuration
1941 * Tag will take care of the read-only bits.
1942 */
1943 env->CP0_TagLo = arg1;
1944 } else {
1945 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1946 }
1947 }
1948
1949 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1950 {
1951 env->CP0_DataLo = arg1; /* XXX */
1952 }
1953
1954 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1955 {
1956 env->CP0_TagHi = arg1; /* XXX */
1957 }
1958
1959 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1960 {
1961 env->CP0_DataHi = arg1; /* XXX */
1962 }
1963
1964 /* MIPS MT functions */
1965 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1966 {
1967 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1968 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1969
1970 if (other_tc == other->current_tc) {
1971 return other->active_tc.gpr[sel];
1972 } else {
1973 return other->tcs[other_tc].gpr[sel];
1974 }
1975 }
1976
1977 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1978 {
1979 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1980 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1981
1982 if (other_tc == other->current_tc) {
1983 return other->active_tc.LO[sel];
1984 } else {
1985 return other->tcs[other_tc].LO[sel];
1986 }
1987 }
1988
1989 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1990 {
1991 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1992 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1993
1994 if (other_tc == other->current_tc) {
1995 return other->active_tc.HI[sel];
1996 } else {
1997 return other->tcs[other_tc].HI[sel];
1998 }
1999 }
2000
2001 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
2002 {
2003 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2004 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2005
2006 if (other_tc == other->current_tc) {
2007 return other->active_tc.ACX[sel];
2008 } else {
2009 return other->tcs[other_tc].ACX[sel];
2010 }
2011 }
2012
2013 target_ulong helper_mftdsp(CPUMIPSState *env)
2014 {
2015 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2016 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2017
2018 if (other_tc == other->current_tc) {
2019 return other->active_tc.DSPControl;
2020 } else {
2021 return other->tcs[other_tc].DSPControl;
2022 }
2023 }
2024
2025 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2026 {
2027 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2028 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2029
2030 if (other_tc == other->current_tc) {
2031 other->active_tc.gpr[sel] = arg1;
2032 } else {
2033 other->tcs[other_tc].gpr[sel] = arg1;
2034 }
2035 }
2036
2037 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2038 {
2039 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2040 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2041
2042 if (other_tc == other->current_tc) {
2043 other->active_tc.LO[sel] = arg1;
2044 } else {
2045 other->tcs[other_tc].LO[sel] = arg1;
2046 }
2047 }
2048
2049 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2050 {
2051 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2052 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2053
2054 if (other_tc == other->current_tc) {
2055 other->active_tc.HI[sel] = arg1;
2056 } else {
2057 other->tcs[other_tc].HI[sel] = arg1;
2058 }
2059 }
2060
2061 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2062 {
2063 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2064 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2065
2066 if (other_tc == other->current_tc) {
2067 other->active_tc.ACX[sel] = arg1;
2068 } else {
2069 other->tcs[other_tc].ACX[sel] = arg1;
2070 }
2071 }
2072
2073 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
2074 {
2075 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2076 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2077
2078 if (other_tc == other->current_tc) {
2079 other->active_tc.DSPControl = arg1;
2080 } else {
2081 other->tcs[other_tc].DSPControl = arg1;
2082 }
2083 }
2084
2085 /* MIPS MT functions */
2086 target_ulong helper_dmt(void)
2087 {
2088 /* TODO */
2089 return 0;
2090 }
2091
2092 target_ulong helper_emt(void)
2093 {
2094 /* TODO */
2095 return 0;
2096 }
2097
2098 target_ulong helper_dvpe(CPUMIPSState *env)
2099 {
2100 CPUState *other_cs = first_cpu;
2101 target_ulong prev = env->mvp->CP0_MVPControl;
2102
2103 CPU_FOREACH(other_cs) {
2104 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2105 /* Turn off all VPEs except the one executing the dvpe. */
2106 if (&other_cpu->env != env) {
2107 other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
2108 mips_vpe_sleep(other_cpu);
2109 }
2110 }
2111 return prev;
2112 }
2113
2114 target_ulong helper_evpe(CPUMIPSState *env)
2115 {
2116 CPUState *other_cs = first_cpu;
2117 target_ulong prev = env->mvp->CP0_MVPControl;
2118
2119 CPU_FOREACH(other_cs) {
2120 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2121
2122 if (&other_cpu->env != env
2123 /* If the VPE is WFI, don't disturb its sleep. */
2124 && !mips_vpe_is_wfi(other_cpu)) {
2125 /* Enable the VPE. */
2126 other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
2127 mips_vpe_wake(other_cpu); /* And wake it up. */
2128 }
2129 }
2130 return prev;
2131 }
2132 #endif /* !CONFIG_USER_ONLY */
2133
2134 void helper_fork(target_ulong arg1, target_ulong arg2)
2135 {
2136 /*
2137 * arg1 = rt, arg2 = rs
2138 * TODO: store to TC register
2139 */
2140 }
2141
2142 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
2143 {
2144 target_long arg1 = arg;
2145
2146 if (arg1 < 0) {
2147 /* No scheduling policy implemented. */
2148 if (arg1 != -2) {
2149 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
2150 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
2151 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2152 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
2153 do_raise_exception(env, EXCP_THREAD, GETPC());
2154 }
2155 }
2156 } else if (arg1 == 0) {
2157 if (0) {
2158 /* TODO: TC underflow */
2159 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2160 do_raise_exception(env, EXCP_THREAD, GETPC());
2161 } else {
2162 /* TODO: Deallocate TC */
2163 }
2164 } else if (arg1 > 0) {
2165 /* Yield qualifier inputs not implemented. */
2166 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2167 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
2168 do_raise_exception(env, EXCP_THREAD, GETPC());
2169 }
2170 return env->CP0_YQMask;
2171 }
2172
2173 /* R6 Multi-threading */
2174 #ifndef CONFIG_USER_ONLY
2175 target_ulong helper_dvp(CPUMIPSState *env)
2176 {
2177 CPUState *other_cs = first_cpu;
2178 target_ulong prev = env->CP0_VPControl;
2179
2180 if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
2181 CPU_FOREACH(other_cs) {
2182 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2183 /* Turn off all VPs except the one executing the dvp. */
2184 if (&other_cpu->env != env) {
2185 mips_vpe_sleep(other_cpu);
2186 }
2187 }
2188 env->CP0_VPControl |= (1 << CP0VPCtl_DIS);
2189 }
2190 return prev;
2191 }
2192
2193 target_ulong helper_evp(CPUMIPSState *env)
2194 {
2195 CPUState *other_cs = first_cpu;
2196 target_ulong prev = env->CP0_VPControl;
2197
2198 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
2199 CPU_FOREACH(other_cs) {
2200 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2201 if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {
2202 /*
2203 * If the VP is WFI, don't disturb its sleep.
2204 * Otherwise, wake it up.
2205 */
2206 mips_vpe_wake(other_cpu);
2207 }
2208 }
2209 env->CP0_VPControl &= ~(1 << CP0VPCtl_DIS);
2210 }
2211 return prev;
2212 }
2213 #endif /* !CONFIG_USER_ONLY */
2214
2215 #ifndef CONFIG_USER_ONLY
2216 /* TLB management */
2217 static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first)
2218 {
2219 /* Discard entries from env->tlb[first] onwards. */
2220 while (env->tlb->tlb_in_use > first) {
2221 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
2222 }
2223 }
2224
2225 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
2226 {
2227 #if defined(TARGET_MIPS64)
2228 return extract64(entrylo, 6, 54);
2229 #else
2230 return extract64(entrylo, 6, 24) | /* PFN */
2231 (extract64(entrylo, 32, 32) << 24); /* PFNX */
2232 #endif
2233 }
2234
2235 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
2236 {
2237 r4k_tlb_t *tlb;
2238 uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1);
2239
2240 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
2241 tlb = &env->tlb->mmu.r4k.tlb[idx];
2242 if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
2243 tlb->EHINV = 1;
2244 return;
2245 }
2246 tlb->EHINV = 0;
2247 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
2248 #if defined(TARGET_MIPS64)
2249 tlb->VPN &= env->SEGMask;
2250 #endif
2251 tlb->ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2252 tlb->PageMask = env->CP0_PageMask;
2253 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
2254 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
2255 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
2256 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
2257 tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
2258 tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
2259 tlb->PFN[0] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) << 12;
2260 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
2261 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
2262 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
2263 tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
2264 tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
2265 tlb->PFN[1] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) << 12;
2266 }
2267
2268 void r4k_helper_tlbinv(CPUMIPSState *env)
2269 {
2270 int idx;
2271 r4k_tlb_t *tlb;
2272 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2273
2274 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2275 tlb = &env->tlb->mmu.r4k.tlb[idx];
2276 if (!tlb->G && tlb->ASID == ASID) {
2277 tlb->EHINV = 1;
2278 }
2279 }
2280 cpu_mips_tlb_flush(env);
2281 }
2282
2283 void r4k_helper_tlbinvf(CPUMIPSState *env)
2284 {
2285 int idx;
2286
2287 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2288 env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
2289 }
2290 cpu_mips_tlb_flush(env);
2291 }
2292
2293 void r4k_helper_tlbwi(CPUMIPSState *env)
2294 {
2295 r4k_tlb_t *tlb;
2296 int idx;
2297 target_ulong VPN;
2298 uint16_t ASID;
2299 bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1;
2300
2301 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2302 tlb = &env->tlb->mmu.r4k.tlb[idx];
2303 VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
2304 #if defined(TARGET_MIPS64)
2305 VPN &= env->SEGMask;
2306 #endif
2307 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2308 EHINV = (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) != 0;
2309 G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
2310 V0 = (env->CP0_EntryLo0 & 2) != 0;
2311 D0 = (env->CP0_EntryLo0 & 4) != 0;
2312 XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) &1;
2313 RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) &1;
2314 V1 = (env->CP0_EntryLo1 & 2) != 0;
2315 D1 = (env->CP0_EntryLo1 & 4) != 0;
2316 XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) &1;
2317 RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) &1;
2318
2319 /*
2320 * Discard cached TLB entries, unless tlbwi is just upgrading access
2321 * permissions on the current entry.
2322 */
2323 if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
2324 (!tlb->EHINV && EHINV) ||
2325 (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
2326 (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) ||
2327 (tlb->V1 && !V1) || (tlb->D1 && !D1) ||
2328 (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) {
2329 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2330 }
2331
2332 r4k_invalidate_tlb(env, idx, 0);
2333 r4k_fill_tlb(env, idx);
2334 }
2335
2336 void r4k_helper_tlbwr(CPUMIPSState *env)
2337 {
2338 int r = cpu_mips_get_random(env);
2339
2340 r4k_invalidate_tlb(env, r, 1);
2341 r4k_fill_tlb(env, r);
2342 }
2343
2344 void r4k_helper_tlbp(CPUMIPSState *env)
2345 {
2346 r4k_tlb_t *tlb;
2347 target_ulong mask;
2348 target_ulong tag;
2349 target_ulong VPN;
2350 uint16_t ASID;
2351 int i;
2352
2353 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2354 for (i = 0; i < env->tlb->nb_tlb; i++) {
2355 tlb = &env->tlb->mmu.r4k.tlb[i];
2356 /* 1k pages are not supported. */
2357 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2358 tag = env->CP0_EntryHi & ~mask;
2359 VPN = tlb->VPN & ~mask;
2360 #if defined(TARGET_MIPS64)
2361 tag &= env->SEGMask;
2362 #endif
2363 /* Check ASID, virtual page number & size */
2364 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
2365 /* TLB match */
2366 env->CP0_Index = i;
2367 break;
2368 }
2369 }
2370 if (i == env->tlb->nb_tlb) {
2371 /* No match. Discard any shadow entries, if any of them match. */
2372 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
2373 tlb = &env->tlb->mmu.r4k.tlb[i];
2374 /* 1k pages are not supported. */
2375 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2376 tag = env->CP0_EntryHi & ~mask;
2377 VPN = tlb->VPN & ~mask;
2378 #if defined(TARGET_MIPS64)
2379 tag &= env->SEGMask;
2380 #endif
2381 /* Check ASID, virtual page number & size */
2382 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
2383 r4k_mips_tlb_flush_extra(env, i);
2384 break;
2385 }
2386 }
2387
2388 env->CP0_Index |= 0x80000000;
2389 }
2390 }
2391
2392 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
2393 {
2394 #if defined(TARGET_MIPS64)
2395 return tlb_pfn << 6;
2396 #else
2397 return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
2398 (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
2399 #endif
2400 }
2401
2402 void r4k_helper_tlbr(CPUMIPSState *env)
2403 {
2404 r4k_tlb_t *tlb;
2405 uint16_t ASID;
2406 int idx;
2407
2408 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2409 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2410 tlb = &env->tlb->mmu.r4k.tlb[idx];
2411
2412 /* If this will change the current ASID, flush qemu's TLB. */
2413 if (ASID != tlb->ASID) {
2414 cpu_mips_tlb_flush(env);
2415 }
2416
2417 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2418
2419 if (tlb->EHINV) {
2420 env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2421 env->CP0_PageMask = 0;
2422 env->CP0_EntryLo0 = 0;
2423 env->CP0_EntryLo1 = 0;
2424 } else {
2425 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2426 env->CP0_PageMask = tlb->PageMask;
2427 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2428 ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
2429 ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
2430 get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
2431 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2432 ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
2433 ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
2434 get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
2435 }
2436 }
2437
2438 void helper_tlbwi(CPUMIPSState *env)
2439 {
2440 env->tlb->helper_tlbwi(env);
2441 }
2442
2443 void helper_tlbwr(CPUMIPSState *env)
2444 {
2445 env->tlb->helper_tlbwr(env);
2446 }
2447
2448 void helper_tlbp(CPUMIPSState *env)
2449 {
2450 env->tlb->helper_tlbp(env);
2451 }
2452
2453 void helper_tlbr(CPUMIPSState *env)
2454 {
2455 env->tlb->helper_tlbr(env);
2456 }
2457
2458 void helper_tlbinv(CPUMIPSState *env)
2459 {
2460 env->tlb->helper_tlbinv(env);
2461 }
2462
2463 void helper_tlbinvf(CPUMIPSState *env)
2464 {
2465 env->tlb->helper_tlbinvf(env);
2466 }
2467
2468 /* Specials */
2469 target_ulong helper_di(CPUMIPSState *env)
2470 {
2471 target_ulong t0 = env->CP0_Status;
2472
2473 env->CP0_Status = t0 & ~(1 << CP0St_IE);
2474 return t0;
2475 }
2476
2477 target_ulong helper_ei(CPUMIPSState *env)
2478 {
2479 target_ulong t0 = env->CP0_Status;
2480
2481 env->CP0_Status = t0 | (1 << CP0St_IE);
2482 return t0;
2483 }
2484
2485 static void debug_pre_eret(CPUMIPSState *env)
2486 {
2487 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2488 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2489 env->active_tc.PC, env->CP0_EPC);
2490 if (env->CP0_Status & (1 << CP0St_ERL)) {
2491 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2492 }
2493 if (env->hflags & MIPS_HFLAG_DM) {
2494 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2495 }
2496 qemu_log("\n");
2497 }
2498 }
2499
2500 static void debug_post_eret(CPUMIPSState *env)
2501 {
2502 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2503 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2504 env->active_tc.PC, env->CP0_EPC);
2505 if (env->CP0_Status & (1 << CP0St_ERL)) {
2506 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2507 }
2508 if (env->hflags & MIPS_HFLAG_DM) {
2509 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2510 }
2511 switch (cpu_mmu_index(env, false)) {
2512 case 3:
2513 qemu_log(", ERL\n");
2514 break;
2515 case MIPS_HFLAG_UM:
2516 qemu_log(", UM\n");
2517 break;
2518 case MIPS_HFLAG_SM:
2519 qemu_log(", SM\n");
2520 break;
2521 case MIPS_HFLAG_KM:
2522 qemu_log("\n");
2523 break;
2524 default:
2525 cpu_abort(env_cpu(env), "Invalid MMU mode!\n");
2526 break;
2527 }
2528 }
2529 }
2530
2531 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2532 {
2533 env->active_tc.PC = error_pc & ~(target_ulong)1;
2534 if (error_pc & 1) {
2535 env->hflags |= MIPS_HFLAG_M16;
2536 } else {
2537 env->hflags &= ~(MIPS_HFLAG_M16);
2538 }
2539 }
2540
2541 static inline void exception_return(CPUMIPSState *env)
2542 {
2543 debug_pre_eret(env);
2544 if (env->CP0_Status & (1 << CP0St_ERL)) {
2545 set_pc(env, env->CP0_ErrorEPC);
2546 env->CP0_Status &= ~(1 << CP0St_ERL);
2547 } else {
2548 set_pc(env, env->CP0_EPC);
2549 env->CP0_Status &= ~(1 << CP0St_EXL);
2550 }
2551 compute_hflags(env);
2552 debug_post_eret(env);
2553 }
2554
2555 void helper_eret(CPUMIPSState *env)
2556 {
2557 exception_return(env);
2558 env->CP0_LLAddr = 1;
2559 env->lladdr = 1;
2560 }
2561
2562 void helper_eretnc(CPUMIPSState *env)
2563 {
2564 exception_return(env);
2565 }
2566
2567 void helper_deret(CPUMIPSState *env)
2568 {
2569 debug_pre_eret(env);
2570
2571 env->hflags &= ~MIPS_HFLAG_DM;
2572 compute_hflags(env);
2573
2574 set_pc(env, env->CP0_DEPC);
2575
2576 debug_post_eret(env);
2577 }
2578 #endif /* !CONFIG_USER_ONLY */
2579
2580 static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc)
2581 {
2582 if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) {
2583 return;
2584 }
2585 do_raise_exception(env, EXCP_RI, pc);
2586 }
2587
2588 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2589 {
2590 check_hwrena(env, 0, GETPC());
2591 return env->CP0_EBase & 0x3ff;
2592 }
2593
2594 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2595 {
2596 check_hwrena(env, 1, GETPC());
2597 return env->SYNCI_Step;
2598 }
2599
2600 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2601 {
2602 check_hwrena(env, 2, GETPC());
2603 #ifdef CONFIG_USER_ONLY
2604 return env->CP0_Count;
2605 #else
2606 return (int32_t)cpu_mips_get_count(env);
2607 #endif
2608 }
2609
2610 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2611 {
2612 check_hwrena(env, 3, GETPC());
2613 return env->CCRes;
2614 }
2615
2616 target_ulong helper_rdhwr_performance(CPUMIPSState *env)
2617 {
2618 check_hwrena(env, 4, GETPC());
2619 return env->CP0_Performance0;
2620 }
2621
2622 target_ulong helper_rdhwr_xnp(CPUMIPSState *env)
2623 {
2624 check_hwrena(env, 5, GETPC());
2625 return (env->CP0_Config5 >> CP0C5_XNP) & 1;
2626 }
2627
2628 void helper_pmon(CPUMIPSState *env, int function)
2629 {
2630 function /= 2;
2631 switch (function) {
2632 case 2: /* TODO: char inbyte(int waitflag); */
2633 if (env->active_tc.gpr[4] == 0) {
2634 env->active_tc.gpr[2] = -1;
2635 }
2636 /* Fall through */
2637 case 11: /* TODO: char inbyte (void); */
2638 env->active_tc.gpr[2] = -1;
2639 break;
2640 case 3:
2641 case 12:
2642 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2643 break;
2644 case 17:
2645 break;
2646 case 158:
2647 {
2648 unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2649 printf("%s", fmt);
2650 }
2651 break;
2652 }
2653 }
2654
2655 void helper_wait(CPUMIPSState *env)
2656 {
2657 CPUState *cs = env_cpu(env);
2658
2659 cs->halted = 1;
2660 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2661 /*
2662 * Last instruction in the block, PC was updated before
2663 * - no need to recover PC and icount.
2664 */
2665 raise_exception(env, EXCP_HLT);
2666 }
2667
2668 #if !defined(CONFIG_USER_ONLY)
2669
2670 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2671 MMUAccessType access_type,
2672 int mmu_idx, uintptr_t retaddr)
2673 {
2674 MIPSCPU *cpu = MIPS_CPU(cs);
2675 CPUMIPSState *env = &cpu->env;
2676 int error_code = 0;
2677 int excp;
2678
2679 if (!(env->hflags & MIPS_HFLAG_DM)) {
2680 env->CP0_BadVAddr = addr;
2681 }
2682
2683 if (access_type == MMU_DATA_STORE) {
2684 excp = EXCP_AdES;
2685 } else {
2686 excp = EXCP_AdEL;
2687 if (access_type == MMU_INST_FETCH) {
2688 error_code |= EXCP_INST_NOTAVAIL;
2689 }
2690 }
2691
2692 do_raise_exception_err(env, excp, error_code, retaddr);
2693 }
2694
2695 void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
2696 vaddr addr, unsigned size,
2697 MMUAccessType access_type,
2698 int mmu_idx, MemTxAttrs attrs,
2699 MemTxResult response, uintptr_t retaddr)
2700 {
2701 MIPSCPU *cpu = MIPS_CPU(cs);
2702 CPUMIPSState *env = &cpu->env;
2703
2704 if (access_type == MMU_INST_FETCH) {
2705 do_raise_exception(env, EXCP_IBE, retaddr);
2706 } else {
2707 do_raise_exception(env, EXCP_DBE, retaddr);
2708 }
2709 }
2710 #endif /* !CONFIG_USER_ONLY */
2711
2712 /* Complex FPU operations which may need stack space. */
2713
2714 #define FLOAT_TWO32 make_float32(1 << 30)
2715 #define FLOAT_TWO64 make_float64(1ULL << 62)
2716
2717 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2718 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2719
2720 /* convert MIPS rounding mode in FCR31 to IEEE library */
2721 unsigned int ieee_rm[] = {
2722 float_round_nearest_even,
2723 float_round_to_zero,
2724 float_round_up,
2725 float_round_down
2726 };
2727
2728 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2729 {
2730 target_ulong arg1 = 0;
2731
2732 switch (reg) {
2733 case 0:
2734 arg1 = (int32_t)env->active_fpu.fcr0;
2735 break;
2736 case 1:
2737 /* UFR Support - Read Status FR */
2738 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2739 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2740 arg1 = (int32_t)
2741 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR);
2742 } else {
2743 do_raise_exception(env, EXCP_RI, GETPC());
2744 }
2745 }
2746 break;
2747 case 5:
2748 /* FRE Support - read Config5.FRE bit */
2749 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
2750 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2751 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
2752 } else {
2753 helper_raise_exception(env, EXCP_RI);
2754 }
2755 }
2756 break;
2757 case 25:
2758 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) |
2759 ((env->active_fpu.fcr31 >> 23) & 0x1);
2760 break;
2761 case 26:
2762 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2763 break;
2764 case 28:
2765 arg1 = (env->active_fpu.fcr31 & 0x00000f83) |
2766 ((env->active_fpu.fcr31 >> 22) & 0x4);
2767 break;
2768 default:
2769 arg1 = (int32_t)env->active_fpu.fcr31;
2770 break;
2771 }
2772
2773 return arg1;
2774 }
2775
2776 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2777 {
2778 switch (fs) {
2779 case 1:
2780 /* UFR Alias - Reset Status FR */
2781 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2782 return;
2783 }
2784 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2785 env->CP0_Status &= ~(1 << CP0St_FR);
2786 compute_hflags(env);
2787 } else {
2788 do_raise_exception(env, EXCP_RI, GETPC());
2789 }
2790 break;
2791 case 4:
2792 /* UNFR Alias - Set Status FR */
2793 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2794 return;
2795 }
2796 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2797 env->CP0_Status |= (1 << CP0St_FR);
2798 compute_hflags(env);
2799 } else {
2800 do_raise_exception(env, EXCP_RI, GETPC());
2801 }
2802 break;
2803 case 5:
2804 /* FRE Support - clear Config5.FRE bit */
2805 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2806 return;
2807 }
2808 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2809 env->CP0_Config5 &= ~(1 << CP0C5_FRE);
2810 compute_hflags(env);
2811 } else {
2812 helper_raise_exception(env, EXCP_RI);
2813 }
2814 break;
2815 case 6:
2816 /* FRE Support - set Config5.FRE bit */
2817 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2818 return;
2819 }
2820 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2821 env->CP0_Config5 |= (1 << CP0C5_FRE);
2822 compute_hflags(env);
2823 } else {
2824 helper_raise_exception(env, EXCP_RI);
2825 }
2826 break;
2827 case 25:
2828 if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2829 return;
2830 }
2831 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) |
2832 ((arg1 & 0xfe) << 24) |
2833 ((arg1 & 0x1) << 23);
2834 break;
2835 case 26:
2836 if (arg1 & 0x007c0000) {
2837 return;
2838 }
2839 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) |
2840 (arg1 & 0x0003f07c);
2841 break;
2842 case 28:
2843 if (arg1 & 0x007c0000) {
2844 return;
2845 }
2846 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) |
2847 (arg1 & 0x00000f83) |
2848 ((arg1 & 0x4) << 22);
2849 break;
2850 case 31:
2851 env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) |
2852 (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
2853 break;
2854 default:
2855 if (env->insn_flags & ISA_MIPS32R6) {
2856 do_raise_exception(env, EXCP_RI, GETPC());
2857 }
2858 return;
2859 }
2860 restore_fp_status(env);
2861 set_float_exception_flags(0, &env->active_fpu.fp_status);
2862 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) &
2863 GET_FP_CAUSE(env->active_fpu.fcr31)) {
2864 do_raise_exception(env, EXCP_FPE, GETPC());
2865 }
2866 }
2867
2868 int ieee_ex_to_mips(int xcpt)
2869 {
2870 int ret = 0;
2871 if (xcpt) {
2872 if (xcpt & float_flag_invalid) {
2873 ret |= FP_INVALID;
2874 }
2875 if (xcpt & float_flag_overflow) {
2876 ret |= FP_OVERFLOW;
2877 }
2878 if (xcpt & float_flag_underflow) {
2879 ret |= FP_UNDERFLOW;
2880 }
2881 if (xcpt & float_flag_divbyzero) {
2882 ret |= FP_DIV0;
2883 }
2884 if (xcpt & float_flag_inexact) {
2885 ret |= FP_INEXACT;
2886 }
2887 }
2888 return ret;
2889 }
2890
2891 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2892 {
2893 int tmp = ieee_ex_to_mips(get_float_exception_flags(
2894 &env->active_fpu.fp_status));
2895
2896 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2897
2898 if (tmp) {
2899 set_float_exception_flags(0, &env->active_fpu.fp_status);
2900
2901 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2902 do_raise_exception(env, EXCP_FPE, pc);
2903 } else {
2904 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2905 }
2906 }
2907 }
2908
2909 /*
2910 * Float support.
2911 * Single precition routines have a "s" suffix, double precision a
2912 * "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2913 * paired single lower "pl", paired single upper "pu".
2914 */
2915
2916 /* unary operations, modifying fp status */
2917 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2918 {
2919 fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2920 update_fcr31(env, GETPC());
2921 return fdt0;
2922 }
2923
2924 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2925 {
2926 fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2927 update_fcr31(env, GETPC());
2928 return fst0;
2929 }
2930
2931 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2932 {
2933 uint64_t fdt2;
2934
2935 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2936 update_fcr31(env, GETPC());
2937 return fdt2;
2938 }
2939
2940 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2941 {
2942 uint64_t fdt2;
2943
2944 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2945 update_fcr31(env, GETPC());
2946 return fdt2;
2947 }
2948
2949 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2950 {
2951 uint64_t fdt2;
2952
2953 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2954 update_fcr31(env, GETPC());
2955 return fdt2;
2956 }
2957
2958 uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
2959 {
2960 uint64_t dt2;
2961
2962 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2963 if (get_float_exception_flags(&env->active_fpu.fp_status)
2964 & (float_flag_invalid | float_flag_overflow)) {
2965 dt2 = FP_TO_INT64_OVERFLOW;
2966 }
2967 update_fcr31(env, GETPC());
2968 return dt2;
2969 }
2970
2971 uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
2972 {
2973 uint64_t dt2;
2974
2975 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2976 if (get_float_exception_flags(&env->active_fpu.fp_status)
2977 & (float_flag_invalid | float_flag_overflow)) {
2978 dt2 = FP_TO_INT64_OVERFLOW;
2979 }
2980 update_fcr31(env, GETPC());
2981 return dt2;
2982 }
2983
2984 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2985 {
2986 uint32_t fst2;
2987 uint32_t fsth2;
2988
2989 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2990 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2991 update_fcr31(env, GETPC());
2992 return ((uint64_t)fsth2 << 32) | fst2;
2993 }
2994
2995 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2996 {
2997 uint32_t wt2;
2998 uint32_t wth2;
2999 int excp, excph;
3000
3001 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3002 excp = get_float_exception_flags(&env->active_fpu.fp_status);
3003 if (excp & (float_flag_overflow | float_flag_invalid)) {
3004 wt2 = FP_TO_INT32_OVERFLOW;
3005 }
3006
3007 set_float_exception_flags(0, &env->active_fpu.fp_status);
3008 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
3009 excph = get_float_exception_flags(&env->active_fpu.fp_status);
3010 if (excph & (float_flag_overflow | float_flag_invalid)) {
3011 wth2 = FP_TO_INT32_OVERFLOW;
3012 }
3013
3014 set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
3015 update_fcr31(env, GETPC());
3016
3017 return ((uint64_t)wth2 << 32) | wt2;
3018 }
3019
3020 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
3021 {
3022 uint32_t fst2;
3023
3024 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
3025 update_fcr31(env, GETPC());
3026 return fst2;
3027 }
3028
3029 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
3030 {
3031 uint32_t fst2;
3032
3033 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
3034 update_fcr31(env, GETPC());
3035 return fst2;
3036 }
3037
3038 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
3039 {
3040 uint32_t fst2;
3041
3042 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
3043 update_fcr31(env, GETPC());
3044 return fst2;
3045 }
3046
3047 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
3048 {
3049 uint32_t wt2;
3050
3051 wt2 = wt0;
3052 update_fcr31(env, GETPC());
3053 return wt2;
3054 }
3055
3056 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
3057 {
3058 uint32_t wt2;
3059
3060 wt2 = wth0;
3061 update_fcr31(env, GETPC());
3062 return wt2;
3063 }
3064
3065 uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
3066 {
3067 uint32_t wt2;
3068
3069 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3070 if (get_float_exception_flags(&env->active_fpu.fp_status)
3071 & (float_flag_invalid | float_flag_overflow)) {
3072 wt2 = FP_TO_INT32_OVERFLOW;
3073 }
3074 update_fcr31(env, GETPC());
3075 return wt2;
3076 }
3077
3078 uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
3079 {
3080 uint32_t wt2;
3081
3082 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3083 if (get_float_exception_flags(&env->active_fpu.fp_status)
3084 & (float_flag_invalid | float_flag_overflow)) {
3085 wt2 = FP_TO_INT32_OVERFLOW;
3086 }
3087 update_fcr31(env, GETPC());
3088 return wt2;
3089 }
3090
3091 uint64_t helper_float_round_l_d(CPUMIPSState *env, uint64_t fdt0)
3092 {
3093 uint64_t dt2;
3094
3095 set_float_rounding_mode(float_round_nearest_even,
3096 &env->active_fpu.fp_status);
3097 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3098 restore_rounding_mode(env);
3099 if (get_float_exception_flags(&env->active_fpu.fp_status)
3100 & (float_flag_invalid | float_flag_overflow)) {
3101 dt2 = FP_TO_INT64_OVERFLOW;
3102 }
3103 update_fcr31(env, GETPC());
3104 return dt2;
3105 }
3106
3107 uint64_t helper_float_round_l_s(CPUMIPSState *env, uint32_t fst0)
3108 {
3109 uint64_t dt2;
3110
3111 set_float_rounding_mode(float_round_nearest_even,
3112 &env->active_fpu.fp_status);
3113 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3114 restore_rounding_mode(env);
3115 if (get_float_exception_flags(&env->active_fpu.fp_status)
3116 & (float_flag_invalid | float_flag_overflow)) {
3117 dt2 = FP_TO_INT64_OVERFLOW;
3118 }
3119 update_fcr31(env, GETPC());
3120 return dt2;
3121 }
3122
3123 uint32_t helper_float_round_w_d(CPUMIPSState *env, uint64_t fdt0)
3124 {
3125 uint32_t wt2;
3126
3127 set_float_rounding_mode(float_round_nearest_even,
3128 &env->active_fpu.fp_status);
3129 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3130 restore_rounding_mode(env);
3131 if (get_float_exception_flags(&env->active_fpu.fp_status)
3132 & (float_flag_invalid | float_flag_overflow)) {
3133 wt2 = FP_TO_INT32_OVERFLOW;
3134 }
3135 update_fcr31(env, GETPC());
3136 return wt2;
3137 }
3138
3139 uint32_t helper_float_round_w_s(CPUMIPSState *env, uint32_t fst0)
3140 {
3141 uint32_t wt2;
3142
3143 set_float_rounding_mode(float_round_nearest_even,
3144 &env->active_fpu.fp_status);
3145 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3146 restore_rounding_mode(env);
3147 if (get_float_exception_flags(&env->active_fpu.fp_status)
3148 & (float_flag_invalid | float_flag_overflow)) {
3149 wt2 = FP_TO_INT32_OVERFLOW;
3150 }
3151 update_fcr31(env, GETPC());
3152 return wt2;
3153 }
3154
3155 uint64_t helper_float_trunc_l_d(CPUMIPSState *env, uint64_t fdt0)
3156 {
3157 uint64_t dt2;
3158
3159 dt2 = float64_to_int64_round_to_zero(fdt0,
3160 &env->active_fpu.fp_status);
3161 if (get_float_exception_flags(&env->active_fpu.fp_status)
3162 & (float_flag_invalid | float_flag_overflow)) {
3163 dt2 = FP_TO_INT64_OVERFLOW;
3164 }
3165 update_fcr31(env, GETPC());
3166 return dt2;
3167 }
3168
3169 uint64_t helper_float_trunc_l_s(CPUMIPSState *env, uint32_t fst0)
3170 {
3171 uint64_t dt2;
3172
3173 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
3174 if (get_float_exception_flags(&env->active_fpu.fp_status)
3175 & (float_flag_invalid | float_flag_overflow)) {
3176 dt2 = FP_TO_INT64_OVERFLOW;
3177 }
3178 update_fcr31(env, GETPC());
3179 return dt2;
3180 }
3181
3182 uint32_t helper_float_trunc_w_d(CPUMIPSState *env, uint64_t fdt0)
3183 {
3184 uint32_t wt2;
3185
3186 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
3187 if (get_float_exception_flags(&env->active_fpu.fp_status)
3188 & (float_flag_invalid | float_flag_overflow)) {
3189 wt2 = FP_TO_INT32_OVERFLOW;
3190 }
3191 update_fcr31(env, GETPC());
3192 return wt2;
3193 }
3194
3195 uint32_t helper_float_trunc_w_s(CPUMIPSState *env, uint32_t fst0)
3196 {
3197 uint32_t wt2;
3198
3199 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
3200 if (get_float_exception_flags(&env->active_fpu.fp_status)
3201 & (float_flag_invalid | float_flag_overflow)) {
3202 wt2 = FP_TO_INT32_OVERFLOW;
3203 }
3204 update_fcr31(env, GETPC());
3205 return wt2;
3206 }
3207
3208 uint64_t helper_float_ceil_l_d(CPUMIPSState *env, uint64_t fdt0)
3209 {
3210 uint64_t dt2;
3211
3212 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3213 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3214 restore_rounding_mode(env);
3215 if (get_float_exception_flags(&env->active_fpu.fp_status)
3216 & (float_flag_invalid | float_flag_overflow)) {
3217 dt2 = FP_TO_INT64_OVERFLOW;
3218 }
3219 update_fcr31(env, GETPC());
3220 return dt2;
3221 }
3222
3223 uint64_t helper_float_ceil_l_s(CPUMIPSState *env, uint32_t fst0)
3224 {
3225 uint64_t dt2;
3226
3227 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3228 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3229 restore_rounding_mode(env);
3230 if (get_float_exception_flags(&env->active_fpu.fp_status)
3231 & (float_flag_invalid | float_flag_overflow)) {
3232 dt2 = FP_TO_INT64_OVERFLOW;
3233 }
3234 update_fcr31(env, GETPC());
3235 return dt2;
3236 }
3237
3238 uint32_t helper_float_ceil_w_d(CPUMIPSState *env, uint64_t fdt0)
3239 {
3240 uint32_t wt2;
3241
3242 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3243 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3244 restore_rounding_mode(env);
3245 if (get_float_exception_flags(&env->active_fpu.fp_status)
3246 & (float_flag_invalid | float_flag_overflow)) {
3247 wt2 = FP_TO_INT32_OVERFLOW;
3248 }
3249 update_fcr31(env, GETPC());
3250 return wt2;
3251 }
3252
3253 uint32_t helper_float_ceil_w_s(CPUMIPSState *env, uint32_t fst0)
3254 {
3255 uint32_t wt2;
3256
3257 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3258 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3259 restore_rounding_mode(env);
3260 if (get_float_exception_flags(&env->active_fpu.fp_status)
3261 & (float_flag_invalid | float_flag_overflow)) {
3262 wt2 = FP_TO_INT32_OVERFLOW;
3263 }
3264 update_fcr31(env, GETPC());
3265 return wt2;
3266 }
3267
3268 uint64_t helper_float_floor_l_d(CPUMIPSState *env, uint64_t fdt0)
3269 {
3270 uint64_t dt2;
3271
3272 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3273 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3274 restore_rounding_mode(env);
3275 if (get_float_exception_flags(&env->active_fpu.fp_status)
3276 & (float_flag_invalid | float_flag_overflow)) {
3277 dt2 = FP_TO_INT64_OVERFLOW;
3278 }
3279 update_fcr31(env, GETPC());
3280 return dt2;
3281 }
3282
3283 uint64_t helper_float_floor_l_s(CPUMIPSState *env, uint32_t fst0)
3284 {
3285 uint64_t dt2;
3286
3287 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3288 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3289 restore_rounding_mode(env);
3290 if (get_float_exception_flags(&env->active_fpu.fp_status)
3291 & (float_flag_invalid | float_flag_overflow)) {
3292 dt2 = FP_TO_INT64_OVERFLOW;
3293 }
3294 update_fcr31(env, GETPC());
3295 return dt2;
3296 }
3297
3298 uint32_t helper_float_floor_w_d(CPUMIPSState *env, uint64_t fdt0)
3299 {
3300 uint32_t wt2;
3301
3302 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3303 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3304 restore_rounding_mode(env);
3305 if (get_float_exception_flags(&env->active_fpu.fp_status)
3306 & (float_flag_invalid | float_flag_overflow)) {
3307 wt2 = FP_TO_INT32_OVERFLOW;
3308 }
3309 update_fcr31(env, GETPC());
3310 return wt2;
3311 }
3312
3313 uint32_t helper_float_floor_w_s(CPUMIPSState *env, uint32_t fst0)
3314 {
3315 uint32_t wt2;
3316
3317 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3318 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3319 restore_rounding_mode(env);
3320 if (get_float_exception_flags(&env->active_fpu.fp_status)
3321 & (float_flag_invalid | float_flag_overflow)) {
3322 wt2 = FP_TO_INT32_OVERFLOW;
3323 }
3324 update_fcr31(env, GETPC());
3325 return wt2;
3326 }
3327
3328 uint64_t helper_float_cvt_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3329 {
3330 uint64_t dt2;
3331
3332 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3333 if (get_float_exception_flags(&env->active_fpu.fp_status)
3334 & float_flag_invalid) {
3335 if (float64_is_any_nan(fdt0)) {
3336 dt2 = 0;
3337 }
3338 }
3339 update_fcr31(env, GETPC());
3340 return dt2;
3341 }
3342
3343 uint64_t helper_float_cvt_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3344 {
3345 uint64_t dt2;
3346
3347 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3348 if (get_float_exception_flags(&env->active_fpu.fp_status)
3349 & float_flag_invalid) {
3350 if (float32_is_any_nan(fst0)) {
3351 dt2 = 0;
3352 }
3353 }
3354 update_fcr31(env, GETPC());
3355 return dt2;
3356 }
3357
3358 uint32_t helper_float_cvt_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3359 {
3360 uint32_t wt2;
3361
3362 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3363 if (get_float_exception_flags(&env->active_fpu.fp_status)
3364 & float_flag_invalid) {
3365 if (float64_is_any_nan(fdt0)) {
3366 wt2 = 0;
3367 }
3368 }
3369 update_fcr31(env, GETPC());
3370 return wt2;
3371 }
3372
3373 uint32_t helper_float_cvt_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3374 {
3375 uint32_t wt2;
3376
3377 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3378 if (get_float_exception_flags(&env->active_fpu.fp_status)
3379 & float_flag_invalid) {
3380 if (float32_is_any_nan(fst0)) {
3381 wt2 = 0;
3382 }
3383 }
3384 update_fcr31(env, GETPC());
3385 return wt2;
3386 }
3387
3388 uint64_t helper_float_round_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3389 {
3390 uint64_t dt2;
3391
3392 set_float_rounding_mode(float_round_nearest_even,
3393 &env->active_fpu.fp_status);
3394 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3395 restore_rounding_mode(env);
3396 if (get_float_exception_flags(&env->active_fpu.fp_status)
3397 & float_flag_invalid) {
3398 if (float64_is_any_nan(fdt0)) {
3399 dt2 = 0;
3400 }
3401 }
3402 update_fcr31(env, GETPC());
3403 return dt2;
3404 }
3405
3406 uint64_t helper_float_round_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3407 {
3408 uint64_t dt2;
3409
3410 set_float_rounding_mode(float_round_nearest_even,
3411 &env->active_fpu.fp_status);
3412 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3413 restore_rounding_mode(env);
3414 if (get_float_exception_flags(&env->active_fpu.fp_status)
3415 & float_flag_invalid) {
3416 if (float32_is_any_nan(fst0)) {
3417 dt2 = 0;
3418 }
3419 }
3420 update_fcr31(env, GETPC());
3421 return dt2;
3422 }
3423
3424 uint32_t helper_float_round_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3425 {
3426 uint32_t wt2;
3427
3428 set_float_rounding_mode(float_round_nearest_even,
3429 &env->active_fpu.fp_status);
3430 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3431 restore_rounding_mode(env);
3432 if (get_float_exception_flags(&env->active_fpu.fp_status)
3433 & float_flag_invalid) {
3434 if (float64_is_any_nan(fdt0)) {
3435 wt2 = 0;
3436 }
3437 }
3438 update_fcr31(env, GETPC());
3439 return wt2;
3440 }
3441
3442 uint32_t helper_float_round_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3443 {
3444 uint32_t wt2;
3445
3446 set_float_rounding_mode(float_round_nearest_even,
3447 &env->active_fpu.fp_status);
3448 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3449 restore_rounding_mode(env);
3450 if (get_float_exception_flags(&env->active_fpu.fp_status)
3451 & float_flag_invalid) {
3452 if (float32_is_any_nan(fst0)) {
3453 wt2 = 0;
3454 }
3455 }
3456 update_fcr31(env, GETPC());
3457 return wt2;
3458 }
3459
3460 uint64_t helper_float_trunc_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3461 {
3462 uint64_t dt2;
3463
3464 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
3465 if (get_float_exception_flags(&env->active_fpu.fp_status)
3466 & float_flag_invalid) {
3467 if (float64_is_any_nan(fdt0)) {
3468 dt2 = 0;
3469 }
3470 }
3471 update_fcr31(env, GETPC());
3472 return dt2;
3473 }
3474
3475 uint64_t helper_float_trunc_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3476 {
3477 uint64_t dt2;
3478
3479 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
3480 if (get_float_exception_flags(&env->active_fpu.fp_status)
3481 & float_flag_invalid) {
3482 if (float32_is_any_nan(fst0)) {
3483 dt2 = 0;
3484 }
3485 }
3486 update_fcr31(env, GETPC());
3487 return dt2;
3488 }
3489
3490 uint32_t helper_float_trunc_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3491 {
3492 uint32_t wt2;
3493
3494 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
3495 if (get_float_exception_flags(&env->active_fpu.fp_status)
3496 & float_flag_invalid) {
3497 if (float64_is_any_nan(fdt0)) {
3498 wt2 = 0;
3499 }
3500 }
3501 update_fcr31(env, GETPC());
3502 return wt2;
3503 }
3504
3505 uint32_t helper_float_trunc_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3506 {
3507 uint32_t wt2;
3508
3509 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
3510 if (get_float_exception_flags(&env->active_fpu.fp_status)
3511 & float_flag_invalid) {
3512 if (float32_is_any_nan(fst0)) {
3513 wt2 = 0;
3514 }
3515 }
3516 update_fcr31(env, GETPC());
3517 return wt2;
3518 }
3519
3520 uint64_t helper_float_ceil_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3521 {
3522 uint64_t dt2;
3523
3524 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3525 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3526 restore_rounding_mode(env);
3527 if (get_float_exception_flags(&env->active_fpu.fp_status)
3528 & float_flag_invalid) {
3529 if (float64_is_any_nan(fdt0)) {
3530 dt2 = 0;
3531 }
3532 }
3533 update_fcr31(env, GETPC());
3534 return dt2;
3535 }
3536
3537 uint64_t helper_float_ceil_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3538 {
3539 uint64_t dt2;
3540
3541 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3542 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3543 restore_rounding_mode(env);
3544 if (get_float_exception_flags(&env->active_fpu.fp_status)
3545 & float_flag_invalid) {
3546 if (float32_is_any_nan(fst0)) {
3547 dt2 = 0;
3548 }
3549 }
3550 update_fcr31(env, GETPC());
3551 return dt2;
3552 }
3553
3554 uint32_t helper_float_ceil_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3555 {
3556 uint32_t wt2;
3557
3558 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3559 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3560 restore_rounding_mode(env);
3561 if (get_float_exception_flags(&env->active_fpu.fp_status)
3562 & float_flag_invalid) {
3563 if (float64_is_any_nan(fdt0)) {
3564 wt2 = 0;
3565 }
3566 }
3567 update_fcr31(env, GETPC());
3568 return wt2;
3569 }
3570
3571 uint32_t helper_float_ceil_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3572 {
3573 uint32_t wt2;
3574
3575 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3576 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3577 restore_rounding_mode(env);
3578 if (get_float_exception_flags(&env->active_fpu.fp_status)
3579 & float_flag_invalid) {
3580 if (float32_is_any_nan(fst0)) {
3581 wt2 = 0;
3582 }
3583 }
3584 update_fcr31(env, GETPC());
3585 return wt2;
3586 }
3587
3588 uint64_t helper_float_floor_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3589 {
3590 uint64_t dt2;
3591
3592 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3593 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3594 restore_rounding_mode(env);
3595 if (get_float_exception_flags(&env->active_fpu.fp_status)
3596 & float_flag_invalid) {
3597 if (float64_is_any_nan(fdt0)) {
3598 dt2 = 0;
3599 }
3600 }
3601 update_fcr31(env, GETPC());
3602 return dt2;
3603 }
3604
3605 uint64_t helper_float_floor_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3606 {
3607 uint64_t dt2;
3608
3609 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3610 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3611 restore_rounding_mode(env);
3612 if (get_float_exception_flags(&env->active_fpu.fp_status)
3613 & float_flag_invalid) {
3614 if (float32_is_any_nan(fst0)) {
3615 dt2 = 0;
3616 }
3617 }
3618 update_fcr31(env, GETPC());
3619 return dt2;
3620 }
3621
3622 uint32_t helper_float_floor_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3623 {
3624 uint32_t wt2;
3625
3626 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3627 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3628 restore_rounding_mode(env);
3629 if (get_float_exception_flags(&env->active_fpu.fp_status)
3630 & float_flag_invalid) {
3631 if (float64_is_any_nan(fdt0)) {
3632 wt2 = 0;
3633 }
3634 }
3635 update_fcr31(env, GETPC());
3636 return wt2;
3637 }
3638
3639 uint32_t helper_float_floor_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3640 {
3641 uint32_t wt2;
3642
3643 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3644 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3645 restore_rounding_mode(env);
3646 if (get_float_exception_flags(&env->active_fpu.fp_status)
3647 & float_flag_invalid) {
3648 if (float32_is_any_nan(fst0)) {
3649 wt2 = 0;
3650 }
3651 }
3652 update_fcr31(env, GETPC());
3653 return wt2;
3654 }
3655
3656 /* unary operations, not modifying fp status */
3657 #define FLOAT_UNOP(name) \
3658 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
3659 { \
3660 return float64_ ## name(fdt0); \
3661 } \
3662 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
3663 { \
3664 return float32_ ## name(fst0); \
3665 } \
3666 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
3667 { \
3668 uint32_t wt0; \
3669 uint32_t wth0; \
3670 \
3671 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
3672 wth0 = float32_ ## name(fdt0 >> 32); \
3673 return ((uint64_t)wth0 << 32) | wt0; \
3674 }
3675 FLOAT_UNOP(abs)
3676 FLOAT_UNOP(chs)
3677 #undef FLOAT_UNOP
3678
3679 /* MIPS specific unary operations */
3680 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
3681 {
3682 uint64_t fdt2;
3683
3684 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3685 update_fcr31(env, GETPC());
3686 return fdt2;
3687 }
3688
3689 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
3690 {
3691 uint32_t fst2;
3692
3693 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3694 update_fcr31(env, GETPC());
3695 return fst2;
3696 }
3697
3698 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
3699 {
3700 uint64_t fdt2;
3701
3702 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3703 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3704 update_fcr31(env, GETPC());
3705 return fdt2;
3706 }
3707
3708 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
3709 {
3710 uint32_t fst2;
3711
3712 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3713 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3714 update_fcr31(env, GETPC());
3715 return fst2;
3716 }
3717
3718 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
3719 {
3720 uint64_t fdt2;
3721
3722 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3723 update_fcr31(env, GETPC());
3724 return fdt2;
3725 }
3726
3727 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
3728 {
3729 uint32_t fst2;
3730
3731 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3732 update_fcr31(env, GETPC());
3733 return fst2;
3734 }
3735
3736 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
3737 {
3738 uint32_t fst2;
3739 uint32_t fsth2;
3740
3741 fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF,
3742 &env->active_fpu.fp_status);
3743 fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
3744 update_fcr31(env, GETPC());
3745 return ((uint64_t)fsth2 << 32) | fst2;
3746 }
3747
3748 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
3749 {
3750 uint64_t fdt2;
3751
3752 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3753 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3754 update_fcr31(env, GETPC());
3755 return fdt2;
3756 }
3757
3758 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3759 {
3760 uint32_t fst2;
3761
3762 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3763 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3764 update_fcr31(env, GETPC());
3765 return fst2;
3766 }
3767
3768 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3769 {
3770 uint32_t fst2;
3771 uint32_t fsth2;
3772
3773 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3774 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3775 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3776 fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3777 update_fcr31(env, GETPC());
3778 return ((uint64_t)fsth2 << 32) | fst2;
3779 }
3780
3781 #define FLOAT_RINT(name, bits) \
3782 uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
3783 uint ## bits ## _t fs) \
3784 { \
3785 uint ## bits ## _t fdret; \
3786 \
3787 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3788 update_fcr31(env, GETPC()); \
3789 return fdret; \
3790 }
3791
3792 FLOAT_RINT(rint_s, 32)
3793 FLOAT_RINT(rint_d, 64)
3794 #undef FLOAT_RINT
3795
3796 #define FLOAT_CLASS_SIGNALING_NAN 0x001
3797 #define FLOAT_CLASS_QUIET_NAN 0x002
3798 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
3799 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
3800 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3801 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
3802 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
3803 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
3804 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3805 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
3806
3807 #define FLOAT_CLASS(name, bits) \
3808 uint ## bits ## _t float_ ## name(uint ## bits ## _t arg, \
3809 float_status *status) \
3810 { \
3811 if (float ## bits ## _is_signaling_nan(arg, status)) { \
3812 return FLOAT_CLASS_SIGNALING_NAN; \
3813 } else if (float ## bits ## _is_quiet_nan(arg, status)) { \
3814 return FLOAT_CLASS_QUIET_NAN; \
3815 } else if (float ## bits ## _is_neg(arg)) { \
3816 if (float ## bits ## _is_infinity(arg)) { \
3817 return FLOAT_CLASS_NEGATIVE_INFINITY; \
3818 } else if (float ## bits ## _is_zero(arg)) { \
3819 return FLOAT_CLASS_NEGATIVE_ZERO; \
3820 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3821 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
3822 } else { \
3823 return FLOAT_CLASS_NEGATIVE_NORMAL; \
3824 } \
3825 } else { \
3826 if (float ## bits ## _is_infinity(arg)) { \
3827 return FLOAT_CLASS_POSITIVE_INFINITY; \
3828 } else if (float ## bits ## _is_zero(arg)) { \
3829 return FLOAT_CLASS_POSITIVE_ZERO; \
3830 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3831 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
3832 } else { \
3833 return FLOAT_CLASS_POSITIVE_NORMAL; \
3834 } \
3835 } \
3836 } \
3837 \
3838 uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
3839 uint ## bits ## _t arg) \
3840 { \
3841 return float_ ## name(arg, &env->active_fpu.fp_status); \
3842 }
3843
3844 FLOAT_CLASS(class_s, 32)
3845 FLOAT_CLASS(class_d, 64)
3846 #undef FLOAT_CLASS
3847
3848 /* binary operations */
3849 #define FLOAT_BINOP(name) \
3850 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3851 uint64_t fdt0, uint64_t fdt1) \
3852 { \
3853 uint64_t dt2; \
3854 \
3855 dt2 = float64_ ## name(fdt0, fdt1, &env->active_fpu.fp_status);\
3856 update_fcr31(env, GETPC()); \
3857 return dt2; \
3858 } \
3859 \
3860 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3861 uint32_t fst0, uint32_t fst1) \
3862 { \
3863 uint32_t wt2; \
3864 \
3865 wt2 = float32_ ## name(fst0, fst1, &env->active_fpu.fp_status);\
3866 update_fcr31(env, GETPC()); \
3867 return wt2; \
3868 } \
3869 \
3870 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3871 uint64_t fdt0, \
3872 uint64_t fdt1) \
3873 { \
3874 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3875 uint32_t fsth0 = fdt0 >> 32; \
3876 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3877 uint32_t fsth1 = fdt1 >> 32; \
3878 uint32_t wt2; \
3879 uint32_t wth2; \
3880 \
3881 wt2 = float32_ ## name(fst0, fst1, &env->active_fpu.fp_status); \
3882 wth2 = float32_ ## name(fsth0, fsth1, &env->active_fpu.fp_status); \
3883 update_fcr31(env, GETPC()); \
3884 return ((uint64_t)wth2 << 32) | wt2; \
3885 }
3886
3887 FLOAT_BINOP(add)
3888 FLOAT_BINOP(sub)
3889 FLOAT_BINOP(mul)
3890 FLOAT_BINOP(div)
3891 #undef FLOAT_BINOP
3892
3893 /* MIPS specific binary operations */
3894 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3895 {
3896 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3897 fdt2 = float64_chs(float64_sub(fdt2, float64_one,
3898 &env->active_fpu.fp_status));
3899 update_fcr31(env, GETPC());
3900 return fdt2;
3901 }
3902
3903 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3904 {
3905 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3906 fst2 = float32_chs(float32_sub(fst2, float32_one,
3907 &env->active_fpu.fp_status));
3908 update_fcr31(env, GETPC());
3909 return fst2;
3910 }
3911
3912 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3913 {
3914 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3915 uint32_t fsth0 = fdt0 >> 32;
3916 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3917 uint32_t fsth2 = fdt2 >> 32;
3918
3919 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3920 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3921 fst2 = float32_chs(float32_sub(fst2, float32_one,
3922 &env->active_fpu.fp_status));
3923 fsth2 = float32_chs(float32_sub(fsth2, float32_one,
3924 &env->active_fpu.fp_status));
3925 update_fcr31(env, GETPC());
3926 return ((uint64_t)fsth2 << 32) | fst2;
3927 }
3928
3929 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3930 {
3931 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3932 fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3933 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64,
3934 &env->active_fpu.fp_status));
3935 update_fcr31(env, GETPC());
3936 return fdt2;
3937 }
3938
3939 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3940 {
3941 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3942 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3943 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32,
3944 &env->active_fpu.fp_status));
3945 update_fcr31(env, GETPC());
3946 return fst2;
3947 }
3948
3949 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3950 {
3951 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3952 uint32_t fsth0 = fdt0 >> 32;
3953 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3954 uint32_t fsth2 = fdt2 >> 32;
3955
3956 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3957 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3958 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3959 fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3960 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32,
3961 &env->active_fpu.fp_status));
3962 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32,
3963 &env->active_fpu.fp_status));
3964 update_fcr31(env, GETPC());
3965 return ((uint64_t)fsth2 << 32) | fst2;
3966 }
3967
3968 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3969 {
3970 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3971 uint32_t fsth0 = fdt0 >> 32;
3972 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3973 uint32_t fsth1 = fdt1 >> 32;
3974 uint32_t fst2;
3975 uint32_t fsth2;
3976
3977 fst2 = float32_add(fst0, fsth0, &env->active_fpu.fp_status);
3978 fsth2 = float32_add(fst1, fsth1, &env->active_fpu.fp_status);
3979 update_fcr31(env, GETPC());
3980 return ((uint64_t)fsth2 << 32) | fst2;
3981 }
3982
3983 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3984 {
3985 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3986 uint32_t fsth0 = fdt0 >> 32;
3987 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3988 uint32_t fsth1 = fdt1 >> 32;
3989 uint32_t fst2;
3990 uint32_t fsth2;
3991
3992 fst2 = float32_mul(fst0, fsth0, &env->active_fpu.fp_status);
3993 fsth2 = float32_mul(fst1, fsth1, &env->active_fpu.fp_status);
3994 update_fcr31(env, GETPC());
3995 return ((uint64_t)fsth2 << 32) | fst2;
3996 }
3997
3998 #define FLOAT_MINMAX(name, bits, minmaxfunc) \
3999 uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
4000 uint ## bits ## _t fs, \
4001 uint ## bits ## _t ft) \
4002 { \
4003 uint ## bits ## _t fdret; \
4004 \
4005 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
4006 &env->active_fpu.fp_status); \
4007 update_fcr31(env, GETPC()); \
4008 return fdret; \
4009 }
4010
4011 FLOAT_MINMAX(max_s, 32, maxnum)
4012 FLOAT_MINMAX(max_d, 64, maxnum)
4013 FLOAT_MINMAX(maxa_s, 32, maxnummag)
4014 FLOAT_MINMAX(maxa_d, 64, maxnummag)
4015
4016 FLOAT_MINMAX(min_s, 32, minnum)
4017 FLOAT_MINMAX(min_d, 64, minnum)
4018 FLOAT_MINMAX(mina_s, 32, minnummag)
4019 FLOAT_MINMAX(mina_d, 64, minnummag)
4020 #undef FLOAT_MINMAX
4021
4022 /* ternary operations */
4023 #define UNFUSED_FMA(prefix, a, b, c, flags) \
4024 { \
4025 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
4026 if ((flags) & float_muladd_negate_c) { \
4027 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
4028 } else { \
4029 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
4030 } \
4031 if ((flags) & float_muladd_negate_result) { \
4032 a = prefix##_chs(a); \
4033 } \
4034 }
4035
4036 /* FMA based operations */
4037 #define FLOAT_FMA(name, type) \
4038 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
4039 uint64_t fdt0, uint64_t fdt1, \
4040 uint64_t fdt2) \
4041 { \
4042 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
4043 update_fcr31(env, GETPC()); \
4044 return fdt0; \
4045 } \
4046 \
4047 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
4048 uint32_t fst0, uint32_t fst1, \
4049 uint32_t fst2) \
4050 { \
4051 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
4052 update_fcr31(env, GETPC()); \
4053 return fst0; \
4054 } \
4055 \
4056 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
4057 uint64_t fdt0, uint64_t fdt1, \
4058 uint64_t fdt2) \
4059 { \
4060 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
4061 uint32_t fsth0 = fdt0 >> 32; \
4062 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
4063 uint32_t fsth1 = fdt1 >> 32; \
4064 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
4065 uint32_t fsth2 = fdt2 >> 32; \
4066 \
4067 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
4068 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
4069 update_fcr31(env, GETPC()); \
4070 return ((uint64_t)fsth0 << 32) | fst0; \
4071 }
4072 FLOAT_FMA(madd, 0)
4073 FLOAT_FMA(msub, float_muladd_negate_c)
4074 FLOAT_FMA(nmadd, float_muladd_negate_result)
4075 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
4076 #undef FLOAT_FMA
4077
4078 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \
4079 uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
4080 uint ## bits ## _t fs, \
4081 uint ## bits ## _t ft, \
4082 uint ## bits ## _t fd) \
4083 { \
4084 uint ## bits ## _t fdret; \
4085 \
4086 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
4087 &env->active_fpu.fp_status); \
4088 update_fcr31(env, GETPC()); \
4089 return fdret; \
4090 }
4091
4092 FLOAT_FMADDSUB(maddf_s, 32, 0)
4093 FLOAT_FMADDSUB(maddf_d, 64, 0)
4094 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
4095 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
4096 #undef FLOAT_FMADDSUB
4097
4098 /* compare operations */
4099 #define FOP_COND_D(op, cond) \
4100 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4101 uint64_t fdt1, int cc) \
4102 { \
4103 int c; \
4104 c = cond; \
4105 update_fcr31(env, GETPC()); \
4106 if (c) \
4107 SET_FP_COND(cc, env->active_fpu); \
4108 else \
4109 CLEAR_FP_COND(cc, env->active_fpu); \
4110 } \
4111 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4112 uint64_t fdt1, int cc) \
4113 { \
4114 int c; \
4115 fdt0 = float64_abs(fdt0); \
4116 fdt1 = float64_abs(fdt1); \
4117 c = cond; \
4118 update_fcr31(env, GETPC()); \
4119 if (c) \
4120 SET_FP_COND(cc, env->active_fpu); \
4121 else \
4122 CLEAR_FP_COND(cc, env->active_fpu); \
4123 }
4124
4125 /*
4126 * NOTE: the comma operator will make "cond" to eval to false,
4127 * but float64_unordered_quiet() is still called.
4128 */
4129 FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0,
4130 &env->active_fpu.fp_status), 0))
4131 FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0,
4132 &env->active_fpu.fp_status))
4133 FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1,
4134 &env->active_fpu.fp_status))
4135 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0,
4136 &env->active_fpu.fp_status)
4137 || float64_eq_quiet(fdt0, fdt1,
4138 &env->active_fpu.fp_status))
4139 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1,
4140 &env->active_fpu.fp_status))
4141 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0,
4142 &env->active_fpu.fp_status)
4143 || float64_lt_quiet(fdt0, fdt1,
4144 &env->active_fpu.fp_status))
4145 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1,
4146 &env->active_fpu.fp_status))
4147 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0,
4148 &env->active_fpu.fp_status)
4149 || float64_le_quiet(fdt0, fdt1,
4150 &env->active_fpu.fp_status))
4151 /*
4152 * NOTE: the comma operator will make "cond" to eval to false,
4153 * but float64_unordered() is still called.
4154 */
4155 FOP_COND_D(sf, (float64_unordered(fdt1, fdt0,
4156 &env->active_fpu.fp_status), 0))
4157 FOP_COND_D(ngle, float64_unordered(fdt1, fdt0,
4158 &env->active_fpu.fp_status))
4159 FOP_COND_D(seq, float64_eq(fdt0, fdt1,
4160 &env->active_fpu.fp_status))
4161 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0,
4162 &env->active_fpu.fp_status)
4163 || float64_eq(fdt0, fdt1,
4164 &env->active_fpu.fp_status))
4165 FOP_COND_D(lt, float64_lt(fdt0, fdt1,
4166 &env->active_fpu.fp_status))
4167 FOP_COND_D(nge, float64_unordered(fdt1, fdt0,
4168 &env->active_fpu.fp_status)
4169 || float64_lt(fdt0, fdt1,
4170 &env->active_fpu.fp_status))
4171 FOP_COND_D(le, float64_le(fdt0, fdt1,
4172 &env->active_fpu.fp_status))
4173 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0,
4174 &env->active_fpu.fp_status)
4175 || float64_le(fdt0, fdt1,
4176 &env->active_fpu.fp_status))
4177
4178 #define FOP_COND_S(op, cond) \
4179 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
4180 uint32_t fst1, int cc) \
4181 { \
4182 int c; \
4183 c = cond; \
4184 update_fcr31(env, GETPC()); \
4185 if (c) \
4186 SET_FP_COND(cc, env->active_fpu); \
4187 else \
4188 CLEAR_FP_COND(cc, env->active_fpu); \
4189 } \
4190 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
4191 uint32_t fst1, int cc) \
4192 { \
4193 int c; \
4194 fst0 = float32_abs(fst0); \
4195 fst1 = float32_abs(fst1); \
4196 c = cond; \
4197 update_fcr31(env, GETPC()); \
4198 if (c) \
4199 SET_FP_COND(cc, env->active_fpu); \
4200 else \
4201 CLEAR_FP_COND(cc, env->active_fpu); \
4202 }
4203
4204 /*
4205 * NOTE: the comma operator will make "cond" to eval to false,
4206 * but float32_unordered_quiet() is still called.
4207 */
4208 FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0,
4209 &env->active_fpu.fp_status), 0))
4210 FOP_COND_S(un, float32_unordered_quiet(fst1, fst0,
4211 &env->active_fpu.fp_status))
4212 FOP_COND_S(eq, float32_eq_quiet(fst0, fst1,
4213 &env->active_fpu.fp_status))
4214 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0,
4215 &env->active_fpu.fp_status)
4216 || float32_eq_quiet(fst0, fst1,
4217 &env->active_fpu.fp_status))
4218 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1,
4219 &env->active_fpu.fp_status))
4220 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0,
4221 &env->active_fpu.fp_status)
4222 || float32_lt_quiet(fst0, fst1,
4223 &env->active_fpu.fp_status))
4224 FOP_COND_S(ole, float32_le_quiet(fst0, fst1,
4225 &env->active_fpu.fp_status))
4226 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0,
4227 &env->active_fpu.fp_status)
4228 || float32_le_quiet(fst0, fst1,
4229 &env->active_fpu.fp_status))
4230 /*
4231 * NOTE: the comma operator will make "cond" to eval to false,
4232 * but float32_unordered() is still called.
4233 */
4234 FOP_COND_S(sf, (float32_unordered(fst1, fst0,
4235 &env->active_fpu.fp_status), 0))
4236 FOP_COND_S(ngle, float32_unordered(fst1, fst0,
4237 &env->active_fpu.fp_status))
4238 FOP_COND_S(seq, float32_eq(fst0, fst1,
4239 &env->active_fpu.fp_status))
4240 FOP_COND_S(ngl, float32_unordered(fst1, fst0,
4241 &env->active_fpu.fp_status)
4242 || float32_eq(fst0, fst1,
4243 &env->active_fpu.fp_status))
4244 FOP_COND_S(lt, float32_lt(fst0, fst1,
4245 &env->active_fpu.fp_status))
4246 FOP_COND_S(nge, float32_unordered(fst1, fst0,
4247 &env->active_fpu.fp_status)
4248 || float32_lt(fst0, fst1,
4249 &env->active_fpu.fp_status))
4250 FOP_COND_S(le, float32_le(fst0, fst1,
4251 &env->active_fpu.fp_status))
4252 FOP_COND_S(ngt, float32_unordered(fst1, fst0,
4253 &env->active_fpu.fp_status)
4254 || float32_le(fst0, fst1,
4255 &env->active_fpu.fp_status))
4256
4257 #define FOP_COND_PS(op, condl, condh) \
4258 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4259 uint64_t fdt1, int cc) \
4260 { \
4261 uint32_t fst0, fsth0, fst1, fsth1; \
4262 int ch, cl; \
4263 fst0 = fdt0 & 0XFFFFFFFF; \
4264 fsth0 = fdt0 >> 32; \
4265 fst1 = fdt1 & 0XFFFFFFFF; \
4266 fsth1 = fdt1 >> 32; \
4267 cl = condl; \
4268 ch = condh; \
4269 update_fcr31(env, GETPC()); \
4270 if (cl) \
4271 SET_FP_COND(cc, env->active_fpu); \
4272 else \
4273 CLEAR_FP_COND(cc, env->active_fpu); \
4274 if (ch) \
4275 SET_FP_COND(cc + 1, env->active_fpu); \
4276 else \
4277 CLEAR_FP_COND(cc + 1, env->active_fpu); \
4278 } \
4279 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4280 uint64_t fdt1, int cc) \
4281 { \
4282 uint32_t fst0, fsth0, fst1, fsth1; \
4283 int ch, cl; \
4284 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
4285 fsth0 = float32_abs(fdt0 >> 32); \
4286 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
4287 fsth1 = float32_abs(fdt1 >> 32); \
4288 cl = condl; \
4289 ch = condh; \
4290 update_fcr31(env, GETPC()); \
4291 if (cl) \
4292 SET_FP_COND(cc, env->active_fpu); \
4293 else \
4294 CLEAR_FP_COND(cc, env->active_fpu); \
4295 if (ch) \
4296 SET_FP_COND(cc + 1, env->active_fpu); \
4297 else \
4298 CLEAR_FP_COND(cc + 1, env->active_fpu); \
4299 }
4300
4301 /*
4302 * NOTE: the comma operator will make "cond" to eval to false,
4303 * but float32_unordered_quiet() is still called.
4304 */
4305 FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0,
4306 &env->active_fpu.fp_status), 0),
4307 (float32_unordered_quiet(fsth1, fsth0,
4308 &env->active_fpu.fp_status), 0))
4309 FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0,
4310 &env->active_fpu.fp_status),
4311 float32_unordered_quiet(fsth1, fsth0,
4312 &env->active_fpu.fp_status))
4313 FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1,
4314 &env->active_fpu.fp_status),
4315 float32_eq_quiet(fsth0, fsth1,
4316 &env->active_fpu.fp_status))
4317 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0,
4318 &env->active_fpu.fp_status)
4319 || float32_eq_quiet(fst0, fst1,
4320 &env->active_fpu.fp_status),
4321 float32_unordered_quiet(fsth1, fsth0,
4322 &env->active_fpu.fp_status)
4323 || float32_eq_quiet(fsth0, fsth1,
4324 &env->active_fpu.fp_status))
4325 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1,
4326 &env->active_fpu.fp_status),
4327 float32_lt_quiet(fsth0, fsth1,
4328 &env->active_fpu.fp_status))
4329 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0,
4330 &env->active_fpu.fp_status)
4331 || float32_lt_quiet(fst0, fst1,
4332 &env->active_fpu.fp_status),
4333 float32_unordered_quiet(fsth1, fsth0,
4334 &env->active_fpu.fp_status)
4335 || float32_lt_quiet(fsth0, fsth1,
4336 &env->active_fpu.fp_status))
4337 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1,
4338 &env->active_fpu.fp_status),
4339 float32_le_quiet(fsth0, fsth1,
4340 &env->active_fpu.fp_status))
4341 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0,
4342 &env->active_fpu.fp_status)
4343 || float32_le_quiet(fst0, fst1,
4344 &env->active_fpu.fp_status),
4345 float32_unordered_quiet(fsth1, fsth0,
4346 &env->active_fpu.fp_status)
4347 || float32_le_quiet(fsth0, fsth1,
4348 &env->active_fpu.fp_status))
4349 /*
4350 * NOTE: the comma operator will make "cond" to eval to false,
4351 * but float32_unordered() is still called.
4352 */
4353 FOP_COND_PS(sf, (float32_unordered(fst1, fst0,
4354 &env->active_fpu.fp_status), 0),
4355 (float32_unordered(fsth1, fsth0,
4356 &env->active_fpu.fp_status), 0))
4357 FOP_COND_PS(ngle, float32_unordered(fst1, fst0,
4358 &env->active_fpu.fp_status),
4359 float32_unordered(fsth1, fsth0,
4360 &env->active_fpu.fp_status))
4361 FOP_COND_PS(seq, float32_eq(fst0, fst1,
4362 &env->active_fpu.fp_status),
4363 float32_eq(fsth0, fsth1,
4364 &env->active_fpu.fp_status))
4365 FOP_COND_PS(ngl, float32_unordered(fst1, fst0,
4366 &env->active_fpu.fp_status)
4367 || float32_eq(fst0, fst1,
4368 &env->active_fpu.fp_status),
4369 float32_unordered(fsth1, fsth0,
4370 &env->active_fpu.fp_status)
4371 || float32_eq(fsth0, fsth1,
4372 &env->active_fpu.fp_status))
4373 FOP_COND_PS(lt, float32_lt(fst0, fst1,
4374 &env->active_fpu.fp_status),
4375 float32_lt(fsth0, fsth1,
4376 &env->active_fpu.fp_status))
4377 FOP_COND_PS(nge, float32_unordered(fst1, fst0,
4378 &env->active_fpu.fp_status)
4379 || float32_lt(fst0, fst1,
4380 &env->active_fpu.fp_status),
4381 float32_unordered(fsth1, fsth0,
4382 &env->active_fpu.fp_status)
4383 || float32_lt(fsth0, fsth1,
4384 &env->active_fpu.fp_status))
4385 FOP_COND_PS(le, float32_le(fst0, fst1,
4386 &env->active_fpu.fp_status),
4387 float32_le(fsth0, fsth1,
4388 &env->active_fpu.fp_status))
4389 FOP_COND_PS(ngt, float32_unordered(fst1, fst0,
4390 &env->active_fpu.fp_status)
4391 || float32_le(fst0, fst1,
4392 &env->active_fpu.fp_status),
4393 float32_unordered(fsth1, fsth0,
4394 &env->active_fpu.fp_status)
4395 || float32_le(fsth0, fsth1,
4396 &env->active_fpu.fp_status))
4397
4398 /* R6 compare operations */
4399 #define FOP_CONDN_D(op, cond) \
4400 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4401 uint64_t fdt1) \
4402 { \
4403 uint64_t c; \
4404 c = cond; \
4405 update_fcr31(env, GETPC()); \
4406 if (c) { \
4407 return -1; \
4408 } else { \
4409 return 0; \
4410 } \
4411 }
4412
4413 /*
4414 * NOTE: the comma operator will make "cond" to eval to false,
4415 * but float64_unordered_quiet() is still called.
4416 */
4417 FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0,
4418 &env->active_fpu.fp_status), 0))
4419 FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0,
4420 &env->active_fpu.fp_status)))
4421 FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1,
4422 &env->active_fpu.fp_status)))
4423 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0,
4424 &env->active_fpu.fp_status)
4425 || float64_eq_quiet(fdt0, fdt1,
4426 &env->active_fpu.fp_status)))
4427 FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1,
4428 &env->active_fpu.fp_status)))
4429 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0,
4430 &env->active_fpu.fp_status)
4431 || float64_lt_quiet(fdt0, fdt1,
4432 &env->active_fpu.fp_status)))
4433 FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1,
4434 &env->active_fpu.fp_status)))
4435 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0,
4436 &env->active_fpu.fp_status)
4437 || float64_le_quiet(fdt0, fdt1,
4438 &env->active_fpu.fp_status)))
4439 /*
4440 * NOTE: the comma operator will make "cond" to eval to false,
4441 * but float64_unordered() is still called.\
4442 */
4443 FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0,
4444 &env->active_fpu.fp_status), 0))
4445 FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0,
4446 &env->active_fpu.fp_status)))
4447 FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1,
4448 &env->active_fpu.fp_status)))
4449 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0,
4450 &env->active_fpu.fp_status)
4451 || float64_eq(fdt0, fdt1,
4452 &env->active_fpu.fp_status)))
4453 FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1,
4454 &env->active_fpu.fp_status)))
4455 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0,
4456 &env->active_fpu.fp_status)
4457 || float64_lt(fdt0, fdt1,
4458 &env->active_fpu.fp_status)))
4459 FOP_CONDN_D(sle, (float64_le(fdt0, fdt1,
4460 &env->active_fpu.fp_status)))
4461 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0,
4462 &env->active_fpu.fp_status)
4463 || float64_le(fdt0, fdt1,
4464 &env->active_fpu.fp_status)))
4465 FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0,
4466 &env->active_fpu.fp_status)
4467 || float64_le_quiet(fdt0, fdt1,
4468 &env->active_fpu.fp_status)))
4469 FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0,
4470 &env->active_fpu.fp_status)
4471 || float64_lt_quiet(fdt1, fdt0,
4472 &env->active_fpu.fp_status)
4473 || float64_lt_quiet(fdt0, fdt1,
4474 &env->active_fpu.fp_status)))
4475 FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0,
4476 &env->active_fpu.fp_status)
4477 || float64_lt_quiet(fdt0, fdt1,
4478 &env->active_fpu.fp_status)))
4479 FOP_CONDN_D(sor, (float64_le(fdt1, fdt0,
4480 &env->active_fpu.fp_status)
4481 || float64_le(fdt0, fdt1,
4482 &env->active_fpu.fp_status)))
4483 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0,
4484 &env->active_fpu.fp_status)
4485 || float64_lt(fdt1, fdt0,
4486 &env->active_fpu.fp_status)
4487 || float64_lt(fdt0, fdt1,
4488 &env->active_fpu.fp_status)))
4489 FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0,
4490 &env->active_fpu.fp_status)
4491 || float64_lt(fdt0, fdt1,
4492 &env->active_fpu.fp_status)))
4493
4494 #define FOP_CONDN_S(op, cond) \
4495 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
4496 uint32_t fst1) \
4497 { \
4498 uint64_t c; \
4499 c = cond; \
4500 update_fcr31(env, GETPC()); \
4501 if (c) { \
4502 return -1; \
4503 } else { \
4504 return 0; \
4505 } \
4506 }
4507
4508 /*
4509 * NOTE: the comma operator will make "cond" to eval to false,
4510 * but float32_unordered_quiet() is still called.
4511 */
4512 FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0,
4513 &env->active_fpu.fp_status), 0))
4514 FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0,
4515 &env->active_fpu.fp_status)))
4516 FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1,
4517 &env->active_fpu.fp_status)))
4518 FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0,
4519 &env->active_fpu.fp_status)
4520 || float32_eq_quiet(fst0, fst1,
4521 &env->active_fpu.fp_status)))
4522 FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1,
4523 &env->active_fpu.fp_status)))
4524 FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0,
4525 &env->active_fpu.fp_status)
4526 || float32_lt_quiet(fst0, fst1,
4527 &env->active_fpu.fp_status)))
4528 FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1,
4529 &env->active_fpu.fp_status)))
4530 FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0,
4531 &env->active_fpu.fp_status)
4532 || float32_le_quiet(fst0, fst1,
4533 &env->active_fpu.fp_status)))
4534 /*
4535 * NOTE: the comma operator will make "cond" to eval to false,
4536 * but float32_unordered() is still called.
4537 */
4538 FOP_CONDN_S(saf, (float32_unordered(fst1, fst0,
4539 &env->active_fpu.fp_status), 0))
4540 FOP_CONDN_S(sun, (float32_unordered(fst1, fst0,
4541 &env->active_fpu.fp_status)))
4542 FOP_CONDN_S(seq, (float32_eq(fst0, fst1,
4543 &env->active_fpu.fp_status)))
4544 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0,
4545 &env->active_fpu.fp_status)
4546 || float32_eq(fst0, fst1,
4547 &env->active_fpu.fp_status)))
4548 FOP_CONDN_S(slt, (float32_lt(fst0, fst1,
4549 &env->active_fpu.fp_status)))
4550 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0,
4551 &env->active_fpu.fp_status)
4552 || float32_lt(fst0, fst1,
4553 &env->active_fpu.fp_status)))
4554 FOP_CONDN_S(sle, (float32_le(fst0, fst1,
4555 &env->active_fpu.fp_status)))
4556 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0,
4557 &env->active_fpu.fp_status)
4558 || float32_le(fst0, fst1,
4559 &env->active_fpu.fp_status)))
4560 FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0,
4561 &env->active_fpu.fp_status)
4562 || float32_le_quiet(fst0, fst1,
4563 &env->active_fpu.fp_status)))
4564 FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0,
4565 &env->active_fpu.fp_status)
4566 || float32_lt_quiet(fst1, fst0,
4567 &env->active_fpu.fp_status)
4568 || float32_lt_quiet(fst0, fst1,
4569 &env->active_fpu.fp_status)))
4570 FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0,
4571 &env->active_fpu.fp_status)
4572 || float32_lt_quiet(fst0, fst1,
4573 &env->active_fpu.fp_status)))
4574 FOP_CONDN_S(sor, (float32_le(fst1, fst0,
4575 &env->active_fpu.fp_status)
4576 || float32_le(fst0, fst1,
4577 &env->active_fpu.fp_status)))
4578 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0,
4579 &env->active_fpu.fp_status)
4580 || float32_lt(fst1, fst0,
4581 &env->active_fpu.fp_status)
4582 || float32_lt(fst0, fst1,
4583 &env->active_fpu.fp_status)))
4584 FOP_CONDN_S(sne, (float32_lt(fst1, fst0,
4585 &env->active_fpu.fp_status)
4586 || float32_lt(fst0, fst1,
4587 &env->active_fpu.fp_status)))
4588
4589 /* MSA */
4590 /* Data format min and max values */
4591 #define DF_BITS(df) (1 << ((df) + 3))
4592
4593 /* Element-by-element access macros */
4594 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
4595
4596 #if !defined(CONFIG_USER_ONLY)
4597 #define MEMOP_IDX(DF) \
4598 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
4599 cpu_mmu_index(env, false));
4600 #else
4601 #define MEMOP_IDX(DF)
4602 #endif
4603
4604 void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd,
4605 target_ulong addr)
4606 {
4607 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4608 MEMOP_IDX(DF_BYTE)
4609 #if !defined(CONFIG_USER_ONLY)
4610 #if !defined(HOST_WORDS_BIGENDIAN)
4611 pwd->b[0] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC());
4612 pwd->b[1] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC());
4613 pwd->b[2] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC());
4614 pwd->b[3] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC());
4615 pwd->b[4] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC());
4616 pwd->b[5] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC());
4617 pwd->b[6] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC());
4618 pwd->b[7] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC());
4619 pwd->b[8] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC());
4620 pwd->b[9] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC());
4621 pwd->b[10] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC());
4622 pwd->b[11] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC());
4623 pwd->b[12] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC());
4624 pwd->b[13] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC());
4625 pwd->b[14] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC());
4626 pwd->b[15] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC());
4627 #else
4628 pwd->b[0] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC());
4629 pwd->b[1] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC());
4630 pwd->b[2] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC());
4631 pwd->b[3] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC());
4632 pwd->b[4] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC());
4633 pwd->b[5] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC());
4634 pwd->b[6] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC());
4635 pwd->b[7] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC());
4636 pwd->b[8] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC());
4637 pwd->b[9] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC());
4638 pwd->b[10] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC());
4639 pwd->b[11] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC());
4640 pwd->b[12] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC());
4641 pwd->b[13] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC());
4642 pwd->b[14] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC());
4643 pwd->b[15] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC());
4644 #endif
4645 #else
4646 #if !defined(HOST_WORDS_BIGENDIAN)
4647 pwd->b[0] = cpu_ldub_data(env, addr + (0 << DF_BYTE));
4648 pwd->b[1] = cpu_ldub_data(env, addr + (1 << DF_BYTE));
4649 pwd->b[2] = cpu_ldub_data(env, addr + (2 << DF_BYTE));
4650 pwd->b[3] = cpu_ldub_data(env, addr + (3 << DF_BYTE));
4651 pwd->b[4] = cpu_ldub_data(env, addr + (4 << DF_BYTE));
4652 pwd->b[5] = cpu_ldub_data(env, addr + (5 << DF_BYTE));
4653 pwd->b[6] = cpu_ldub_data(env, addr + (6 << DF_BYTE));
4654 pwd->b[7] = cpu_ldub_data(env, addr + (7 << DF_BYTE));
4655 pwd->b[8] = cpu_ldub_data(env, addr + (8 << DF_BYTE));
4656 pwd->b[9] = cpu_ldub_data(env, addr + (9 << DF_BYTE));
4657 pwd->b[10] = cpu_ldub_data(env, addr + (10 << DF_BYTE));
4658 pwd->b[11] = cpu_ldub_data(env, addr + (11 << DF_BYTE));
4659 pwd->b[12] = cpu_ldub_data(env, addr + (12 << DF_BYTE));
4660 pwd->b[13] = cpu_ldub_data(env, addr + (13 << DF_BYTE));
4661 pwd->b[14] = cpu_ldub_data(env, addr + (14 << DF_BYTE));
4662 pwd->b[15] = cpu_ldub_data(env, addr + (15 << DF_BYTE));
4663 #else
4664 pwd->b[0] = cpu_ldub_data(env, addr + (7 << DF_BYTE));
4665 pwd->b[1] = cpu_ldub_data(env, addr + (6 << DF_BYTE));
4666 pwd->b[2] = cpu_ldub_data(env, addr + (5 << DF_BYTE));
4667 pwd->b[3] = cpu_ldub_data(env, addr + (4 << DF_BYTE));
4668 pwd->b[4] = cpu_ldub_data(env, addr + (3 << DF_BYTE));
4669 pwd->b[5] = cpu_ldub_data(env, addr + (2 << DF_BYTE));
4670 pwd->b[6] = cpu_ldub_data(env, addr + (1 << DF_BYTE));
4671 pwd->b[7] = cpu_ldub_data(env, addr + (0 << DF_BYTE));
4672 pwd->b[8] = cpu_ldub_data(env, addr + (15 << DF_BYTE));
4673 pwd->b[9] = cpu_ldub_data(env, addr + (14 << DF_BYTE));
4674 pwd->b[10] = cpu_ldub_data(env, addr + (13 << DF_BYTE));
4675 pwd->b[11] = cpu_ldub_data(env, addr + (12 << DF_BYTE));
4676 pwd->b[12] = cpu_ldub_data(env, addr + (11 << DF_BYTE));
4677 pwd->b[13] = cpu_ldub_data(env, addr + (10 << DF_BYTE));
4678 pwd->b[14] = cpu_ldub_data(env, addr + (9 << DF_BYTE));
4679 pwd->b[15] = cpu_ldub_data(env, addr + (8 << DF_BYTE));
4680 #endif
4681 #endif
4682 }
4683
4684 void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd,
4685 target_ulong addr)
4686 {
4687 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4688 MEMOP_IDX(DF_HALF)
4689 #if !defined(CONFIG_USER_ONLY)
4690 #if !defined(HOST_WORDS_BIGENDIAN)
4691 pwd->h[0] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC());
4692 pwd->h[1] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC());
4693 pwd->h[2] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC());
4694 pwd->h[3] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC());
4695 pwd->h[4] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC());
4696 pwd->h[5] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC());
4697 pwd->h[6] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC());
4698 pwd->h[7] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC());
4699 #else
4700 pwd->h[0] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC());
4701 pwd->h[1] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC());
4702 pwd->h[2] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC());
4703 pwd->h[3] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC());
4704 pwd->h[4] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC());
4705 pwd->h[5] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC());
4706 pwd->h[6] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC());
4707 pwd->h[7] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC());
4708 #endif
4709 #else
4710 #if !defined(HOST_WORDS_BIGENDIAN)
4711 pwd->h[0] = cpu_lduw_data(env, addr + (0 << DF_HALF));
4712 pwd->h[1] = cpu_lduw_data(env, addr + (1 << DF_HALF));
4713 pwd->h[2] = cpu_lduw_data(env, addr + (2 << DF_HALF));
4714 pwd->h[3] = cpu_lduw_data(env, addr + (3 << DF_HALF));
4715 pwd->h[4] = cpu_lduw_data(env, addr + (4 << DF_HALF));
4716 pwd->h[5] = cpu_lduw_data(env, addr + (5 << DF_HALF));
4717 pwd->h[6] = cpu_lduw_data(env, addr + (6 << DF_HALF));
4718 pwd->h[7] = cpu_lduw_data(env, addr + (7 << DF_HALF));
4719 #else
4720 pwd->h[0] = cpu_lduw_data(env, addr + (3 << DF_HALF));
4721 pwd->h[1] = cpu_lduw_data(env, addr + (2 << DF_HALF));
4722 pwd->h[2] = cpu_lduw_data(env, addr + (1 << DF_HALF));
4723 pwd->h[3] = cpu_lduw_data(env, addr + (0 << DF_HALF));
4724 pwd->h[4] = cpu_lduw_data(env, addr + (7 << DF_HALF));
4725 pwd->h[5] = cpu_lduw_data(env, addr + (6 << DF_HALF));
4726 pwd->h[6] = cpu_lduw_data(env, addr + (5 << DF_HALF));
4727 pwd->h[7] = cpu_lduw_data(env, addr + (4 << DF_HALF));
4728 #endif
4729 #endif
4730 }
4731
4732 void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd,
4733 target_ulong addr)
4734 {
4735 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4736 MEMOP_IDX(DF_WORD)
4737 #if !defined(CONFIG_USER_ONLY)
4738 #if !defined(HOST_WORDS_BIGENDIAN)
4739 pwd->w[0] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC());
4740 pwd->w[1] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC());
4741 pwd->w[2] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC());
4742 pwd->w[3] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC());
4743 #else
4744 pwd->w[0] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC());
4745 pwd->w[1] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC());
4746 pwd->w[2] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC());
4747 pwd->w[3] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC());
4748 #endif
4749 #else
4750 #if !defined(HOST_WORDS_BIGENDIAN)
4751 pwd->w[0] = cpu_ldl_data(env, addr + (0 << DF_WORD));
4752 pwd->w[1] = cpu_ldl_data(env, addr + (1 << DF_WORD));
4753 pwd->w[2] = cpu_ldl_data(env, addr + (2 << DF_WORD));
4754 pwd->w[3] = cpu_ldl_data(env, addr + (3 << DF_WORD));
4755 #else
4756 pwd->w[0] = cpu_ldl_data(env, addr + (1 << DF_WORD));
4757 pwd->w[1] = cpu_ldl_data(env, addr + (0 << DF_WORD));
4758 pwd->w[2] = cpu_ldl_data(env, addr + (3 << DF_WORD));
4759 pwd->w[3] = cpu_ldl_data(env, addr + (2 << DF_WORD));
4760 #endif
4761 #endif
4762 }
4763
4764 void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd,
4765 target_ulong addr)
4766 {
4767 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4768 MEMOP_IDX(DF_DOUBLE)
4769 #if !defined(CONFIG_USER_ONLY)
4770 pwd->d[0] = helper_ret_ldq_mmu(env, addr + (0 << DF_DOUBLE), oi, GETPC());
4771 pwd->d[1] = helper_ret_ldq_mmu(env, addr + (1 << DF_DOUBLE), oi, GETPC());
4772 #else
4773 pwd->d[0] = cpu_ldq_data(env, addr + (0 << DF_DOUBLE));
4774 pwd->d[1] = cpu_ldq_data(env, addr + (1 << DF_DOUBLE));
4775 #endif
4776 }
4777
4778 #define MSA_PAGESPAN(x) \
4779 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >= TARGET_PAGE_SIZE)
4780
4781 static inline void ensure_writable_pages(CPUMIPSState *env,
4782 target_ulong addr,
4783 int mmu_idx,
4784 uintptr_t retaddr)
4785 {
4786 /* FIXME: Probe the actual accesses (pass and use a size) */
4787 if (unlikely(MSA_PAGESPAN(addr))) {
4788 /* first page */
4789 probe_write(env, addr, 0, mmu_idx, retaddr);
4790 /* second page */
4791 addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4792 probe_write(env, addr, 0, mmu_idx, retaddr);
4793 }
4794 }
4795
4796 void helper_msa_st_b(CPUMIPSState *env, uint32_t wd,
4797 target_ulong addr)
4798 {
4799 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4800 int mmu_idx = cpu_mmu_index(env, false);
4801
4802 MEMOP_IDX(DF_BYTE)
4803 ensure_writable_pages(env, addr, mmu_idx, GETPC());
4804 #if !defined(CONFIG_USER_ONLY)
4805 #if !defined(HOST_WORDS_BIGENDIAN)
4806 helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[0], oi, GETPC());
4807 helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[1], oi, GETPC());
4808 helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[2], oi, GETPC());
4809 helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[3], oi, GETPC());
4810 helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[4], oi, GETPC());
4811 helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[5], oi, GETPC());
4812 helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[6], oi, GETPC());
4813 helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[7], oi, GETPC());
4814 helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[8], oi, GETPC());
4815 helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[9], oi, GETPC());
4816 helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[10], oi, GETPC());
4817 helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[11], oi, GETPC());
4818 helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[12], oi, GETPC());
4819 helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[13], oi, GETPC());
4820 helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[14], oi, GETPC());
4821 helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[15], oi, GETPC());
4822 #else
4823 helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[0], oi, GETPC());
4824 helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[1], oi, GETPC());
4825 helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[2], oi, GETPC());
4826 helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[3], oi, GETPC());
4827 helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[4], oi, GETPC());
4828 helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[5], oi, GETPC());
4829 helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[6], oi, GETPC());
4830 helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[7], oi, GETPC());
4831 helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[8], oi, GETPC());
4832 helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[9], oi, GETPC());
4833 helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[10], oi, GETPC());
4834 helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[11], oi, GETPC());
4835 helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[12], oi, GETPC());
4836 helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[13], oi, GETPC());
4837 helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[14], oi, GETPC());
4838 helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[15], oi, GETPC());
4839 #endif
4840 #else
4841 #if !defined(HOST_WORDS_BIGENDIAN)
4842 cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[0]);
4843 cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[1]);
4844 cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[2]);
4845 cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[3]);
4846 cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[4]);
4847 cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[5]);
4848 cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[6]);
4849 cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[7]);
4850 cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[8]);
4851 cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[9]);
4852 cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[10]);
4853 cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[11]);
4854 cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[12]);
4855 cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[13]);
4856 cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[14]);
4857 cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[15]);
4858 #else
4859 cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[0]);
4860 cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[1]);
4861 cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[2]);
4862 cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[3]);
4863 cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[4]);
4864 cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[5]);
4865 cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[6]);
4866 cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[7]);
4867 cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[8]);
4868 cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[9]);
4869 cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[10]);
4870 cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[11]);
4871 cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[12]);
4872 cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[13]);
4873 cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[14]);
4874 cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[15]);
4875 #endif
4876 #endif
4877 }
4878
4879 void helper_msa_st_h(CPUMIPSState *env, uint32_t wd,
4880 target_ulong addr)
4881 {
4882 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4883 int mmu_idx = cpu_mmu_index(env, false);
4884
4885 MEMOP_IDX(DF_HALF)
4886 ensure_writable_pages(env, addr, mmu_idx, GETPC());
4887 #if !defined(CONFIG_USER_ONLY)
4888 #if !defined(HOST_WORDS_BIGENDIAN)
4889 helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[0], oi, GETPC());
4890 helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[1], oi, GETPC());
4891 helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[2], oi, GETPC());
4892 helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[3], oi, GETPC());
4893 helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[4], oi, GETPC());
4894 helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[5], oi, GETPC());
4895 helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[6], oi, GETPC());
4896 helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[7], oi, GETPC());
4897 #else
4898 helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[0], oi, GETPC());
4899 helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[1], oi, GETPC());
4900 helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[2], oi, GETPC());
4901 helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[3], oi, GETPC());
4902 helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[4], oi, GETPC());
4903 helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[5], oi, GETPC());
4904 helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[6], oi, GETPC());
4905 helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[7], oi, GETPC());
4906 #endif
4907 #else
4908 #if !defined(HOST_WORDS_BIGENDIAN)
4909 cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[0]);
4910 cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[1]);
4911 cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[2]);
4912 cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[3]);
4913 cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[4]);
4914 cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[5]);
4915 cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[6]);
4916 cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[7]);
4917 #else
4918 cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[0]);
4919 cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[1]);
4920 cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[2]);
4921 cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[3]);
4922 cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[4]);
4923 cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[5]);
4924 cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[6]);
4925 cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[7]);
4926 #endif
4927 #endif
4928 }
4929
4930 void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,
4931 target_ulong addr)
4932 {
4933 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4934 int mmu_idx = cpu_mmu_index(env, false);
4935
4936 MEMOP_IDX(DF_WORD)
4937 ensure_writable_pages(env, addr, mmu_idx, GETPC());
4938 #if !defined(CONFIG_USER_ONLY)
4939 #if !defined(HOST_WORDS_BIGENDIAN)
4940 helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC());
4941 helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC());
4942 helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC());
4943 helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC());
4944 #else
4945 helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC());
4946 helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC());
4947 helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC());
4948 helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC());
4949 #endif
4950 #else
4951 #if !defined(HOST_WORDS_BIGENDIAN)
4952 cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[0]);
4953 cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[1]);
4954 cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[2]);
4955 cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[3]);
4956 #else
4957 cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[0]);
4958 cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[1]);
4959 cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[2]);
4960 cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[3]);
4961 #endif
4962 #endif
4963 }
4964
4965 void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
4966 target_ulong addr)
4967 {
4968 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4969 int mmu_idx = cpu_mmu_index(env, false);
4970
4971 MEMOP_IDX(DF_DOUBLE)
4972 ensure_writable_pages(env, addr, mmu_idx, GETPC());
4973 #if !defined(CONFIG_USER_ONLY)
4974 helper_ret_stq_mmu(env, addr + (0 << DF_DOUBLE), pwd->d[0], oi, GETPC());
4975 helper_ret_stq_mmu(env, addr + (1 << DF_DOUBLE), pwd->d[1], oi, GETPC());
4976 #else
4977 cpu_stq_data(env, addr + (0 << DF_DOUBLE), pwd->d[0]);
4978 cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]);
4979 #endif
4980 }
4981
4982 void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
4983 {
4984 #ifndef CONFIG_USER_ONLY
4985 target_ulong index = addr & 0x1fffffff;
4986 if (op == 9) {
4987 /* Index Store Tag */
4988 memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
4989 MO_64, MEMTXATTRS_UNSPECIFIED);
4990 } else if (op == 5) {
4991 /* Index Load Tag */
4992 memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
4993 MO_64, MEMTXATTRS_UNSPECIFIED);
4994 }
4995 #endif
4996 }
Random patches