2 * MIPS internal definitions and helpers
4 * This work is licensed under the terms of the GNU GPL, version 2 or later.
5 * See the COPYING file in the top-level directory.
8 #ifndef MIPS_INTERNAL_H
9 #define MIPS_INTERNAL_H
11 #include "fpu/softfloat-helpers.h"
14 * MMU types, the first four entries have the same layout as the
35 int32_t CP0_Config4_rw_bitmask
;
37 int32_t CP0_Config5_rw_bitmask
;
40 target_ulong CP0_LLAddr_rw_bitmask
;
44 int32_t CP0_Status_rw_bitmask
;
45 int32_t CP0_TCStatus_rw_bitmask
;
48 int32_t CP1_fcr31_rw_bitmask
;
53 int32_t CP0_SRSConf0_rw_bitmask
;
55 int32_t CP0_SRSConf1_rw_bitmask
;
57 int32_t CP0_SRSConf2_rw_bitmask
;
59 int32_t CP0_SRSConf3_rw_bitmask
;
61 int32_t CP0_SRSConf4_rw_bitmask
;
63 int32_t CP0_PageGrain_rw_bitmask
;
64 int32_t CP0_PageGrain
;
65 target_ulong CP0_EBaseWG_rw_bitmask
;
67 enum mips_mmu_types mmu_type
;
71 extern const struct mips_def_t mips_defs
[];
72 extern const int mips_defs_number
;
74 enum CPUMIPSMSADataFormat
{
81 void mips_cpu_do_interrupt(CPUState
*cpu
);
82 bool mips_cpu_exec_interrupt(CPUState
*cpu
, int int_req
);
83 void mips_cpu_dump_state(CPUState
*cpu
, FILE *f
, int flags
);
84 hwaddr
mips_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
85 int mips_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
86 int mips_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
87 void mips_cpu_do_unaligned_access(CPUState
*cpu
, vaddr addr
,
88 MMUAccessType access_type
,
89 int mmu_idx
, uintptr_t retaddr
);
91 #if !defined(CONFIG_USER_ONLY)
93 typedef struct r4k_tlb_t r4k_tlb_t
;
109 unsigned int EHINV
:1;
113 struct CPUMIPSTLBContext
{
116 int (*map_address
)(struct CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
117 target_ulong address
, int rw
, int access_type
);
118 void (*helper_tlbwi
)(struct CPUMIPSState
*env
);
119 void (*helper_tlbwr
)(struct CPUMIPSState
*env
);
120 void (*helper_tlbp
)(struct CPUMIPSState
*env
);
121 void (*helper_tlbr
)(struct CPUMIPSState
*env
);
122 void (*helper_tlbinv
)(struct CPUMIPSState
*env
);
123 void (*helper_tlbinvf
)(struct CPUMIPSState
*env
);
126 r4k_tlb_t tlb
[MIPS_TLB_MAX
];
131 int no_mmu_map_address(CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
132 target_ulong address
, int rw
, int access_type
);
133 int fixed_mmu_map_address(CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
134 target_ulong address
, int rw
, int access_type
);
135 int r4k_map_address(CPUMIPSState
*env
, hwaddr
*physical
, int *prot
,
136 target_ulong address
, int rw
, int access_type
);
137 void r4k_helper_tlbwi(CPUMIPSState
*env
);
138 void r4k_helper_tlbwr(CPUMIPSState
*env
);
139 void r4k_helper_tlbp(CPUMIPSState
*env
);
140 void r4k_helper_tlbr(CPUMIPSState
*env
);
141 void r4k_helper_tlbinv(CPUMIPSState
*env
);
142 void r4k_helper_tlbinvf(CPUMIPSState
*env
);
143 void r4k_invalidate_tlb(CPUMIPSState
*env
, int idx
, int use_extra
);
145 void mips_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
146 vaddr addr
, unsigned size
,
147 MMUAccessType access_type
,
148 int mmu_idx
, MemTxAttrs attrs
,
149 MemTxResult response
, uintptr_t retaddr
);
150 hwaddr
cpu_mips_translate_address(CPUMIPSState
*env
, target_ulong address
,
154 #define cpu_signal_handler cpu_mips_signal_handler
156 #ifndef CONFIG_USER_ONLY
157 extern const VMStateDescription vmstate_mips_cpu
;
160 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState
*env
)
162 return (env
->CP0_Status
& (1 << CP0St_IE
)) &&
163 !(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
164 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
165 !(env
->hflags
& MIPS_HFLAG_DM
) &&
167 * Note that the TCStatus IXMT field is initialized to zero,
168 * and only MT capable cores can set it to one. So we don't
169 * need to check for MT capabilities here.
171 !(env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_IXMT
));
174 /* Check if there is pending and not masked out interrupt */
175 static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState
*env
)
181 pending
= env
->CP0_Cause
& CP0Ca_IP_mask
;
182 status
= env
->CP0_Status
& CP0Ca_IP_mask
;
184 if (env
->CP0_Config3
& (1 << CP0C3_VEIC
)) {
186 * A MIPS configured with a vectorizing external interrupt controller
187 * will feed a vector into the Cause pending lines. The core treats
188 * the status lines as a vector level, not as indiviual masks.
190 r
= pending
> status
;
193 * A MIPS configured with compatibility or VInt (Vectored Interrupts)
194 * treats the pending lines as individual interrupt lines, the status
195 * lines are individual masks.
197 r
= (pending
& status
) != 0;
202 void mips_tcg_init(void);
204 /* TODO QOM'ify CPU reset and remove */
205 void cpu_state_reset(CPUMIPSState
*s
);
206 void cpu_mips_realize_env(CPUMIPSState
*env
);
209 uint32_t cpu_mips_get_random(CPUMIPSState
*env
);
210 uint32_t cpu_mips_get_count(CPUMIPSState
*env
);
211 void cpu_mips_store_count(CPUMIPSState
*env
, uint32_t value
);
212 void cpu_mips_store_compare(CPUMIPSState
*env
, uint32_t value
);
213 void cpu_mips_start_count(CPUMIPSState
*env
);
214 void cpu_mips_stop_count(CPUMIPSState
*env
);
217 bool mips_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
218 MMUAccessType access_type
, int mmu_idx
,
219 bool probe
, uintptr_t retaddr
);
222 uint32_t float_class_s(uint32_t arg
, float_status
*fst
);
223 uint64_t float_class_d(uint64_t arg
, float_status
*fst
);
225 extern unsigned int ieee_rm
[];
226 int ieee_ex_to_mips(int xcpt
);
227 void update_pagemask(CPUMIPSState
*env
, target_ulong arg1
, int32_t *pagemask
);
229 static inline void restore_rounding_mode(CPUMIPSState
*env
)
231 set_float_rounding_mode(ieee_rm
[env
->active_fpu
.fcr31
& 3],
232 &env
->active_fpu
.fp_status
);
235 static inline void restore_flush_mode(CPUMIPSState
*env
)
237 set_flush_to_zero((env
->active_fpu
.fcr31
& (1 << FCR31_FS
)) != 0,
238 &env
->active_fpu
.fp_status
);
241 static inline void restore_snan_bit_mode(CPUMIPSState
*env
)
243 set_snan_bit_is_one((env
->active_fpu
.fcr31
& (1 << FCR31_NAN2008
)) == 0,
244 &env
->active_fpu
.fp_status
);
247 static inline void restore_fp_status(CPUMIPSState
*env
)
249 restore_rounding_mode(env
);
250 restore_flush_mode(env
);
251 restore_snan_bit_mode(env
);
254 static inline void restore_msa_fp_status(CPUMIPSState
*env
)
256 float_status
*status
= &env
->active_tc
.msa_fp_status
;
257 int rounding_mode
= (env
->active_tc
.msacsr
& MSACSR_RM_MASK
) >> MSACSR_RM
;
258 bool flush_to_zero
= (env
->active_tc
.msacsr
& MSACSR_FS_MASK
) != 0;
260 set_float_rounding_mode(ieee_rm
[rounding_mode
], status
);
261 set_flush_to_zero(flush_to_zero
, status
);
262 set_flush_inputs_to_zero(flush_to_zero
, status
);
265 static inline void restore_pamask(CPUMIPSState
*env
)
267 if (env
->hflags
& MIPS_HFLAG_ELPA
) {
268 env
->PAMask
= (1ULL << env
->PABITS
) - 1;
270 env
->PAMask
= PAMASK_BASE
;
274 static inline int mips_vpe_active(CPUMIPSState
*env
)
278 /* Check that the VPE is enabled. */
279 if (!(env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_EVP
))) {
282 /* Check that the VPE is activated. */
283 if (!(env
->CP0_VPEConf0
& (1 << CP0VPEC0_VPA
))) {
288 * Now verify that there are active thread contexts in the VPE.
290 * This assumes the CPU model will internally reschedule threads
291 * if the active one goes to sleep. If there are no threads available
292 * the active one will be in a sleeping state, and we can turn off
295 if (!(env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_A
))) {
296 /* TC is not activated. */
299 if (env
->active_tc
.CP0_TCHalt
& 1) {
300 /* TC is in halt state. */
307 static inline int mips_vp_active(CPUMIPSState
*env
)
309 CPUState
*other_cs
= first_cpu
;
311 /* Check if the VP disabled other VPs (which means the VP is enabled) */
312 if ((env
->CP0_VPControl
>> CP0VPCtl_DIS
) & 1) {
316 /* Check if the virtual processor is disabled due to a DVP */
317 CPU_FOREACH(other_cs
) {
318 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
319 if ((&other_cpu
->env
!= env
) &&
320 ((other_cpu
->env
.CP0_VPControl
>> CP0VPCtl_DIS
) & 1)) {
327 static inline void compute_hflags(CPUMIPSState
*env
)
329 env
->hflags
&= ~(MIPS_HFLAG_COP1X
| MIPS_HFLAG_64
| MIPS_HFLAG_CP0
|
330 MIPS_HFLAG_F64
| MIPS_HFLAG_FPU
| MIPS_HFLAG_KSU
|
331 MIPS_HFLAG_AWRAP
| MIPS_HFLAG_DSP
| MIPS_HFLAG_DSP_R2
|
332 MIPS_HFLAG_DSP_R3
| MIPS_HFLAG_SBRI
| MIPS_HFLAG_MSA
|
333 MIPS_HFLAG_FRE
| MIPS_HFLAG_ELPA
| MIPS_HFLAG_ERL
);
334 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
335 env
->hflags
|= MIPS_HFLAG_ERL
;
337 if (!(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
338 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
339 !(env
->hflags
& MIPS_HFLAG_DM
)) {
340 env
->hflags
|= (env
->CP0_Status
>> CP0St_KSU
) &
343 #if defined(TARGET_MIPS64)
344 if ((env
->insn_flags
& ISA_MIPS3
) &&
345 (((env
->hflags
& MIPS_HFLAG_KSU
) != MIPS_HFLAG_UM
) ||
346 (env
->CP0_Status
& (1 << CP0St_PX
)) ||
347 (env
->CP0_Status
& (1 << CP0St_UX
)))) {
348 env
->hflags
|= MIPS_HFLAG_64
;
351 if (!(env
->insn_flags
& ISA_MIPS3
)) {
352 env
->hflags
|= MIPS_HFLAG_AWRAP
;
353 } else if (((env
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_UM
) &&
354 !(env
->CP0_Status
& (1 << CP0St_UX
))) {
355 env
->hflags
|= MIPS_HFLAG_AWRAP
;
356 } else if (env
->insn_flags
& ISA_MIPS64R6
) {
357 /* Address wrapping for Supervisor and Kernel is specified in R6 */
358 if ((((env
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_SM
) &&
359 !(env
->CP0_Status
& (1 << CP0St_SX
))) ||
360 (((env
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_KM
) &&
361 !(env
->CP0_Status
& (1 << CP0St_KX
)))) {
362 env
->hflags
|= MIPS_HFLAG_AWRAP
;
366 if (((env
->CP0_Status
& (1 << CP0St_CU0
)) &&
367 !(env
->insn_flags
& ISA_MIPS32R6
)) ||
368 !(env
->hflags
& MIPS_HFLAG_KSU
)) {
369 env
->hflags
|= MIPS_HFLAG_CP0
;
371 if (env
->CP0_Status
& (1 << CP0St_CU1
)) {
372 env
->hflags
|= MIPS_HFLAG_FPU
;
374 if (env
->CP0_Status
& (1 << CP0St_FR
)) {
375 env
->hflags
|= MIPS_HFLAG_F64
;
377 if (((env
->hflags
& MIPS_HFLAG_KSU
) != MIPS_HFLAG_KM
) &&
378 (env
->CP0_Config5
& (1 << CP0C5_SBRI
))) {
379 env
->hflags
|= MIPS_HFLAG_SBRI
;
381 if (env
->insn_flags
& ASE_DSP_R3
) {
383 * Our cpu supports DSP R3 ASE, so enable
384 * access to DSP R3 resources.
386 if (env
->CP0_Status
& (1 << CP0St_MX
)) {
387 env
->hflags
|= MIPS_HFLAG_DSP
| MIPS_HFLAG_DSP_R2
|
390 } else if (env
->insn_flags
& ASE_DSP_R2
) {
392 * Our cpu supports DSP R2 ASE, so enable
393 * access to DSP R2 resources.
395 if (env
->CP0_Status
& (1 << CP0St_MX
)) {
396 env
->hflags
|= MIPS_HFLAG_DSP
| MIPS_HFLAG_DSP_R2
;
399 } else if (env
->insn_flags
& ASE_DSP
) {
401 * Our cpu supports DSP ASE, so enable
402 * access to DSP resources.
404 if (env
->CP0_Status
& (1 << CP0St_MX
)) {
405 env
->hflags
|= MIPS_HFLAG_DSP
;
409 if (env
->insn_flags
& ISA_MIPS32R2
) {
410 if (env
->active_fpu
.fcr0
& (1 << FCR0_F64
)) {
411 env
->hflags
|= MIPS_HFLAG_COP1X
;
413 } else if (env
->insn_flags
& ISA_MIPS32
) {
414 if (env
->hflags
& MIPS_HFLAG_64
) {
415 env
->hflags
|= MIPS_HFLAG_COP1X
;
417 } else if (env
->insn_flags
& ISA_MIPS4
) {
419 * All supported MIPS IV CPUs use the XX (CU3) to enable
420 * and disable the MIPS IV extensions to the MIPS III ISA.
421 * Some other MIPS IV CPUs ignore the bit, so the check here
422 * would be too restrictive for them.
424 if (env
->CP0_Status
& (1U << CP0St_CU3
)) {
425 env
->hflags
|= MIPS_HFLAG_COP1X
;
428 if (env
->insn_flags
& ASE_MSA
) {
429 if (env
->CP0_Config5
& (1 << CP0C5_MSAEn
)) {
430 env
->hflags
|= MIPS_HFLAG_MSA
;
433 if (env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) {
434 if (env
->CP0_Config5
& (1 << CP0C5_FRE
)) {
435 env
->hflags
|= MIPS_HFLAG_FRE
;
438 if (env
->CP0_Config3
& (1 << CP0C3_LPA
)) {
439 if (env
->CP0_PageGrain
& (1 << CP0PG_ELPA
)) {
440 env
->hflags
|= MIPS_HFLAG_ELPA
;
445 void cpu_mips_tlb_flush(CPUMIPSState
*env
);
446 void sync_c0_status(CPUMIPSState
*env
, CPUMIPSState
*cpu
, int tc
);
447 void cpu_mips_store_status(CPUMIPSState
*env
, target_ulong val
);
448 void cpu_mips_store_cause(CPUMIPSState
*env
, target_ulong val
);
450 void QEMU_NORETURN
do_raise_exception_err(CPUMIPSState
*env
, uint32_t exception
,
451 int error_code
, uintptr_t pc
);
453 static inline void QEMU_NORETURN
do_raise_exception(CPUMIPSState
*env
,
457 do_raise_exception_err(env
, exception
, 0, pc
);