Tranfer dirty blocks during iterative phase
[qemu/kevin.git] / target-arm / cpu.h
blob4a1c53f24f97fb4a5c9aa0b91c4d3c3b6280840e
1 /*
2 * ARM virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #ifndef CPU_ARM_H
20 #define CPU_ARM_H
22 #define TARGET_LONG_BITS 32
24 #define ELF_MACHINE EM_ARM
26 #define CPUState struct CPUARMState
28 #include "cpu-defs.h"
30 #include "softfloat.h"
32 #define TARGET_HAS_ICE 1
34 #define EXCP_UDEF 1 /* undefined instruction */
35 #define EXCP_SWI 2 /* software interrupt */
36 #define EXCP_PREFETCH_ABORT 3
37 #define EXCP_DATA_ABORT 4
38 #define EXCP_IRQ 5
39 #define EXCP_FIQ 6
40 #define EXCP_BKPT 7
41 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
42 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
43 #define EXCP_STREX 10
45 #define ARMV7M_EXCP_RESET 1
46 #define ARMV7M_EXCP_NMI 2
47 #define ARMV7M_EXCP_HARD 3
48 #define ARMV7M_EXCP_MEM 4
49 #define ARMV7M_EXCP_BUS 5
50 #define ARMV7M_EXCP_USAGE 6
51 #define ARMV7M_EXCP_SVC 11
52 #define ARMV7M_EXCP_DEBUG 12
53 #define ARMV7M_EXCP_PENDSV 14
54 #define ARMV7M_EXCP_SYSTICK 15
56 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
57 int srcreg, int operand, uint32_t value);
58 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
59 int dstreg, int operand);
61 struct arm_boot_info;
63 #define NB_MMU_MODES 2
65 /* We currently assume float and double are IEEE single and double
66 precision respectively.
67 Doing runtime conversions is tricky because VFP registers may contain
68 integer values (eg. as the result of a FTOSI instruction).
69 s<2n> maps to the least significant half of d<n>
70 s<2n+1> maps to the most significant half of d<n>
73 typedef struct CPUARMState {
74 /* Regs for current mode. */
75 uint32_t regs[16];
76 /* Frequently accessed CPSR bits are stored separately for efficiently.
77 This contains all the other bits. Use cpsr_{read,write} to access
78 the whole CPSR. */
79 uint32_t uncached_cpsr;
80 uint32_t spsr;
82 /* Banked registers. */
83 uint32_t banked_spsr[6];
84 uint32_t banked_r13[6];
85 uint32_t banked_r14[6];
87 /* These hold r8-r12. */
88 uint32_t usr_regs[5];
89 uint32_t fiq_regs[5];
91 /* cpsr flag cache for faster execution */
92 uint32_t CF; /* 0 or 1 */
93 uint32_t VF; /* V is the bit 31. All other bits are undefined */
94 uint32_t NF; /* N is bit 31. All other bits are undefined. */
95 uint32_t ZF; /* Z set if zero. */
96 uint32_t QF; /* 0 or 1 */
97 uint32_t GE; /* cpsr[19:16] */
98 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
99 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
101 /* System control coprocessor (cp15) */
102 struct {
103 uint32_t c0_cpuid;
104 uint32_t c0_cachetype;
105 uint32_t c0_ccsid[16]; /* Cache size. */
106 uint32_t c0_clid; /* Cache level. */
107 uint32_t c0_cssel; /* Cache size selection. */
108 uint32_t c0_c1[8]; /* Feature registers. */
109 uint32_t c0_c2[8]; /* Instruction set registers. */
110 uint32_t c1_sys; /* System control register. */
111 uint32_t c1_coproc; /* Coprocessor access register. */
112 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
113 uint32_t c2_base0; /* MMU translation table base 0. */
114 uint32_t c2_base1; /* MMU translation table base 1. */
115 uint32_t c2_control; /* MMU translation table base control. */
116 uint32_t c2_mask; /* MMU translation table base selection mask. */
117 uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
118 uint32_t c2_data; /* MPU data cachable bits. */
119 uint32_t c2_insn; /* MPU instruction cachable bits. */
120 uint32_t c3; /* MMU domain access control register
121 MPU write buffer control. */
122 uint32_t c5_insn; /* Fault status registers. */
123 uint32_t c5_data;
124 uint32_t c6_region[8]; /* MPU base/size registers. */
125 uint32_t c6_insn; /* Fault address registers. */
126 uint32_t c6_data;
127 uint32_t c9_insn; /* Cache lockdown registers. */
128 uint32_t c9_data;
129 uint32_t c13_fcse; /* FCSE PID. */
130 uint32_t c13_context; /* Context ID. */
131 uint32_t c13_tls1; /* User RW Thread register. */
132 uint32_t c13_tls2; /* User RO Thread register. */
133 uint32_t c13_tls3; /* Privileged Thread register. */
134 uint32_t c15_cpar; /* XScale Coprocessor Access Register */
135 uint32_t c15_ticonfig; /* TI925T configuration byte. */
136 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
137 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
138 uint32_t c15_threadid; /* TI debugger thread-ID. */
139 } cp15;
141 struct {
142 uint32_t other_sp;
143 uint32_t vecbase;
144 uint32_t basepri;
145 uint32_t control;
146 int current_sp;
147 int exception;
148 int pending_exception;
149 void *nvic;
150 } v7m;
152 /* Coprocessor IO used by peripherals */
153 struct {
154 ARMReadCPFunc *cp_read;
155 ARMWriteCPFunc *cp_write;
156 void *opaque;
157 } cp[15];
159 /* Thumb-2 EE state. */
160 uint32_t teecr;
161 uint32_t teehbr;
163 /* Internal CPU feature flags. */
164 uint32_t features;
166 /* Callback for vectored interrupt controller. */
167 int (*get_irq_vector)(struct CPUARMState *);
168 void *irq_opaque;
170 /* VFP coprocessor state. */
171 struct {
172 float64 regs[32];
174 uint32_t xregs[16];
175 /* We store these fpcsr fields separately for convenience. */
176 int vec_len;
177 int vec_stride;
179 /* scratch space when Tn are not sufficient. */
180 uint32_t scratch[8];
182 float_status fp_status;
183 } vfp;
184 uint32_t exclusive_addr;
185 uint32_t exclusive_val;
186 uint32_t exclusive_high;
187 #if defined(CONFIG_USER_ONLY)
188 uint32_t exclusive_test;
189 uint32_t exclusive_info;
190 #endif
192 /* iwMMXt coprocessor state. */
193 struct {
194 uint64_t regs[16];
195 uint64_t val;
197 uint32_t cregs[16];
198 } iwmmxt;
200 #if defined(CONFIG_USER_ONLY)
201 /* For usermode syscall translation. */
202 int eabi;
203 #endif
205 CPU_COMMON
207 /* These fields after the common ones so they are preserved on reset. */
208 struct arm_boot_info *boot_info;
209 } CPUARMState;
211 CPUARMState *cpu_arm_init(const char *cpu_model);
212 void arm_translate_init(void);
213 int cpu_arm_exec(CPUARMState *s);
214 void cpu_arm_close(CPUARMState *s);
215 void do_interrupt(CPUARMState *);
216 void switch_mode(CPUARMState *, int);
217 uint32_t do_arm_semihosting(CPUARMState *env);
219 /* you can call this signal handler from your SIGBUS and SIGSEGV
220 signal handlers to inform the virtual CPU of exceptions. non zero
221 is returned if the signal was handled by the virtual CPU. */
222 int cpu_arm_signal_handler(int host_signum, void *pinfo,
223 void *puc);
224 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
225 int mmu_idx, int is_softmuu);
226 #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
228 void cpu_lock(void);
229 void cpu_unlock(void);
230 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
232 env->cp15.c13_tls2 = newtls;
235 #define CPSR_M (0x1f)
236 #define CPSR_T (1 << 5)
237 #define CPSR_F (1 << 6)
238 #define CPSR_I (1 << 7)
239 #define CPSR_A (1 << 8)
240 #define CPSR_E (1 << 9)
241 #define CPSR_IT_2_7 (0xfc00)
242 #define CPSR_GE (0xf << 16)
243 #define CPSR_RESERVED (0xf << 20)
244 #define CPSR_J (1 << 24)
245 #define CPSR_IT_0_1 (3 << 25)
246 #define CPSR_Q (1 << 27)
247 #define CPSR_V (1 << 28)
248 #define CPSR_C (1 << 29)
249 #define CPSR_Z (1 << 30)
250 #define CPSR_N (1 << 31)
251 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
253 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
254 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
255 /* Bits writable in user mode. */
256 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
257 /* Execution state bits. MRS read as zero, MSR writes ignored. */
258 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
260 /* Return the current CPSR value. */
261 uint32_t cpsr_read(CPUARMState *env);
262 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
263 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
265 /* Return the current xPSR value. */
266 static inline uint32_t xpsr_read(CPUARMState *env)
268 int ZF;
269 ZF = (env->ZF == 0);
270 return (env->NF & 0x80000000) | (ZF << 30)
271 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
272 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
273 | ((env->condexec_bits & 0xfc) << 8)
274 | env->v7m.exception;
277 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
278 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
280 if (mask & CPSR_NZCV) {
281 env->ZF = (~val) & CPSR_Z;
282 env->NF = val;
283 env->CF = (val >> 29) & 1;
284 env->VF = (val << 3) & 0x80000000;
286 if (mask & CPSR_Q)
287 env->QF = ((val & CPSR_Q) != 0);
288 if (mask & (1 << 24))
289 env->thumb = ((val & (1 << 24)) != 0);
290 if (mask & CPSR_IT_0_1) {
291 env->condexec_bits &= ~3;
292 env->condexec_bits |= (val >> 25) & 3;
294 if (mask & CPSR_IT_2_7) {
295 env->condexec_bits &= 3;
296 env->condexec_bits |= (val >> 8) & 0xfc;
298 if (mask & 0x1ff) {
299 env->v7m.exception = val & 0x1ff;
303 enum arm_cpu_mode {
304 ARM_CPU_MODE_USR = 0x10,
305 ARM_CPU_MODE_FIQ = 0x11,
306 ARM_CPU_MODE_IRQ = 0x12,
307 ARM_CPU_MODE_SVC = 0x13,
308 ARM_CPU_MODE_ABT = 0x17,
309 ARM_CPU_MODE_UND = 0x1b,
310 ARM_CPU_MODE_SYS = 0x1f
313 /* VFP system registers. */
314 #define ARM_VFP_FPSID 0
315 #define ARM_VFP_FPSCR 1
316 #define ARM_VFP_MVFR1 6
317 #define ARM_VFP_MVFR0 7
318 #define ARM_VFP_FPEXC 8
319 #define ARM_VFP_FPINST 9
320 #define ARM_VFP_FPINST2 10
322 /* iwMMXt coprocessor control registers. */
323 #define ARM_IWMMXT_wCID 0
324 #define ARM_IWMMXT_wCon 1
325 #define ARM_IWMMXT_wCSSF 2
326 #define ARM_IWMMXT_wCASF 3
327 #define ARM_IWMMXT_wCGR0 8
328 #define ARM_IWMMXT_wCGR1 9
329 #define ARM_IWMMXT_wCGR2 10
330 #define ARM_IWMMXT_wCGR3 11
332 enum arm_features {
333 ARM_FEATURE_VFP,
334 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
335 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
336 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
337 ARM_FEATURE_V6,
338 ARM_FEATURE_V6K,
339 ARM_FEATURE_V7,
340 ARM_FEATURE_THUMB2,
341 ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
342 ARM_FEATURE_VFP3,
343 ARM_FEATURE_VFP_FP16,
344 ARM_FEATURE_NEON,
345 ARM_FEATURE_DIV,
346 ARM_FEATURE_M, /* Microcontroller profile. */
347 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
348 ARM_FEATURE_THUMB2EE
351 static inline int arm_feature(CPUARMState *env, int feature)
353 return (env->features & (1u << feature)) != 0;
356 void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
358 /* Interface between CPU and Interrupt controller. */
359 void armv7m_nvic_set_pending(void *opaque, int irq);
360 int armv7m_nvic_acknowledge_irq(void *opaque);
361 void armv7m_nvic_complete_irq(void *opaque, int irq);
363 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
364 ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
365 void *opaque);
367 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
368 Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
369 conventional cores (ie. Application or Realtime profile). */
371 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
372 #define ARM_CPUID(env) (env->cp15.c0_cpuid)
374 #define ARM_CPUID_ARM1026 0x4106a262
375 #define ARM_CPUID_ARM926 0x41069265
376 #define ARM_CPUID_ARM946 0x41059461
377 #define ARM_CPUID_TI915T 0x54029152
378 #define ARM_CPUID_TI925T 0x54029252
379 #define ARM_CPUID_PXA250 0x69052100
380 #define ARM_CPUID_PXA255 0x69052d00
381 #define ARM_CPUID_PXA260 0x69052903
382 #define ARM_CPUID_PXA261 0x69052d05
383 #define ARM_CPUID_PXA262 0x69052d06
384 #define ARM_CPUID_PXA270 0x69054110
385 #define ARM_CPUID_PXA270_A0 0x69054110
386 #define ARM_CPUID_PXA270_A1 0x69054111
387 #define ARM_CPUID_PXA270_B0 0x69054112
388 #define ARM_CPUID_PXA270_B1 0x69054113
389 #define ARM_CPUID_PXA270_C0 0x69054114
390 #define ARM_CPUID_PXA270_C5 0x69054117
391 #define ARM_CPUID_ARM1136 0x4117b363
392 #define ARM_CPUID_ARM1136_R2 0x4107b362
393 #define ARM_CPUID_ARM11MPCORE 0x410fb022
394 #define ARM_CPUID_CORTEXA8 0x410fc080
395 #define ARM_CPUID_CORTEXA9 0x410fc090
396 #define ARM_CPUID_CORTEXM3 0x410fc231
397 #define ARM_CPUID_ANY 0xffffffff
399 #if defined(CONFIG_USER_ONLY)
400 #define TARGET_PAGE_BITS 12
401 #else
402 /* The ARM MMU allows 1k pages. */
403 /* ??? Linux doesn't actually use these, and they're deprecated in recent
404 architecture revisions. Maybe a configure option to disable them. */
405 #define TARGET_PAGE_BITS 10
406 #endif
408 #define cpu_init cpu_arm_init
409 #define cpu_exec cpu_arm_exec
410 #define cpu_gen_code cpu_arm_gen_code
411 #define cpu_signal_handler cpu_arm_signal_handler
412 #define cpu_list arm_cpu_list
414 #define CPU_SAVE_VERSION 2
416 /* MMU modes definitions */
417 #define MMU_MODE0_SUFFIX _kernel
418 #define MMU_MODE1_SUFFIX _user
419 #define MMU_USER_IDX 1
420 static inline int cpu_mmu_index (CPUState *env)
422 return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
425 #if defined(CONFIG_USER_ONLY)
426 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
428 if (newsp)
429 env->regs[13] = newsp;
430 env->regs[0] = 0;
432 #endif
434 #include "cpu-all.h"
435 #include "exec-all.h"
437 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
439 env->regs[15] = tb->pc;
442 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
443 target_ulong *cs_base, int *flags)
445 *pc = env->regs[15];
446 *cs_base = 0;
447 *flags = env->thumb | (env->vfp.vec_len << 1)
448 | (env->vfp.vec_stride << 4) | (env->condexec_bits << 8);
449 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
450 *flags |= (1 << 6);
451 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
452 *flags |= (1 << 7);
455 #endif