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target-i386: kvm: Allocate kvm_msrs struct once per VCPU
[qemu/kevin.git] / target-i386 / kvm.c
blob7ad9c32326ffeab7cb5158ab5fe01647c480ba89
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/mman.h>
19 #include <sys/utsname.h>
20
21 #include <linux/kvm.h>
22 #include <linux/kvm_para.h>
23
24 #include "qemu-common.h"
25 #include "cpu.h"
26 #include "sysemu/sysemu.h"
27 #include "sysemu/kvm_int.h"
28 #include "kvm_i386.h"
29 #include "hyperv.h"
30
31 #include "exec/gdbstub.h"
32 #include "qemu/host-utils.h"
33 #include "qemu/config-file.h"
34 #include "qemu/error-report.h"
35 #include "hw/i386/pc.h"
36 #include "hw/i386/apic.h"
37 #include "hw/i386/apic_internal.h"
38 #include "hw/i386/apic-msidef.h"
39
40 #include "exec/ioport.h"
41 #include "standard-headers/asm-x86/hyperv.h"
42 #include "hw/pci/pci.h"
43 #include "hw/pci/msi.h"
44 #include "migration/migration.h"
45 #include "exec/memattrs.h"
46
47 //#define DEBUG_KVM
48
49 #ifdef DEBUG_KVM
50 #define DPRINTF(fmt, ...) \
51 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
52 #else
53 #define DPRINTF(fmt, ...) \
54 do { } while (0)
55 #endif
56
57 #define MSR_KVM_WALL_CLOCK 0x11
58 #define MSR_KVM_SYSTEM_TIME 0x12
59
60 #define MSR_BUF_SIZE \
61 (sizeof(struct kvm_msrs) + 150 * sizeof(struct kvm_msr_entry))
62
63 #ifndef BUS_MCEERR_AR
64 #define BUS_MCEERR_AR 4
65 #endif
66 #ifndef BUS_MCEERR_AO
67 #define BUS_MCEERR_AO 5
68 #endif
69
70 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
71 KVM_CAP_INFO(SET_TSS_ADDR),
72 KVM_CAP_INFO(EXT_CPUID),
73 KVM_CAP_INFO(MP_STATE),
74 KVM_CAP_LAST_INFO
75 };
76
77 static bool has_msr_star;
78 static bool has_msr_hsave_pa;
79 static bool has_msr_tsc_aux;
80 static bool has_msr_tsc_adjust;
81 static bool has_msr_tsc_deadline;
82 static bool has_msr_feature_control;
83 static bool has_msr_async_pf_en;
84 static bool has_msr_pv_eoi_en;
85 static bool has_msr_misc_enable;
86 static bool has_msr_smbase;
87 static bool has_msr_bndcfgs;
88 static bool has_msr_kvm_steal_time;
89 static int lm_capable_kernel;
90 static bool has_msr_hv_hypercall;
91 static bool has_msr_hv_vapic;
92 static bool has_msr_hv_tsc;
93 static bool has_msr_hv_crash;
94 static bool has_msr_hv_reset;
95 static bool has_msr_hv_vpindex;
96 static bool has_msr_hv_runtime;
97 static bool has_msr_hv_synic;
98 static bool has_msr_hv_stimer;
99 static bool has_msr_mtrr;
100 static bool has_msr_xss;
101
102 static bool has_msr_architectural_pmu;
103 static uint32_t num_architectural_pmu_counters;
104
105 static int has_xsave;
106 static int has_xcrs;
107 static int has_pit_state2;
108
109 int kvm_has_pit_state2(void)
110 {
111 return has_pit_state2;
112 }
113
114 bool kvm_has_smm(void)
115 {
116 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
117 }
118
119 bool kvm_allows_irq0_override(void)
120 {
121 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
122 }
123
124 static int kvm_get_tsc(CPUState *cs)
125 {
126 X86CPU *cpu = X86_CPU(cs);
127 CPUX86State *env = &cpu->env;
128 struct {
129 struct kvm_msrs info;
130 struct kvm_msr_entry entries[1];
131 } msr_data;
132 int ret;
133
134 if (env->tsc_valid) {
135 return 0;
136 }
137
138 msr_data.info.nmsrs = 1;
139 msr_data.entries[0].index = MSR_IA32_TSC;
140 env->tsc_valid = !runstate_is_running();
141
142 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
143 if (ret < 0) {
144 return ret;
145 }
146
147 assert(ret == 1);
148 env->tsc = msr_data.entries[0].data;
149 return 0;
150 }
151
152 static inline void do_kvm_synchronize_tsc(void *arg)
153 {
154 CPUState *cpu = arg;
155
156 kvm_get_tsc(cpu);
157 }
158
159 void kvm_synchronize_all_tsc(void)
160 {
161 CPUState *cpu;
162
163 if (kvm_enabled()) {
164 CPU_FOREACH(cpu) {
165 run_on_cpu(cpu, do_kvm_synchronize_tsc, cpu);
166 }
167 }
168 }
169
170 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
171 {
172 struct kvm_cpuid2 *cpuid;
173 int r, size;
174
175 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
176 cpuid = g_malloc0(size);
177 cpuid->nent = max;
178 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
179 if (r == 0 && cpuid->nent >= max) {
180 r = -E2BIG;
181 }
182 if (r < 0) {
183 if (r == -E2BIG) {
184 g_free(cpuid);
185 return NULL;
186 } else {
187 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
188 strerror(-r));
189 exit(1);
190 }
191 }
192 return cpuid;
193 }
194
195 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
196 * for all entries.
197 */
198 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
199 {
200 struct kvm_cpuid2 *cpuid;
201 int max = 1;
202 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
203 max *= 2;
204 }
205 return cpuid;
206 }
207
208 static const struct kvm_para_features {
209 int cap;
210 int feature;
211 } para_features[] = {
212 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
213 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
214 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
215 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
216 };
217
218 static int get_para_features(KVMState *s)
219 {
220 int i, features = 0;
221
222 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
223 if (kvm_check_extension(s, para_features[i].cap)) {
224 features |= (1 << para_features[i].feature);
225 }
226 }
227
228 return features;
229 }
230
231
232 /* Returns the value for a specific register on the cpuid entry
233 */
234 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
235 {
236 uint32_t ret = 0;
237 switch (reg) {
238 case R_EAX:
239 ret = entry->eax;
240 break;
241 case R_EBX:
242 ret = entry->ebx;
243 break;
244 case R_ECX:
245 ret = entry->ecx;
246 break;
247 case R_EDX:
248 ret = entry->edx;
249 break;
250 }
251 return ret;
252 }
253
254 /* Find matching entry for function/index on kvm_cpuid2 struct
255 */
256 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
257 uint32_t function,
258 uint32_t index)
259 {
260 int i;
261 for (i = 0; i < cpuid->nent; ++i) {
262 if (cpuid->entries[i].function == function &&
263 cpuid->entries[i].index == index) {
264 return &cpuid->entries[i];
265 }
266 }
267 /* not found: */
268 return NULL;
269 }
270
271 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
272 uint32_t index, int reg)
273 {
274 struct kvm_cpuid2 *cpuid;
275 uint32_t ret = 0;
276 uint32_t cpuid_1_edx;
277 bool found = false;
278
279 cpuid = get_supported_cpuid(s);
280
281 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
282 if (entry) {
283 found = true;
284 ret = cpuid_entry_get_reg(entry, reg);
285 }
286
287 /* Fixups for the data returned by KVM, below */
288
289 if (function == 1 && reg == R_EDX) {
290 /* KVM before 2.6.30 misreports the following features */
291 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
292 } else if (function == 1 && reg == R_ECX) {
293 /* We can set the hypervisor flag, even if KVM does not return it on
294 * GET_SUPPORTED_CPUID
295 */
296 ret |= CPUID_EXT_HYPERVISOR;
297 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
298 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
299 * and the irqchip is in the kernel.
300 */
301 if (kvm_irqchip_in_kernel() &&
302 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
303 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
304 }
305
306 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
307 * without the in-kernel irqchip
308 */
309 if (!kvm_irqchip_in_kernel()) {
310 ret &= ~CPUID_EXT_X2APIC;
311 }
312 } else if (function == 6 && reg == R_EAX) {
313 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
314 } else if (function == 0x80000001 && reg == R_EDX) {
315 /* On Intel, kvm returns cpuid according to the Intel spec,
316 * so add missing bits according to the AMD spec:
317 */
318 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
319 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
320 }
321
322 g_free(cpuid);
323
324 /* fallback for older kernels */
325 if ((function == KVM_CPUID_FEATURES) && !found) {
326 ret = get_para_features(s);
327 }
328
329 return ret;
330 }
331
332 typedef struct HWPoisonPage {
333 ram_addr_t ram_addr;
334 QLIST_ENTRY(HWPoisonPage) list;
335 } HWPoisonPage;
336
337 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
338 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
339
340 static void kvm_unpoison_all(void *param)
341 {
342 HWPoisonPage *page, *next_page;
343
344 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
345 QLIST_REMOVE(page, list);
346 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
347 g_free(page);
348 }
349 }
350
351 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
352 {
353 HWPoisonPage *page;
354
355 QLIST_FOREACH(page, &hwpoison_page_list, list) {
356 if (page->ram_addr == ram_addr) {
357 return;
358 }
359 }
360 page = g_new(HWPoisonPage, 1);
361 page->ram_addr = ram_addr;
362 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
363 }
364
365 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
366 int *max_banks)
367 {
368 int r;
369
370 r = kvm_check_extension(s, KVM_CAP_MCE);
371 if (r > 0) {
372 *max_banks = r;
373 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
374 }
375 return -ENOSYS;
376 }
377
378 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
379 {
380 CPUX86State *env = &cpu->env;
381 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
382 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
383 uint64_t mcg_status = MCG_STATUS_MCIP;
384
385 if (code == BUS_MCEERR_AR) {
386 status |= MCI_STATUS_AR | 0x134;
387 mcg_status |= MCG_STATUS_EIPV;
388 } else {
389 status |= 0xc0;
390 mcg_status |= MCG_STATUS_RIPV;
391 }
392 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
393 (MCM_ADDR_PHYS << 6) | 0xc,
394 cpu_x86_support_mca_broadcast(env) ?
395 MCE_INJECT_BROADCAST : 0);
396 }
397
398 static void hardware_memory_error(void)
399 {
400 fprintf(stderr, "Hardware memory error!\n");
401 exit(1);
402 }
403
404 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
405 {
406 X86CPU *cpu = X86_CPU(c);
407 CPUX86State *env = &cpu->env;
408 ram_addr_t ram_addr;
409 hwaddr paddr;
410
411 if ((env->mcg_cap & MCG_SER_P) && addr
412 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
413 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
414 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
415 fprintf(stderr, "Hardware memory error for memory used by "
416 "QEMU itself instead of guest system!\n");
417 /* Hope we are lucky for AO MCE */
418 if (code == BUS_MCEERR_AO) {
419 return 0;
420 } else {
421 hardware_memory_error();
422 }
423 }
424 kvm_hwpoison_page_add(ram_addr);
425 kvm_mce_inject(cpu, paddr, code);
426 } else {
427 if (code == BUS_MCEERR_AO) {
428 return 0;
429 } else if (code == BUS_MCEERR_AR) {
430 hardware_memory_error();
431 } else {
432 return 1;
433 }
434 }
435 return 0;
436 }
437
438 int kvm_arch_on_sigbus(int code, void *addr)
439 {
440 X86CPU *cpu = X86_CPU(first_cpu);
441
442 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
443 ram_addr_t ram_addr;
444 hwaddr paddr;
445
446 /* Hope we are lucky for AO MCE */
447 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
448 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
449 addr, &paddr)) {
450 fprintf(stderr, "Hardware memory error for memory used by "
451 "QEMU itself instead of guest system!: %p\n", addr);
452 return 0;
453 }
454 kvm_hwpoison_page_add(ram_addr);
455 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
456 } else {
457 if (code == BUS_MCEERR_AO) {
458 return 0;
459 } else if (code == BUS_MCEERR_AR) {
460 hardware_memory_error();
461 } else {
462 return 1;
463 }
464 }
465 return 0;
466 }
467
468 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
469 {
470 CPUX86State *env = &cpu->env;
471
472 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
473 unsigned int bank, bank_num = env->mcg_cap & 0xff;
474 struct kvm_x86_mce mce;
475
476 env->exception_injected = -1;
477
478 /*
479 * There must be at least one bank in use if an MCE is pending.
480 * Find it and use its values for the event injection.
481 */
482 for (bank = 0; bank < bank_num; bank++) {
483 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
484 break;
485 }
486 }
487 assert(bank < bank_num);
488
489 mce.bank = bank;
490 mce.status = env->mce_banks[bank * 4 + 1];
491 mce.mcg_status = env->mcg_status;
492 mce.addr = env->mce_banks[bank * 4 + 2];
493 mce.misc = env->mce_banks[bank * 4 + 3];
494
495 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
496 }
497 return 0;
498 }
499
500 static void cpu_update_state(void *opaque, int running, RunState state)
501 {
502 CPUX86State *env = opaque;
503
504 if (running) {
505 env->tsc_valid = false;
506 }
507 }
508
509 unsigned long kvm_arch_vcpu_id(CPUState *cs)
510 {
511 X86CPU *cpu = X86_CPU(cs);
512 return cpu->apic_id;
513 }
514
515 #ifndef KVM_CPUID_SIGNATURE_NEXT
516 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
517 #endif
518
519 static bool hyperv_hypercall_available(X86CPU *cpu)
520 {
521 return cpu->hyperv_vapic ||
522 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
523 }
524
525 static bool hyperv_enabled(X86CPU *cpu)
526 {
527 CPUState *cs = CPU(cpu);
528 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
529 (hyperv_hypercall_available(cpu) ||
530 cpu->hyperv_time ||
531 cpu->hyperv_relaxed_timing ||
532 cpu->hyperv_crash ||
533 cpu->hyperv_reset ||
534 cpu->hyperv_vpindex ||
535 cpu->hyperv_runtime ||
536 cpu->hyperv_synic ||
537 cpu->hyperv_stimer);
538 }
539
540 static int kvm_arch_set_tsc_khz(CPUState *cs)
541 {
542 X86CPU *cpu = X86_CPU(cs);
543 CPUX86State *env = &cpu->env;
544 int r;
545
546 if (!env->tsc_khz) {
547 return 0;
548 }
549
550 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
551 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
552 -ENOTSUP;
553 if (r < 0) {
554 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
555 * TSC frequency doesn't match the one we want.
556 */
557 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
558 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
559 -ENOTSUP;
560 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
561 error_report("warning: TSC frequency mismatch between "
562 "VM and host, and TSC scaling unavailable");
563 return r;
564 }
565 }
566
567 return 0;
568 }
569
570 static Error *invtsc_mig_blocker;
571
572 #define KVM_MAX_CPUID_ENTRIES 100
573
574 int kvm_arch_init_vcpu(CPUState *cs)
575 {
576 struct {
577 struct kvm_cpuid2 cpuid;
578 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
579 } QEMU_PACKED cpuid_data;
580 X86CPU *cpu = X86_CPU(cs);
581 CPUX86State *env = &cpu->env;
582 uint32_t limit, i, j, cpuid_i;
583 uint32_t unused;
584 struct kvm_cpuid_entry2 *c;
585 uint32_t signature[3];
586 int kvm_base = KVM_CPUID_SIGNATURE;
587 int r;
588
589 memset(&cpuid_data, 0, sizeof(cpuid_data));
590
591 cpuid_i = 0;
592
593 /* Paravirtualization CPUIDs */
594 if (hyperv_enabled(cpu)) {
595 c = &cpuid_data.entries[cpuid_i++];
596 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
597 if (!cpu->hyperv_vendor_id) {
598 memcpy(signature, "Microsoft Hv", 12);
599 } else {
600 size_t len = strlen(cpu->hyperv_vendor_id);
601
602 if (len > 12) {
603 error_report("hv-vendor-id truncated to 12 characters");
604 len = 12;
605 }
606 memset(signature, 0, 12);
607 memcpy(signature, cpu->hyperv_vendor_id, len);
608 }
609 c->eax = HYPERV_CPUID_MIN;
610 c->ebx = signature[0];
611 c->ecx = signature[1];
612 c->edx = signature[2];
613
614 c = &cpuid_data.entries[cpuid_i++];
615 c->function = HYPERV_CPUID_INTERFACE;
616 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
617 c->eax = signature[0];
618 c->ebx = 0;
619 c->ecx = 0;
620 c->edx = 0;
621
622 c = &cpuid_data.entries[cpuid_i++];
623 c->function = HYPERV_CPUID_VERSION;
624 c->eax = 0x00001bbc;
625 c->ebx = 0x00060001;
626
627 c = &cpuid_data.entries[cpuid_i++];
628 c->function = HYPERV_CPUID_FEATURES;
629 if (cpu->hyperv_relaxed_timing) {
630 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
631 }
632 if (cpu->hyperv_vapic) {
633 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
634 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
635 has_msr_hv_vapic = true;
636 }
637 if (cpu->hyperv_time &&
638 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
639 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
640 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
641 c->eax |= 0x200;
642 has_msr_hv_tsc = true;
643 }
644 if (cpu->hyperv_crash && has_msr_hv_crash) {
645 c->edx |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
646 }
647 c->edx |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
648 if (cpu->hyperv_reset && has_msr_hv_reset) {
649 c->eax |= HV_X64_MSR_RESET_AVAILABLE;
650 }
651 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
652 c->eax |= HV_X64_MSR_VP_INDEX_AVAILABLE;
653 }
654 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
655 c->eax |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
656 }
657 if (cpu->hyperv_synic) {
658 int sint;
659
660 if (!has_msr_hv_synic ||
661 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
662 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
663 return -ENOSYS;
664 }
665
666 c->eax |= HV_X64_MSR_SYNIC_AVAILABLE;
667 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
668 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
669 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
670 }
671 }
672 if (cpu->hyperv_stimer) {
673 if (!has_msr_hv_stimer) {
674 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
675 return -ENOSYS;
676 }
677 c->eax |= HV_X64_MSR_SYNTIMER_AVAILABLE;
678 }
679 c = &cpuid_data.entries[cpuid_i++];
680 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
681 if (cpu->hyperv_relaxed_timing) {
682 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
683 }
684 if (has_msr_hv_vapic) {
685 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
686 }
687 c->ebx = cpu->hyperv_spinlock_attempts;
688
689 c = &cpuid_data.entries[cpuid_i++];
690 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
691 c->eax = 0x40;
692 c->ebx = 0x40;
693
694 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
695 has_msr_hv_hypercall = true;
696 }
697
698 if (cpu->expose_kvm) {
699 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
700 c = &cpuid_data.entries[cpuid_i++];
701 c->function = KVM_CPUID_SIGNATURE | kvm_base;
702 c->eax = KVM_CPUID_FEATURES | kvm_base;
703 c->ebx = signature[0];
704 c->ecx = signature[1];
705 c->edx = signature[2];
706
707 c = &cpuid_data.entries[cpuid_i++];
708 c->function = KVM_CPUID_FEATURES | kvm_base;
709 c->eax = env->features[FEAT_KVM];
710
711 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
712
713 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
714
715 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
716 }
717
718 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
719
720 for (i = 0; i <= limit; i++) {
721 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
722 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
723 abort();
724 }
725 c = &cpuid_data.entries[cpuid_i++];
726
727 switch (i) {
728 case 2: {
729 /* Keep reading function 2 till all the input is received */
730 int times;
731
732 c->function = i;
733 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
734 KVM_CPUID_FLAG_STATE_READ_NEXT;
735 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
736 times = c->eax & 0xff;
737
738 for (j = 1; j < times; ++j) {
739 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
740 fprintf(stderr, "cpuid_data is full, no space for "
741 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
742 abort();
743 }
744 c = &cpuid_data.entries[cpuid_i++];
745 c->function = i;
746 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
747 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
748 }
749 break;
750 }
751 case 4:
752 case 0xb:
753 case 0xd:
754 for (j = 0; ; j++) {
755 if (i == 0xd && j == 64) {
756 break;
757 }
758 c->function = i;
759 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
760 c->index = j;
761 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
762
763 if (i == 4 && c->eax == 0) {
764 break;
765 }
766 if (i == 0xb && !(c->ecx & 0xff00)) {
767 break;
768 }
769 if (i == 0xd && c->eax == 0) {
770 continue;
771 }
772 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
773 fprintf(stderr, "cpuid_data is full, no space for "
774 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
775 abort();
776 }
777 c = &cpuid_data.entries[cpuid_i++];
778 }
779 break;
780 default:
781 c->function = i;
782 c->flags = 0;
783 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
784 break;
785 }
786 }
787
788 if (limit >= 0x0a) {
789 uint32_t ver;
790
791 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
792 if ((ver & 0xff) > 0) {
793 has_msr_architectural_pmu = true;
794 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
795
796 /* Shouldn't be more than 32, since that's the number of bits
797 * available in EBX to tell us _which_ counters are available.
798 * Play it safe.
799 */
800 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
801 num_architectural_pmu_counters = MAX_GP_COUNTERS;
802 }
803 }
804 }
805
806 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
807
808 for (i = 0x80000000; i <= limit; i++) {
809 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
810 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
811 abort();
812 }
813 c = &cpuid_data.entries[cpuid_i++];
814
815 c->function = i;
816 c->flags = 0;
817 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
818 }
819
820 /* Call Centaur's CPUID instructions they are supported. */
821 if (env->cpuid_xlevel2 > 0) {
822 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
823
824 for (i = 0xC0000000; i <= limit; i++) {
825 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
826 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
827 abort();
828 }
829 c = &cpuid_data.entries[cpuid_i++];
830
831 c->function = i;
832 c->flags = 0;
833 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
834 }
835 }
836
837 cpuid_data.cpuid.nent = cpuid_i;
838
839 if (((env->cpuid_version >> 8)&0xF) >= 6
840 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
841 (CPUID_MCE | CPUID_MCA)
842 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
843 uint64_t mcg_cap, unsupported_caps;
844 int banks;
845 int ret;
846
847 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
848 if (ret < 0) {
849 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
850 return ret;
851 }
852
853 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
854 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
855 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
856 return -ENOTSUP;
857 }
858
859 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
860 if (unsupported_caps) {
861 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
862 unsupported_caps);
863 }
864
865 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
866 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
867 if (ret < 0) {
868 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
869 return ret;
870 }
871 }
872
873 qemu_add_vm_change_state_handler(cpu_update_state, env);
874
875 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
876 if (c) {
877 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
878 !!(c->ecx & CPUID_EXT_SMX);
879 }
880
881 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
882 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
883 /* for migration */
884 error_setg(&invtsc_mig_blocker,
885 "State blocked by non-migratable CPU device"
886 " (invtsc flag)");
887 migrate_add_blocker(invtsc_mig_blocker);
888 /* for savevm */
889 vmstate_x86_cpu.unmigratable = 1;
890 }
891
892 cpuid_data.cpuid.padding = 0;
893 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
894 if (r) {
895 return r;
896 }
897
898 r = kvm_arch_set_tsc_khz(cs);
899 if (r < 0) {
900 return r;
901 }
902
903 /* vcpu's TSC frequency is either specified by user, or following
904 * the value used by KVM if the former is not present. In the
905 * latter case, we query it from KVM and record in env->tsc_khz,
906 * so that vcpu's TSC frequency can be migrated later via this field.
907 */
908 if (!env->tsc_khz) {
909 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
910 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
911 -ENOTSUP;
912 if (r > 0) {
913 env->tsc_khz = r;
914 }
915 }
916
917 if (has_xsave) {
918 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
919 }
920 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
921
922 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
923 has_msr_mtrr = true;
924 }
925 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
926 has_msr_tsc_aux = false;
927 }
928
929 return 0;
930 }
931
932 void kvm_arch_reset_vcpu(X86CPU *cpu)
933 {
934 CPUX86State *env = &cpu->env;
935
936 env->exception_injected = -1;
937 env->interrupt_injected = -1;
938 env->xcr0 = 1;
939 if (kvm_irqchip_in_kernel()) {
940 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
941 KVM_MP_STATE_UNINITIALIZED;
942 } else {
943 env->mp_state = KVM_MP_STATE_RUNNABLE;
944 }
945 }
946
947 void kvm_arch_do_init_vcpu(X86CPU *cpu)
948 {
949 CPUX86State *env = &cpu->env;
950
951 /* APs get directly into wait-for-SIPI state. */
952 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
953 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
954 }
955 }
956
957 static int kvm_get_supported_msrs(KVMState *s)
958 {
959 static int kvm_supported_msrs;
960 int ret = 0;
961
962 /* first time */
963 if (kvm_supported_msrs == 0) {
964 struct kvm_msr_list msr_list, *kvm_msr_list;
965
966 kvm_supported_msrs = -1;
967
968 /* Obtain MSR list from KVM. These are the MSRs that we must
969 * save/restore */
970 msr_list.nmsrs = 0;
971 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
972 if (ret < 0 && ret != -E2BIG) {
973 return ret;
974 }
975 /* Old kernel modules had a bug and could write beyond the provided
976 memory. Allocate at least a safe amount of 1K. */
977 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
978 msr_list.nmsrs *
979 sizeof(msr_list.indices[0])));
980
981 kvm_msr_list->nmsrs = msr_list.nmsrs;
982 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
983 if (ret >= 0) {
984 int i;
985
986 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
987 if (kvm_msr_list->indices[i] == MSR_STAR) {
988 has_msr_star = true;
989 continue;
990 }
991 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
992 has_msr_hsave_pa = true;
993 continue;
994 }
995 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
996 has_msr_tsc_aux = true;
997 continue;
998 }
999 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
1000 has_msr_tsc_adjust = true;
1001 continue;
1002 }
1003 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1004 has_msr_tsc_deadline = true;
1005 continue;
1006 }
1007 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1008 has_msr_smbase = true;
1009 continue;
1010 }
1011 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1012 has_msr_misc_enable = true;
1013 continue;
1014 }
1015 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1016 has_msr_bndcfgs = true;
1017 continue;
1018 }
1019 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1020 has_msr_xss = true;
1021 continue;
1022 }
1023 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1024 has_msr_hv_crash = true;
1025 continue;
1026 }
1027 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1028 has_msr_hv_reset = true;
1029 continue;
1030 }
1031 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1032 has_msr_hv_vpindex = true;
1033 continue;
1034 }
1035 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1036 has_msr_hv_runtime = true;
1037 continue;
1038 }
1039 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1040 has_msr_hv_synic = true;
1041 continue;
1042 }
1043 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1044 has_msr_hv_stimer = true;
1045 continue;
1046 }
1047 }
1048 }
1049
1050 g_free(kvm_msr_list);
1051 }
1052
1053 return ret;
1054 }
1055
1056 static Notifier smram_machine_done;
1057 static KVMMemoryListener smram_listener;
1058 static AddressSpace smram_address_space;
1059 static MemoryRegion smram_as_root;
1060 static MemoryRegion smram_as_mem;
1061
1062 static void register_smram_listener(Notifier *n, void *unused)
1063 {
1064 MemoryRegion *smram =
1065 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1066
1067 /* Outer container... */
1068 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1069 memory_region_set_enabled(&smram_as_root, true);
1070
1071 /* ... with two regions inside: normal system memory with low
1072 * priority, and...
1073 */
1074 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1075 get_system_memory(), 0, ~0ull);
1076 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1077 memory_region_set_enabled(&smram_as_mem, true);
1078
1079 if (smram) {
1080 /* ... SMRAM with higher priority */
1081 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1082 memory_region_set_enabled(smram, true);
1083 }
1084
1085 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1086 kvm_memory_listener_register(kvm_state, &smram_listener,
1087 &smram_address_space, 1);
1088 }
1089
1090 int kvm_arch_init(MachineState *ms, KVMState *s)
1091 {
1092 uint64_t identity_base = 0xfffbc000;
1093 uint64_t shadow_mem;
1094 int ret;
1095 struct utsname utsname;
1096
1097 #ifdef KVM_CAP_XSAVE
1098 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1099 #endif
1100
1101 #ifdef KVM_CAP_XCRS
1102 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1103 #endif
1104
1105 #ifdef KVM_CAP_PIT_STATE2
1106 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1107 #endif
1108
1109 ret = kvm_get_supported_msrs(s);
1110 if (ret < 0) {
1111 return ret;
1112 }
1113
1114 uname(&utsname);
1115 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1116
1117 /*
1118 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1119 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1120 * Since these must be part of guest physical memory, we need to allocate
1121 * them, both by setting their start addresses in the kernel and by
1122 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1123 *
1124 * Older KVM versions may not support setting the identity map base. In
1125 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1126 * size.
1127 */
1128 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1129 /* Allows up to 16M BIOSes. */
1130 identity_base = 0xfeffc000;
1131
1132 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1133 if (ret < 0) {
1134 return ret;
1135 }
1136 }
1137
1138 /* Set TSS base one page after EPT identity map. */
1139 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1140 if (ret < 0) {
1141 return ret;
1142 }
1143
1144 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1145 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1146 if (ret < 0) {
1147 fprintf(stderr, "e820_add_entry() table is full\n");
1148 return ret;
1149 }
1150 qemu_register_reset(kvm_unpoison_all, NULL);
1151
1152 shadow_mem = machine_kvm_shadow_mem(ms);
1153 if (shadow_mem != -1) {
1154 shadow_mem /= 4096;
1155 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1156 if (ret < 0) {
1157 return ret;
1158 }
1159 }
1160
1161 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1162 smram_machine_done.notify = register_smram_listener;
1163 qemu_add_machine_init_done_notifier(&smram_machine_done);
1164 }
1165 return 0;
1166 }
1167
1168 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1169 {
1170 lhs->selector = rhs->selector;
1171 lhs->base = rhs->base;
1172 lhs->limit = rhs->limit;
1173 lhs->type = 3;
1174 lhs->present = 1;
1175 lhs->dpl = 3;
1176 lhs->db = 0;
1177 lhs->s = 1;
1178 lhs->l = 0;
1179 lhs->g = 0;
1180 lhs->avl = 0;
1181 lhs->unusable = 0;
1182 }
1183
1184 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1185 {
1186 unsigned flags = rhs->flags;
1187 lhs->selector = rhs->selector;
1188 lhs->base = rhs->base;
1189 lhs->limit = rhs->limit;
1190 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1191 lhs->present = (flags & DESC_P_MASK) != 0;
1192 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1193 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1194 lhs->s = (flags & DESC_S_MASK) != 0;
1195 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1196 lhs->g = (flags & DESC_G_MASK) != 0;
1197 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1198 lhs->unusable = !lhs->present;
1199 lhs->padding = 0;
1200 }
1201
1202 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1203 {
1204 lhs->selector = rhs->selector;
1205 lhs->base = rhs->base;
1206 lhs->limit = rhs->limit;
1207 if (rhs->unusable) {
1208 lhs->flags = 0;
1209 } else {
1210 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1211 (rhs->present * DESC_P_MASK) |
1212 (rhs->dpl << DESC_DPL_SHIFT) |
1213 (rhs->db << DESC_B_SHIFT) |
1214 (rhs->s * DESC_S_MASK) |
1215 (rhs->l << DESC_L_SHIFT) |
1216 (rhs->g * DESC_G_MASK) |
1217 (rhs->avl * DESC_AVL_MASK);
1218 }
1219 }
1220
1221 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1222 {
1223 if (set) {
1224 *kvm_reg = *qemu_reg;
1225 } else {
1226 *qemu_reg = *kvm_reg;
1227 }
1228 }
1229
1230 static int kvm_getput_regs(X86CPU *cpu, int set)
1231 {
1232 CPUX86State *env = &cpu->env;
1233 struct kvm_regs regs;
1234 int ret = 0;
1235
1236 if (!set) {
1237 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1238 if (ret < 0) {
1239 return ret;
1240 }
1241 }
1242
1243 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1244 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1245 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1246 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1247 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1248 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1249 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1250 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1251 #ifdef TARGET_X86_64
1252 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1253 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1254 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1255 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1256 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1257 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1258 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1259 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1260 #endif
1261
1262 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1263 kvm_getput_reg(&regs.rip, &env->eip, set);
1264
1265 if (set) {
1266 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1267 }
1268
1269 return ret;
1270 }
1271
1272 static int kvm_put_fpu(X86CPU *cpu)
1273 {
1274 CPUX86State *env = &cpu->env;
1275 struct kvm_fpu fpu;
1276 int i;
1277
1278 memset(&fpu, 0, sizeof fpu);
1279 fpu.fsw = env->fpus & ~(7 << 11);
1280 fpu.fsw |= (env->fpstt & 7) << 11;
1281 fpu.fcw = env->fpuc;
1282 fpu.last_opcode = env->fpop;
1283 fpu.last_ip = env->fpip;
1284 fpu.last_dp = env->fpdp;
1285 for (i = 0; i < 8; ++i) {
1286 fpu.ftwx |= (!env->fptags[i]) << i;
1287 }
1288 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1289 for (i = 0; i < CPU_NB_REGS; i++) {
1290 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1291 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1292 }
1293 fpu.mxcsr = env->mxcsr;
1294
1295 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1296 }
1297
1298 #define XSAVE_FCW_FSW 0
1299 #define XSAVE_FTW_FOP 1
1300 #define XSAVE_CWD_RIP 2
1301 #define XSAVE_CWD_RDP 4
1302 #define XSAVE_MXCSR 6
1303 #define XSAVE_ST_SPACE 8
1304 #define XSAVE_XMM_SPACE 40
1305 #define XSAVE_XSTATE_BV 128
1306 #define XSAVE_YMMH_SPACE 144
1307 #define XSAVE_BNDREGS 240
1308 #define XSAVE_BNDCSR 256
1309 #define XSAVE_OPMASK 272
1310 #define XSAVE_ZMM_Hi256 288
1311 #define XSAVE_Hi16_ZMM 416
1312 #define XSAVE_PKRU 672
1313
1314 #define XSAVE_BYTE_OFFSET(word_offset) \
1315 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1316
1317 #define ASSERT_OFFSET(word_offset, field) \
1318 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1319 offsetof(X86XSaveArea, field))
1320
1321 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1322 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1323 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1324 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1325 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1326 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1327 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1328 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1329 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1330 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1331 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1332 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1333 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1334 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1335 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1336
1337 static int kvm_put_xsave(X86CPU *cpu)
1338 {
1339 CPUX86State *env = &cpu->env;
1340 X86XSaveArea *xsave = env->kvm_xsave_buf;
1341 uint16_t cwd, swd, twd;
1342 int i, r;
1343
1344 if (!has_xsave) {
1345 return kvm_put_fpu(cpu);
1346 }
1347
1348 memset(xsave, 0, sizeof(struct kvm_xsave));
1349 twd = 0;
1350 swd = env->fpus & ~(7 << 11);
1351 swd |= (env->fpstt & 7) << 11;
1352 cwd = env->fpuc;
1353 for (i = 0; i < 8; ++i) {
1354 twd |= (!env->fptags[i]) << i;
1355 }
1356 xsave->legacy.fcw = cwd;
1357 xsave->legacy.fsw = swd;
1358 xsave->legacy.ftw = twd;
1359 xsave->legacy.fpop = env->fpop;
1360 xsave->legacy.fpip = env->fpip;
1361 xsave->legacy.fpdp = env->fpdp;
1362 memcpy(&xsave->legacy.fpregs, env->fpregs,
1363 sizeof env->fpregs);
1364 xsave->legacy.mxcsr = env->mxcsr;
1365 xsave->header.xstate_bv = env->xstate_bv;
1366 memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs,
1367 sizeof env->bnd_regs);
1368 xsave->bndcsr_state.bndcsr = env->bndcs_regs;
1369 memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs,
1370 sizeof env->opmask_regs);
1371
1372 for (i = 0; i < CPU_NB_REGS; i++) {
1373 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1374 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1375 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1376 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1377 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1378 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1379 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1380 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1381 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1382 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1383 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
1384 }
1385
1386 #ifdef TARGET_X86_64
1387 memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16],
1388 16 * sizeof env->xmm_regs[16]);
1389 memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru);
1390 #endif
1391 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1392 return r;
1393 }
1394
1395 static int kvm_put_xcrs(X86CPU *cpu)
1396 {
1397 CPUX86State *env = &cpu->env;
1398 struct kvm_xcrs xcrs = {};
1399
1400 if (!has_xcrs) {
1401 return 0;
1402 }
1403
1404 xcrs.nr_xcrs = 1;
1405 xcrs.flags = 0;
1406 xcrs.xcrs[0].xcr = 0;
1407 xcrs.xcrs[0].value = env->xcr0;
1408 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1409 }
1410
1411 static int kvm_put_sregs(X86CPU *cpu)
1412 {
1413 CPUX86State *env = &cpu->env;
1414 struct kvm_sregs sregs;
1415
1416 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1417 if (env->interrupt_injected >= 0) {
1418 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1419 (uint64_t)1 << (env->interrupt_injected % 64);
1420 }
1421
1422 if ((env->eflags & VM_MASK)) {
1423 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1424 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1425 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1426 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1427 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1428 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1429 } else {
1430 set_seg(&sregs.cs, &env->segs[R_CS]);
1431 set_seg(&sregs.ds, &env->segs[R_DS]);
1432 set_seg(&sregs.es, &env->segs[R_ES]);
1433 set_seg(&sregs.fs, &env->segs[R_FS]);
1434 set_seg(&sregs.gs, &env->segs[R_GS]);
1435 set_seg(&sregs.ss, &env->segs[R_SS]);
1436 }
1437
1438 set_seg(&sregs.tr, &env->tr);
1439 set_seg(&sregs.ldt, &env->ldt);
1440
1441 sregs.idt.limit = env->idt.limit;
1442 sregs.idt.base = env->idt.base;
1443 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1444 sregs.gdt.limit = env->gdt.limit;
1445 sregs.gdt.base = env->gdt.base;
1446 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1447
1448 sregs.cr0 = env->cr[0];
1449 sregs.cr2 = env->cr[2];
1450 sregs.cr3 = env->cr[3];
1451 sregs.cr4 = env->cr[4];
1452
1453 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1454 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1455
1456 sregs.efer = env->efer;
1457
1458 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1459 }
1460
1461 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1462 uint32_t index, uint64_t value)
1463 {
1464 entry->index = index;
1465 entry->reserved = 0;
1466 entry->data = value;
1467 }
1468
1469 static void kvm_msr_buf_reset(X86CPU *cpu)
1470 {
1471 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1472 }
1473
1474 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1475 {
1476 CPUX86State *env = &cpu->env;
1477 struct {
1478 struct kvm_msrs info;
1479 struct kvm_msr_entry entries[1];
1480 } msr_data;
1481 struct kvm_msr_entry *msrs = msr_data.entries;
1482 int ret;
1483
1484 if (!has_msr_tsc_deadline) {
1485 return 0;
1486 }
1487
1488 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1489
1490 msr_data.info = (struct kvm_msrs) {
1491 .nmsrs = 1,
1492 };
1493
1494 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1495 if (ret < 0) {
1496 return ret;
1497 }
1498
1499 assert(ret == 1);
1500 return 0;
1501 }
1502
1503 /*
1504 * Provide a separate write service for the feature control MSR in order to
1505 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1506 * before writing any other state because forcibly leaving nested mode
1507 * invalidates the VCPU state.
1508 */
1509 static int kvm_put_msr_feature_control(X86CPU *cpu)
1510 {
1511 struct {
1512 struct kvm_msrs info;
1513 struct kvm_msr_entry entry;
1514 } msr_data;
1515 int ret;
1516
1517 if (!has_msr_feature_control) {
1518 return 0;
1519 }
1520
1521 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1522 cpu->env.msr_ia32_feature_control);
1523
1524 msr_data.info = (struct kvm_msrs) {
1525 .nmsrs = 1,
1526 };
1527
1528 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1529 if (ret < 0) {
1530 return ret;
1531 }
1532
1533 assert(ret == 1);
1534 return 0;
1535 }
1536
1537 static int kvm_put_msrs(X86CPU *cpu, int level)
1538 {
1539 CPUX86State *env = &cpu->env;
1540 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
1541 int n = 0, i;
1542 int ret;
1543
1544 kvm_msr_buf_reset(cpu);
1545
1546 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1547 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1548 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1549 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1550 if (has_msr_star) {
1551 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1552 }
1553 if (has_msr_hsave_pa) {
1554 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1555 }
1556 if (has_msr_tsc_aux) {
1557 kvm_msr_entry_set(&msrs[n++], MSR_TSC_AUX, env->tsc_aux);
1558 }
1559 if (has_msr_tsc_adjust) {
1560 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1561 }
1562 if (has_msr_misc_enable) {
1563 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1564 env->msr_ia32_misc_enable);
1565 }
1566 if (has_msr_smbase) {
1567 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SMBASE, env->smbase);
1568 }
1569 if (has_msr_bndcfgs) {
1570 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1571 }
1572 if (has_msr_xss) {
1573 kvm_msr_entry_set(&msrs[n++], MSR_IA32_XSS, env->xss);
1574 }
1575 #ifdef TARGET_X86_64
1576 if (lm_capable_kernel) {
1577 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1578 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1579 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1580 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1581 }
1582 #endif
1583 /*
1584 * The following MSRs have side effects on the guest or are too heavy
1585 * for normal writeback. Limit them to reset or full state updates.
1586 */
1587 if (level >= KVM_PUT_RESET_STATE) {
1588 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1589 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1590 env->system_time_msr);
1591 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1592 if (has_msr_async_pf_en) {
1593 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1594 env->async_pf_en_msr);
1595 }
1596 if (has_msr_pv_eoi_en) {
1597 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1598 env->pv_eoi_en_msr);
1599 }
1600 if (has_msr_kvm_steal_time) {
1601 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1602 env->steal_time_msr);
1603 }
1604 if (has_msr_architectural_pmu) {
1605 /* Stop the counter. */
1606 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1607 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1608
1609 /* Set the counter values. */
1610 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1611 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1612 env->msr_fixed_counters[i]);
1613 }
1614 for (i = 0; i < num_architectural_pmu_counters; i++) {
1615 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1616 env->msr_gp_counters[i]);
1617 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1618 env->msr_gp_evtsel[i]);
1619 }
1620 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1621 env->msr_global_status);
1622 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1623 env->msr_global_ovf_ctrl);
1624
1625 /* Now start the PMU. */
1626 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1627 env->msr_fixed_ctr_ctrl);
1628 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1629 env->msr_global_ctrl);
1630 }
1631 if (has_msr_hv_hypercall) {
1632 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1633 env->msr_hv_guest_os_id);
1634 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1635 env->msr_hv_hypercall);
1636 }
1637 if (has_msr_hv_vapic) {
1638 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1639 env->msr_hv_vapic);
1640 }
1641 if (has_msr_hv_tsc) {
1642 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
1643 env->msr_hv_tsc);
1644 }
1645 if (has_msr_hv_crash) {
1646 int j;
1647
1648 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1649 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_P0 + j,
1650 env->msr_hv_crash_params[j]);
1651
1652 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_CRASH_CTL,
1653 HV_X64_MSR_CRASH_CTL_NOTIFY);
1654 }
1655 if (has_msr_hv_runtime) {
1656 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_VP_RUNTIME,
1657 env->msr_hv_runtime);
1658 }
1659 if (cpu->hyperv_synic) {
1660 int j;
1661
1662 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SCONTROL,
1663 env->msr_hv_synic_control);
1664 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SVERSION,
1665 env->msr_hv_synic_version);
1666 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SIEFP,
1667 env->msr_hv_synic_evt_page);
1668 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SIMP,
1669 env->msr_hv_synic_msg_page);
1670
1671 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1672 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SINT0 + j,
1673 env->msr_hv_synic_sint[j]);
1674 }
1675 }
1676 if (has_msr_hv_stimer) {
1677 int j;
1678
1679 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1680 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_STIMER0_CONFIG + j*2,
1681 env->msr_hv_stimer_config[j]);
1682 }
1683
1684 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1685 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_STIMER0_COUNT + j*2,
1686 env->msr_hv_stimer_count[j]);
1687 }
1688 }
1689 if (has_msr_mtrr) {
1690 kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_deftype);
1691 kvm_msr_entry_set(&msrs[n++],
1692 MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1693 kvm_msr_entry_set(&msrs[n++],
1694 MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1695 kvm_msr_entry_set(&msrs[n++],
1696 MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1697 kvm_msr_entry_set(&msrs[n++],
1698 MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1699 kvm_msr_entry_set(&msrs[n++],
1700 MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1701 kvm_msr_entry_set(&msrs[n++],
1702 MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1703 kvm_msr_entry_set(&msrs[n++],
1704 MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1705 kvm_msr_entry_set(&msrs[n++],
1706 MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1707 kvm_msr_entry_set(&msrs[n++],
1708 MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1709 kvm_msr_entry_set(&msrs[n++],
1710 MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1711 kvm_msr_entry_set(&msrs[n++],
1712 MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1713 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1714 kvm_msr_entry_set(&msrs[n++],
1715 MSR_MTRRphysBase(i), env->mtrr_var[i].base);
1716 kvm_msr_entry_set(&msrs[n++],
1717 MSR_MTRRphysMask(i), env->mtrr_var[i].mask);
1718 }
1719 }
1720
1721 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1722 * kvm_put_msr_feature_control. */
1723 }
1724 if (env->mcg_cap) {
1725 int i;
1726
1727 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1728 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1729 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1730 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1731 }
1732 }
1733
1734 cpu->kvm_msr_buf->nmsrs = n;
1735
1736 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1737 if (ret < 0) {
1738 return ret;
1739 }
1740
1741 assert(ret == n);
1742 return 0;
1743 }
1744
1745
1746 static int kvm_get_fpu(X86CPU *cpu)
1747 {
1748 CPUX86State *env = &cpu->env;
1749 struct kvm_fpu fpu;
1750 int i, ret;
1751
1752 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1753 if (ret < 0) {
1754 return ret;
1755 }
1756
1757 env->fpstt = (fpu.fsw >> 11) & 7;
1758 env->fpus = fpu.fsw;
1759 env->fpuc = fpu.fcw;
1760 env->fpop = fpu.last_opcode;
1761 env->fpip = fpu.last_ip;
1762 env->fpdp = fpu.last_dp;
1763 for (i = 0; i < 8; ++i) {
1764 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1765 }
1766 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1767 for (i = 0; i < CPU_NB_REGS; i++) {
1768 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1769 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1770 }
1771 env->mxcsr = fpu.mxcsr;
1772
1773 return 0;
1774 }
1775
1776 static int kvm_get_xsave(X86CPU *cpu)
1777 {
1778 CPUX86State *env = &cpu->env;
1779 X86XSaveArea *xsave = env->kvm_xsave_buf;
1780 int ret, i;
1781 uint16_t cwd, swd, twd;
1782
1783 if (!has_xsave) {
1784 return kvm_get_fpu(cpu);
1785 }
1786
1787 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1788 if (ret < 0) {
1789 return ret;
1790 }
1791
1792 cwd = xsave->legacy.fcw;
1793 swd = xsave->legacy.fsw;
1794 twd = xsave->legacy.ftw;
1795 env->fpop = xsave->legacy.fpop;
1796 env->fpstt = (swd >> 11) & 7;
1797 env->fpus = swd;
1798 env->fpuc = cwd;
1799 for (i = 0; i < 8; ++i) {
1800 env->fptags[i] = !((twd >> i) & 1);
1801 }
1802 env->fpip = xsave->legacy.fpip;
1803 env->fpdp = xsave->legacy.fpdp;
1804 env->mxcsr = xsave->legacy.mxcsr;
1805 memcpy(env->fpregs, &xsave->legacy.fpregs,
1806 sizeof env->fpregs);
1807 env->xstate_bv = xsave->header.xstate_bv;
1808 memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs,
1809 sizeof env->bnd_regs);
1810 env->bndcs_regs = xsave->bndcsr_state.bndcsr;
1811 memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs,
1812 sizeof env->opmask_regs);
1813
1814 for (i = 0; i < CPU_NB_REGS; i++) {
1815 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1816 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1817 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1818 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1819 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1820 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1821 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1822 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1823 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1824 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1825 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
1826 }
1827
1828 #ifdef TARGET_X86_64
1829 memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm,
1830 16 * sizeof env->xmm_regs[16]);
1831 memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru);
1832 #endif
1833 return 0;
1834 }
1835
1836 static int kvm_get_xcrs(X86CPU *cpu)
1837 {
1838 CPUX86State *env = &cpu->env;
1839 int i, ret;
1840 struct kvm_xcrs xcrs;
1841
1842 if (!has_xcrs) {
1843 return 0;
1844 }
1845
1846 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1847 if (ret < 0) {
1848 return ret;
1849 }
1850
1851 for (i = 0; i < xcrs.nr_xcrs; i++) {
1852 /* Only support xcr0 now */
1853 if (xcrs.xcrs[i].xcr == 0) {
1854 env->xcr0 = xcrs.xcrs[i].value;
1855 break;
1856 }
1857 }
1858 return 0;
1859 }
1860
1861 static int kvm_get_sregs(X86CPU *cpu)
1862 {
1863 CPUX86State *env = &cpu->env;
1864 struct kvm_sregs sregs;
1865 uint32_t hflags;
1866 int bit, i, ret;
1867
1868 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1869 if (ret < 0) {
1870 return ret;
1871 }
1872
1873 /* There can only be one pending IRQ set in the bitmap at a time, so try
1874 to find it and save its number instead (-1 for none). */
1875 env->interrupt_injected = -1;
1876 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1877 if (sregs.interrupt_bitmap[i]) {
1878 bit = ctz64(sregs.interrupt_bitmap[i]);
1879 env->interrupt_injected = i * 64 + bit;
1880 break;
1881 }
1882 }
1883
1884 get_seg(&env->segs[R_CS], &sregs.cs);
1885 get_seg(&env->segs[R_DS], &sregs.ds);
1886 get_seg(&env->segs[R_ES], &sregs.es);
1887 get_seg(&env->segs[R_FS], &sregs.fs);
1888 get_seg(&env->segs[R_GS], &sregs.gs);
1889 get_seg(&env->segs[R_SS], &sregs.ss);
1890
1891 get_seg(&env->tr, &sregs.tr);
1892 get_seg(&env->ldt, &sregs.ldt);
1893
1894 env->idt.limit = sregs.idt.limit;
1895 env->idt.base = sregs.idt.base;
1896 env->gdt.limit = sregs.gdt.limit;
1897 env->gdt.base = sregs.gdt.base;
1898
1899 env->cr[0] = sregs.cr0;
1900 env->cr[2] = sregs.cr2;
1901 env->cr[3] = sregs.cr3;
1902 env->cr[4] = sregs.cr4;
1903
1904 env->efer = sregs.efer;
1905
1906 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1907
1908 #define HFLAG_COPY_MASK \
1909 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1910 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1911 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1912 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1913
1914 hflags = env->hflags & HFLAG_COPY_MASK;
1915 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1916 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1917 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1918 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1919 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1920
1921 if (env->cr[4] & CR4_OSFXSR_MASK) {
1922 hflags |= HF_OSFXSR_MASK;
1923 }
1924
1925 if (env->efer & MSR_EFER_LMA) {
1926 hflags |= HF_LMA_MASK;
1927 }
1928
1929 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1930 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1931 } else {
1932 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1933 (DESC_B_SHIFT - HF_CS32_SHIFT);
1934 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1935 (DESC_B_SHIFT - HF_SS32_SHIFT);
1936 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1937 !(hflags & HF_CS32_MASK)) {
1938 hflags |= HF_ADDSEG_MASK;
1939 } else {
1940 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1941 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1942 }
1943 }
1944 env->hflags = hflags;
1945
1946 return 0;
1947 }
1948
1949 static int kvm_get_msrs(X86CPU *cpu)
1950 {
1951 CPUX86State *env = &cpu->env;
1952 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
1953 int ret, i, n;
1954
1955 kvm_msr_buf_reset(cpu);
1956
1957 n = 0;
1958 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1959 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1960 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1961 msrs[n++].index = MSR_PAT;
1962 if (has_msr_star) {
1963 msrs[n++].index = MSR_STAR;
1964 }
1965 if (has_msr_hsave_pa) {
1966 msrs[n++].index = MSR_VM_HSAVE_PA;
1967 }
1968 if (has_msr_tsc_aux) {
1969 msrs[n++].index = MSR_TSC_AUX;
1970 }
1971 if (has_msr_tsc_adjust) {
1972 msrs[n++].index = MSR_TSC_ADJUST;
1973 }
1974 if (has_msr_tsc_deadline) {
1975 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1976 }
1977 if (has_msr_misc_enable) {
1978 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1979 }
1980 if (has_msr_smbase) {
1981 msrs[n++].index = MSR_IA32_SMBASE;
1982 }
1983 if (has_msr_feature_control) {
1984 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1985 }
1986 if (has_msr_bndcfgs) {
1987 msrs[n++].index = MSR_IA32_BNDCFGS;
1988 }
1989 if (has_msr_xss) {
1990 msrs[n++].index = MSR_IA32_XSS;
1991 }
1992
1993
1994 if (!env->tsc_valid) {
1995 msrs[n++].index = MSR_IA32_TSC;
1996 env->tsc_valid = !runstate_is_running();
1997 }
1998
1999 #ifdef TARGET_X86_64
2000 if (lm_capable_kernel) {
2001 msrs[n++].index = MSR_CSTAR;
2002 msrs[n++].index = MSR_KERNELGSBASE;
2003 msrs[n++].index = MSR_FMASK;
2004 msrs[n++].index = MSR_LSTAR;
2005 }
2006 #endif
2007 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
2008 msrs[n++].index = MSR_KVM_WALL_CLOCK;
2009 if (has_msr_async_pf_en) {
2010 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
2011 }
2012 if (has_msr_pv_eoi_en) {
2013 msrs[n++].index = MSR_KVM_PV_EOI_EN;
2014 }
2015 if (has_msr_kvm_steal_time) {
2016 msrs[n++].index = MSR_KVM_STEAL_TIME;
2017 }
2018 if (has_msr_architectural_pmu) {
2019 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
2020 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
2021 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
2022 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
2023 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
2024 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
2025 }
2026 for (i = 0; i < num_architectural_pmu_counters; i++) {
2027 msrs[n++].index = MSR_P6_PERFCTR0 + i;
2028 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
2029 }
2030 }
2031
2032 if (env->mcg_cap) {
2033 msrs[n++].index = MSR_MCG_STATUS;
2034 msrs[n++].index = MSR_MCG_CTL;
2035 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2036 msrs[n++].index = MSR_MC0_CTL + i;
2037 }
2038 }
2039
2040 if (has_msr_hv_hypercall) {
2041 msrs[n++].index = HV_X64_MSR_HYPERCALL;
2042 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
2043 }
2044 if (has_msr_hv_vapic) {
2045 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
2046 }
2047 if (has_msr_hv_tsc) {
2048 msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
2049 }
2050 if (has_msr_hv_crash) {
2051 int j;
2052
2053 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
2054 msrs[n++].index = HV_X64_MSR_CRASH_P0 + j;
2055 }
2056 }
2057 if (has_msr_hv_runtime) {
2058 msrs[n++].index = HV_X64_MSR_VP_RUNTIME;
2059 }
2060 if (cpu->hyperv_synic) {
2061 uint32_t msr;
2062
2063 msrs[n++].index = HV_X64_MSR_SCONTROL;
2064 msrs[n++].index = HV_X64_MSR_SVERSION;
2065 msrs[n++].index = HV_X64_MSR_SIEFP;
2066 msrs[n++].index = HV_X64_MSR_SIMP;
2067 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2068 msrs[n++].index = msr;
2069 }
2070 }
2071 if (has_msr_hv_stimer) {
2072 uint32_t msr;
2073
2074 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2075 msr++) {
2076 msrs[n++].index = msr;
2077 }
2078 }
2079 if (has_msr_mtrr) {
2080 msrs[n++].index = MSR_MTRRdefType;
2081 msrs[n++].index = MSR_MTRRfix64K_00000;
2082 msrs[n++].index = MSR_MTRRfix16K_80000;
2083 msrs[n++].index = MSR_MTRRfix16K_A0000;
2084 msrs[n++].index = MSR_MTRRfix4K_C0000;
2085 msrs[n++].index = MSR_MTRRfix4K_C8000;
2086 msrs[n++].index = MSR_MTRRfix4K_D0000;
2087 msrs[n++].index = MSR_MTRRfix4K_D8000;
2088 msrs[n++].index = MSR_MTRRfix4K_E0000;
2089 msrs[n++].index = MSR_MTRRfix4K_E8000;
2090 msrs[n++].index = MSR_MTRRfix4K_F0000;
2091 msrs[n++].index = MSR_MTRRfix4K_F8000;
2092 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2093 msrs[n++].index = MSR_MTRRphysBase(i);
2094 msrs[n++].index = MSR_MTRRphysMask(i);
2095 }
2096 }
2097
2098 cpu->kvm_msr_buf->nmsrs = n;
2099
2100 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2101 if (ret < 0) {
2102 return ret;
2103 }
2104
2105 assert(ret == n);
2106 for (i = 0; i < ret; i++) {
2107 uint32_t index = msrs[i].index;
2108 switch (index) {
2109 case MSR_IA32_SYSENTER_CS:
2110 env->sysenter_cs = msrs[i].data;
2111 break;
2112 case MSR_IA32_SYSENTER_ESP:
2113 env->sysenter_esp = msrs[i].data;
2114 break;
2115 case MSR_IA32_SYSENTER_EIP:
2116 env->sysenter_eip = msrs[i].data;
2117 break;
2118 case MSR_PAT:
2119 env->pat = msrs[i].data;
2120 break;
2121 case MSR_STAR:
2122 env->star = msrs[i].data;
2123 break;
2124 #ifdef TARGET_X86_64
2125 case MSR_CSTAR:
2126 env->cstar = msrs[i].data;
2127 break;
2128 case MSR_KERNELGSBASE:
2129 env->kernelgsbase = msrs[i].data;
2130 break;
2131 case MSR_FMASK:
2132 env->fmask = msrs[i].data;
2133 break;
2134 case MSR_LSTAR:
2135 env->lstar = msrs[i].data;
2136 break;
2137 #endif
2138 case MSR_IA32_TSC:
2139 env->tsc = msrs[i].data;
2140 break;
2141 case MSR_TSC_AUX:
2142 env->tsc_aux = msrs[i].data;
2143 break;
2144 case MSR_TSC_ADJUST:
2145 env->tsc_adjust = msrs[i].data;
2146 break;
2147 case MSR_IA32_TSCDEADLINE:
2148 env->tsc_deadline = msrs[i].data;
2149 break;
2150 case MSR_VM_HSAVE_PA:
2151 env->vm_hsave = msrs[i].data;
2152 break;
2153 case MSR_KVM_SYSTEM_TIME:
2154 env->system_time_msr = msrs[i].data;
2155 break;
2156 case MSR_KVM_WALL_CLOCK:
2157 env->wall_clock_msr = msrs[i].data;
2158 break;
2159 case MSR_MCG_STATUS:
2160 env->mcg_status = msrs[i].data;
2161 break;
2162 case MSR_MCG_CTL:
2163 env->mcg_ctl = msrs[i].data;
2164 break;
2165 case MSR_IA32_MISC_ENABLE:
2166 env->msr_ia32_misc_enable = msrs[i].data;
2167 break;
2168 case MSR_IA32_SMBASE:
2169 env->smbase = msrs[i].data;
2170 break;
2171 case MSR_IA32_FEATURE_CONTROL:
2172 env->msr_ia32_feature_control = msrs[i].data;
2173 break;
2174 case MSR_IA32_BNDCFGS:
2175 env->msr_bndcfgs = msrs[i].data;
2176 break;
2177 case MSR_IA32_XSS:
2178 env->xss = msrs[i].data;
2179 break;
2180 default:
2181 if (msrs[i].index >= MSR_MC0_CTL &&
2182 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2183 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2184 }
2185 break;
2186 case MSR_KVM_ASYNC_PF_EN:
2187 env->async_pf_en_msr = msrs[i].data;
2188 break;
2189 case MSR_KVM_PV_EOI_EN:
2190 env->pv_eoi_en_msr = msrs[i].data;
2191 break;
2192 case MSR_KVM_STEAL_TIME:
2193 env->steal_time_msr = msrs[i].data;
2194 break;
2195 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2196 env->msr_fixed_ctr_ctrl = msrs[i].data;
2197 break;
2198 case MSR_CORE_PERF_GLOBAL_CTRL:
2199 env->msr_global_ctrl = msrs[i].data;
2200 break;
2201 case MSR_CORE_PERF_GLOBAL_STATUS:
2202 env->msr_global_status = msrs[i].data;
2203 break;
2204 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2205 env->msr_global_ovf_ctrl = msrs[i].data;
2206 break;
2207 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2208 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2209 break;
2210 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2211 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2212 break;
2213 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2214 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2215 break;
2216 case HV_X64_MSR_HYPERCALL:
2217 env->msr_hv_hypercall = msrs[i].data;
2218 break;
2219 case HV_X64_MSR_GUEST_OS_ID:
2220 env->msr_hv_guest_os_id = msrs[i].data;
2221 break;
2222 case HV_X64_MSR_APIC_ASSIST_PAGE:
2223 env->msr_hv_vapic = msrs[i].data;
2224 break;
2225 case HV_X64_MSR_REFERENCE_TSC:
2226 env->msr_hv_tsc = msrs[i].data;
2227 break;
2228 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2229 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2230 break;
2231 case HV_X64_MSR_VP_RUNTIME:
2232 env->msr_hv_runtime = msrs[i].data;
2233 break;
2234 case HV_X64_MSR_SCONTROL:
2235 env->msr_hv_synic_control = msrs[i].data;
2236 break;
2237 case HV_X64_MSR_SVERSION:
2238 env->msr_hv_synic_version = msrs[i].data;
2239 break;
2240 case HV_X64_MSR_SIEFP:
2241 env->msr_hv_synic_evt_page = msrs[i].data;
2242 break;
2243 case HV_X64_MSR_SIMP:
2244 env->msr_hv_synic_msg_page = msrs[i].data;
2245 break;
2246 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2247 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2248 break;
2249 case HV_X64_MSR_STIMER0_CONFIG:
2250 case HV_X64_MSR_STIMER1_CONFIG:
2251 case HV_X64_MSR_STIMER2_CONFIG:
2252 case HV_X64_MSR_STIMER3_CONFIG:
2253 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2254 msrs[i].data;
2255 break;
2256 case HV_X64_MSR_STIMER0_COUNT:
2257 case HV_X64_MSR_STIMER1_COUNT:
2258 case HV_X64_MSR_STIMER2_COUNT:
2259 case HV_X64_MSR_STIMER3_COUNT:
2260 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2261 msrs[i].data;
2262 break;
2263 case MSR_MTRRdefType:
2264 env->mtrr_deftype = msrs[i].data;
2265 break;
2266 case MSR_MTRRfix64K_00000:
2267 env->mtrr_fixed[0] = msrs[i].data;
2268 break;
2269 case MSR_MTRRfix16K_80000:
2270 env->mtrr_fixed[1] = msrs[i].data;
2271 break;
2272 case MSR_MTRRfix16K_A0000:
2273 env->mtrr_fixed[2] = msrs[i].data;
2274 break;
2275 case MSR_MTRRfix4K_C0000:
2276 env->mtrr_fixed[3] = msrs[i].data;
2277 break;
2278 case MSR_MTRRfix4K_C8000:
2279 env->mtrr_fixed[4] = msrs[i].data;
2280 break;
2281 case MSR_MTRRfix4K_D0000:
2282 env->mtrr_fixed[5] = msrs[i].data;
2283 break;
2284 case MSR_MTRRfix4K_D8000:
2285 env->mtrr_fixed[6] = msrs[i].data;
2286 break;
2287 case MSR_MTRRfix4K_E0000:
2288 env->mtrr_fixed[7] = msrs[i].data;
2289 break;
2290 case MSR_MTRRfix4K_E8000:
2291 env->mtrr_fixed[8] = msrs[i].data;
2292 break;
2293 case MSR_MTRRfix4K_F0000:
2294 env->mtrr_fixed[9] = msrs[i].data;
2295 break;
2296 case MSR_MTRRfix4K_F8000:
2297 env->mtrr_fixed[10] = msrs[i].data;
2298 break;
2299 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2300 if (index & 1) {
2301 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data;
2302 } else {
2303 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2304 }
2305 break;
2306 }
2307 }
2308
2309 return 0;
2310 }
2311
2312 static int kvm_put_mp_state(X86CPU *cpu)
2313 {
2314 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2315
2316 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2317 }
2318
2319 static int kvm_get_mp_state(X86CPU *cpu)
2320 {
2321 CPUState *cs = CPU(cpu);
2322 CPUX86State *env = &cpu->env;
2323 struct kvm_mp_state mp_state;
2324 int ret;
2325
2326 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2327 if (ret < 0) {
2328 return ret;
2329 }
2330 env->mp_state = mp_state.mp_state;
2331 if (kvm_irqchip_in_kernel()) {
2332 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2333 }
2334 return 0;
2335 }
2336
2337 static int kvm_get_apic(X86CPU *cpu)
2338 {
2339 DeviceState *apic = cpu->apic_state;
2340 struct kvm_lapic_state kapic;
2341 int ret;
2342
2343 if (apic && kvm_irqchip_in_kernel()) {
2344 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2345 if (ret < 0) {
2346 return ret;
2347 }
2348
2349 kvm_get_apic_state(apic, &kapic);
2350 }
2351 return 0;
2352 }
2353
2354 static int kvm_put_apic(X86CPU *cpu)
2355 {
2356 DeviceState *apic = cpu->apic_state;
2357 struct kvm_lapic_state kapic;
2358
2359 if (apic && kvm_irqchip_in_kernel()) {
2360 kvm_put_apic_state(apic, &kapic);
2361
2362 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
2363 }
2364 return 0;
2365 }
2366
2367 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2368 {
2369 CPUState *cs = CPU(cpu);
2370 CPUX86State *env = &cpu->env;
2371 struct kvm_vcpu_events events = {};
2372
2373 if (!kvm_has_vcpu_events()) {
2374 return 0;
2375 }
2376
2377 events.exception.injected = (env->exception_injected >= 0);
2378 events.exception.nr = env->exception_injected;
2379 events.exception.has_error_code = env->has_error_code;
2380 events.exception.error_code = env->error_code;
2381 events.exception.pad = 0;
2382
2383 events.interrupt.injected = (env->interrupt_injected >= 0);
2384 events.interrupt.nr = env->interrupt_injected;
2385 events.interrupt.soft = env->soft_interrupt;
2386
2387 events.nmi.injected = env->nmi_injected;
2388 events.nmi.pending = env->nmi_pending;
2389 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2390 events.nmi.pad = 0;
2391
2392 events.sipi_vector = env->sipi_vector;
2393
2394 if (has_msr_smbase) {
2395 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2396 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2397 if (kvm_irqchip_in_kernel()) {
2398 /* As soon as these are moved to the kernel, remove them
2399 * from cs->interrupt_request.
2400 */
2401 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2402 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2403 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2404 } else {
2405 /* Keep these in cs->interrupt_request. */
2406 events.smi.pending = 0;
2407 events.smi.latched_init = 0;
2408 }
2409 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2410 }
2411
2412 events.flags = 0;
2413 if (level >= KVM_PUT_RESET_STATE) {
2414 events.flags |=
2415 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2416 }
2417
2418 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2419 }
2420
2421 static int kvm_get_vcpu_events(X86CPU *cpu)
2422 {
2423 CPUX86State *env = &cpu->env;
2424 struct kvm_vcpu_events events;
2425 int ret;
2426
2427 if (!kvm_has_vcpu_events()) {
2428 return 0;
2429 }
2430
2431 memset(&events, 0, sizeof(events));
2432 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2433 if (ret < 0) {
2434 return ret;
2435 }
2436 env->exception_injected =
2437 events.exception.injected ? events.exception.nr : -1;
2438 env->has_error_code = events.exception.has_error_code;
2439 env->error_code = events.exception.error_code;
2440
2441 env->interrupt_injected =
2442 events.interrupt.injected ? events.interrupt.nr : -1;
2443 env->soft_interrupt = events.interrupt.soft;
2444
2445 env->nmi_injected = events.nmi.injected;
2446 env->nmi_pending = events.nmi.pending;
2447 if (events.nmi.masked) {
2448 env->hflags2 |= HF2_NMI_MASK;
2449 } else {
2450 env->hflags2 &= ~HF2_NMI_MASK;
2451 }
2452
2453 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2454 if (events.smi.smm) {
2455 env->hflags |= HF_SMM_MASK;
2456 } else {
2457 env->hflags &= ~HF_SMM_MASK;
2458 }
2459 if (events.smi.pending) {
2460 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2461 } else {
2462 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2463 }
2464 if (events.smi.smm_inside_nmi) {
2465 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2466 } else {
2467 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2468 }
2469 if (events.smi.latched_init) {
2470 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2471 } else {
2472 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2473 }
2474 }
2475
2476 env->sipi_vector = events.sipi_vector;
2477
2478 return 0;
2479 }
2480
2481 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2482 {
2483 CPUState *cs = CPU(cpu);
2484 CPUX86State *env = &cpu->env;
2485 int ret = 0;
2486 unsigned long reinject_trap = 0;
2487
2488 if (!kvm_has_vcpu_events()) {
2489 if (env->exception_injected == 1) {
2490 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2491 } else if (env->exception_injected == 3) {
2492 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2493 }
2494 env->exception_injected = -1;
2495 }
2496
2497 /*
2498 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2499 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2500 * by updating the debug state once again if single-stepping is on.
2501 * Another reason to call kvm_update_guest_debug here is a pending debug
2502 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2503 * reinject them via SET_GUEST_DEBUG.
2504 */
2505 if (reinject_trap ||
2506 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2507 ret = kvm_update_guest_debug(cs, reinject_trap);
2508 }
2509 return ret;
2510 }
2511
2512 static int kvm_put_debugregs(X86CPU *cpu)
2513 {
2514 CPUX86State *env = &cpu->env;
2515 struct kvm_debugregs dbgregs;
2516 int i;
2517
2518 if (!kvm_has_debugregs()) {
2519 return 0;
2520 }
2521
2522 for (i = 0; i < 4; i++) {
2523 dbgregs.db[i] = env->dr[i];
2524 }
2525 dbgregs.dr6 = env->dr[6];
2526 dbgregs.dr7 = env->dr[7];
2527 dbgregs.flags = 0;
2528
2529 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2530 }
2531
2532 static int kvm_get_debugregs(X86CPU *cpu)
2533 {
2534 CPUX86State *env = &cpu->env;
2535 struct kvm_debugregs dbgregs;
2536 int i, ret;
2537
2538 if (!kvm_has_debugregs()) {
2539 return 0;
2540 }
2541
2542 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2543 if (ret < 0) {
2544 return ret;
2545 }
2546 for (i = 0; i < 4; i++) {
2547 env->dr[i] = dbgregs.db[i];
2548 }
2549 env->dr[4] = env->dr[6] = dbgregs.dr6;
2550 env->dr[5] = env->dr[7] = dbgregs.dr7;
2551
2552 return 0;
2553 }
2554
2555 int kvm_arch_put_registers(CPUState *cpu, int level)
2556 {
2557 X86CPU *x86_cpu = X86_CPU(cpu);
2558 int ret;
2559
2560 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2561
2562 if (level >= KVM_PUT_RESET_STATE) {
2563 ret = kvm_put_msr_feature_control(x86_cpu);
2564 if (ret < 0) {
2565 return ret;
2566 }
2567 }
2568
2569 if (level == KVM_PUT_FULL_STATE) {
2570 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2571 * because TSC frequency mismatch shouldn't abort migration,
2572 * unless the user explicitly asked for a more strict TSC
2573 * setting (e.g. using an explicit "tsc-freq" option).
2574 */
2575 kvm_arch_set_tsc_khz(cpu);
2576 }
2577
2578 ret = kvm_getput_regs(x86_cpu, 1);
2579 if (ret < 0) {
2580 return ret;
2581 }
2582 ret = kvm_put_xsave(x86_cpu);
2583 if (ret < 0) {
2584 return ret;
2585 }
2586 ret = kvm_put_xcrs(x86_cpu);
2587 if (ret < 0) {
2588 return ret;
2589 }
2590 ret = kvm_put_sregs(x86_cpu);
2591 if (ret < 0) {
2592 return ret;
2593 }
2594 /* must be before kvm_put_msrs */
2595 ret = kvm_inject_mce_oldstyle(x86_cpu);
2596 if (ret < 0) {
2597 return ret;
2598 }
2599 ret = kvm_put_msrs(x86_cpu, level);
2600 if (ret < 0) {
2601 return ret;
2602 }
2603 if (level >= KVM_PUT_RESET_STATE) {
2604 ret = kvm_put_mp_state(x86_cpu);
2605 if (ret < 0) {
2606 return ret;
2607 }
2608 ret = kvm_put_apic(x86_cpu);
2609 if (ret < 0) {
2610 return ret;
2611 }
2612 }
2613
2614 ret = kvm_put_tscdeadline_msr(x86_cpu);
2615 if (ret < 0) {
2616 return ret;
2617 }
2618
2619 ret = kvm_put_vcpu_events(x86_cpu, level);
2620 if (ret < 0) {
2621 return ret;
2622 }
2623 ret = kvm_put_debugregs(x86_cpu);
2624 if (ret < 0) {
2625 return ret;
2626 }
2627 /* must be last */
2628 ret = kvm_guest_debug_workarounds(x86_cpu);
2629 if (ret < 0) {
2630 return ret;
2631 }
2632 return 0;
2633 }
2634
2635 int kvm_arch_get_registers(CPUState *cs)
2636 {
2637 X86CPU *cpu = X86_CPU(cs);
2638 int ret;
2639
2640 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2641
2642 ret = kvm_getput_regs(cpu, 0);
2643 if (ret < 0) {
2644 goto out;
2645 }
2646 ret = kvm_get_xsave(cpu);
2647 if (ret < 0) {
2648 goto out;
2649 }
2650 ret = kvm_get_xcrs(cpu);
2651 if (ret < 0) {
2652 goto out;
2653 }
2654 ret = kvm_get_sregs(cpu);
2655 if (ret < 0) {
2656 goto out;
2657 }
2658 ret = kvm_get_msrs(cpu);
2659 if (ret < 0) {
2660 goto out;
2661 }
2662 ret = kvm_get_mp_state(cpu);
2663 if (ret < 0) {
2664 goto out;
2665 }
2666 ret = kvm_get_apic(cpu);
2667 if (ret < 0) {
2668 goto out;
2669 }
2670 ret = kvm_get_vcpu_events(cpu);
2671 if (ret < 0) {
2672 goto out;
2673 }
2674 ret = kvm_get_debugregs(cpu);
2675 if (ret < 0) {
2676 goto out;
2677 }
2678 ret = 0;
2679 out:
2680 cpu_sync_bndcs_hflags(&cpu->env);
2681 return ret;
2682 }
2683
2684 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2685 {
2686 X86CPU *x86_cpu = X86_CPU(cpu);
2687 CPUX86State *env = &x86_cpu->env;
2688 int ret;
2689
2690 /* Inject NMI */
2691 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2692 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2693 qemu_mutex_lock_iothread();
2694 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2695 qemu_mutex_unlock_iothread();
2696 DPRINTF("injected NMI\n");
2697 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2698 if (ret < 0) {
2699 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2700 strerror(-ret));
2701 }
2702 }
2703 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2704 qemu_mutex_lock_iothread();
2705 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2706 qemu_mutex_unlock_iothread();
2707 DPRINTF("injected SMI\n");
2708 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2709 if (ret < 0) {
2710 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2711 strerror(-ret));
2712 }
2713 }
2714 }
2715
2716 if (!kvm_pic_in_kernel()) {
2717 qemu_mutex_lock_iothread();
2718 }
2719
2720 /* Force the VCPU out of its inner loop to process any INIT requests
2721 * or (for userspace APIC, but it is cheap to combine the checks here)
2722 * pending TPR access reports.
2723 */
2724 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2725 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2726 !(env->hflags & HF_SMM_MASK)) {
2727 cpu->exit_request = 1;
2728 }
2729 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2730 cpu->exit_request = 1;
2731 }
2732 }
2733
2734 if (!kvm_pic_in_kernel()) {
2735 /* Try to inject an interrupt if the guest can accept it */
2736 if (run->ready_for_interrupt_injection &&
2737 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2738 (env->eflags & IF_MASK)) {
2739 int irq;
2740
2741 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2742 irq = cpu_get_pic_interrupt(env);
2743 if (irq >= 0) {
2744 struct kvm_interrupt intr;
2745
2746 intr.irq = irq;
2747 DPRINTF("injected interrupt %d\n", irq);
2748 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2749 if (ret < 0) {
2750 fprintf(stderr,
2751 "KVM: injection failed, interrupt lost (%s)\n",
2752 strerror(-ret));
2753 }
2754 }
2755 }
2756
2757 /* If we have an interrupt but the guest is not ready to receive an
2758 * interrupt, request an interrupt window exit. This will
2759 * cause a return to userspace as soon as the guest is ready to
2760 * receive interrupts. */
2761 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2762 run->request_interrupt_window = 1;
2763 } else {
2764 run->request_interrupt_window = 0;
2765 }
2766
2767 DPRINTF("setting tpr\n");
2768 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2769
2770 qemu_mutex_unlock_iothread();
2771 }
2772 }
2773
2774 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2775 {
2776 X86CPU *x86_cpu = X86_CPU(cpu);
2777 CPUX86State *env = &x86_cpu->env;
2778
2779 if (run->flags & KVM_RUN_X86_SMM) {
2780 env->hflags |= HF_SMM_MASK;
2781 } else {
2782 env->hflags &= HF_SMM_MASK;
2783 }
2784 if (run->if_flag) {
2785 env->eflags |= IF_MASK;
2786 } else {
2787 env->eflags &= ~IF_MASK;
2788 }
2789
2790 /* We need to protect the apic state against concurrent accesses from
2791 * different threads in case the userspace irqchip is used. */
2792 if (!kvm_irqchip_in_kernel()) {
2793 qemu_mutex_lock_iothread();
2794 }
2795 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2796 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2797 if (!kvm_irqchip_in_kernel()) {
2798 qemu_mutex_unlock_iothread();
2799 }
2800 return cpu_get_mem_attrs(env);
2801 }
2802
2803 int kvm_arch_process_async_events(CPUState *cs)
2804 {
2805 X86CPU *cpu = X86_CPU(cs);
2806 CPUX86State *env = &cpu->env;
2807
2808 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2809 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2810 assert(env->mcg_cap);
2811
2812 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2813
2814 kvm_cpu_synchronize_state(cs);
2815
2816 if (env->exception_injected == EXCP08_DBLE) {
2817 /* this means triple fault */
2818 qemu_system_reset_request();
2819 cs->exit_request = 1;
2820 return 0;
2821 }
2822 env->exception_injected = EXCP12_MCHK;
2823 env->has_error_code = 0;
2824
2825 cs->halted = 0;
2826 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2827 env->mp_state = KVM_MP_STATE_RUNNABLE;
2828 }
2829 }
2830
2831 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2832 !(env->hflags & HF_SMM_MASK)) {
2833 kvm_cpu_synchronize_state(cs);
2834 do_cpu_init(cpu);
2835 }
2836
2837 if (kvm_irqchip_in_kernel()) {
2838 return 0;
2839 }
2840
2841 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2842 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2843 apic_poll_irq(cpu->apic_state);
2844 }
2845 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2846 (env->eflags & IF_MASK)) ||
2847 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2848 cs->halted = 0;
2849 }
2850 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2851 kvm_cpu_synchronize_state(cs);
2852 do_cpu_sipi(cpu);
2853 }
2854 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2855 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2856 kvm_cpu_synchronize_state(cs);
2857 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2858 env->tpr_access_type);
2859 }
2860
2861 return cs->halted;
2862 }
2863
2864 static int kvm_handle_halt(X86CPU *cpu)
2865 {
2866 CPUState *cs = CPU(cpu);
2867 CPUX86State *env = &cpu->env;
2868
2869 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2870 (env->eflags & IF_MASK)) &&
2871 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2872 cs->halted = 1;
2873 return EXCP_HLT;
2874 }
2875
2876 return 0;
2877 }
2878
2879 static int kvm_handle_tpr_access(X86CPU *cpu)
2880 {
2881 CPUState *cs = CPU(cpu);
2882 struct kvm_run *run = cs->kvm_run;
2883
2884 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2885 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2886 : TPR_ACCESS_READ);
2887 return 1;
2888 }
2889
2890 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2891 {
2892 static const uint8_t int3 = 0xcc;
2893
2894 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2895 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2896 return -EINVAL;
2897 }
2898 return 0;
2899 }
2900
2901 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2902 {
2903 uint8_t int3;
2904
2905 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2906 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2907 return -EINVAL;
2908 }
2909 return 0;
2910 }
2911
2912 static struct {
2913 target_ulong addr;
2914 int len;
2915 int type;
2916 } hw_breakpoint[4];
2917
2918 static int nb_hw_breakpoint;
2919
2920 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2921 {
2922 int n;
2923
2924 for (n = 0; n < nb_hw_breakpoint; n++) {
2925 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2926 (hw_breakpoint[n].len == len || len == -1)) {
2927 return n;
2928 }
2929 }
2930 return -1;
2931 }
2932
2933 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2934 target_ulong len, int type)
2935 {
2936 switch (type) {
2937 case GDB_BREAKPOINT_HW:
2938 len = 1;
2939 break;
2940 case GDB_WATCHPOINT_WRITE:
2941 case GDB_WATCHPOINT_ACCESS:
2942 switch (len) {
2943 case 1:
2944 break;
2945 case 2:
2946 case 4:
2947 case 8:
2948 if (addr & (len - 1)) {
2949 return -EINVAL;
2950 }
2951 break;
2952 default:
2953 return -EINVAL;
2954 }
2955 break;
2956 default:
2957 return -ENOSYS;
2958 }
2959
2960 if (nb_hw_breakpoint == 4) {
2961 return -ENOBUFS;
2962 }
2963 if (find_hw_breakpoint(addr, len, type) >= 0) {
2964 return -EEXIST;
2965 }
2966 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2967 hw_breakpoint[nb_hw_breakpoint].len = len;
2968 hw_breakpoint[nb_hw_breakpoint].type = type;
2969 nb_hw_breakpoint++;
2970
2971 return 0;
2972 }
2973
2974 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2975 target_ulong len, int type)
2976 {
2977 int n;
2978
2979 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2980 if (n < 0) {
2981 return -ENOENT;
2982 }
2983 nb_hw_breakpoint--;
2984 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2985
2986 return 0;
2987 }
2988
2989 void kvm_arch_remove_all_hw_breakpoints(void)
2990 {
2991 nb_hw_breakpoint = 0;
2992 }
2993
2994 static CPUWatchpoint hw_watchpoint;
2995
2996 static int kvm_handle_debug(X86CPU *cpu,
2997 struct kvm_debug_exit_arch *arch_info)
2998 {
2999 CPUState *cs = CPU(cpu);
3000 CPUX86State *env = &cpu->env;
3001 int ret = 0;
3002 int n;
3003
3004 if (arch_info->exception == 1) {
3005 if (arch_info->dr6 & (1 << 14)) {
3006 if (cs->singlestep_enabled) {
3007 ret = EXCP_DEBUG;
3008 }
3009 } else {
3010 for (n = 0; n < 4; n++) {
3011 if (arch_info->dr6 & (1 << n)) {
3012 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3013 case 0x0:
3014 ret = EXCP_DEBUG;
3015 break;
3016 case 0x1:
3017 ret = EXCP_DEBUG;
3018 cs->watchpoint_hit = &hw_watchpoint;
3019 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3020 hw_watchpoint.flags = BP_MEM_WRITE;
3021 break;
3022 case 0x3:
3023 ret = EXCP_DEBUG;
3024 cs->watchpoint_hit = &hw_watchpoint;
3025 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3026 hw_watchpoint.flags = BP_MEM_ACCESS;
3027 break;
3028 }
3029 }
3030 }
3031 }
3032 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3033 ret = EXCP_DEBUG;
3034 }
3035 if (ret == 0) {
3036 cpu_synchronize_state(cs);
3037 assert(env->exception_injected == -1);
3038
3039 /* pass to guest */
3040 env->exception_injected = arch_info->exception;
3041 env->has_error_code = 0;
3042 }
3043
3044 return ret;
3045 }
3046
3047 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3048 {
3049 const uint8_t type_code[] = {
3050 [GDB_BREAKPOINT_HW] = 0x0,
3051 [GDB_WATCHPOINT_WRITE] = 0x1,
3052 [GDB_WATCHPOINT_ACCESS] = 0x3
3053 };
3054 const uint8_t len_code[] = {
3055 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3056 };
3057 int n;
3058
3059 if (kvm_sw_breakpoints_active(cpu)) {
3060 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3061 }
3062 if (nb_hw_breakpoint > 0) {
3063 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3064 dbg->arch.debugreg[7] = 0x0600;
3065 for (n = 0; n < nb_hw_breakpoint; n++) {
3066 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3067 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3068 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3069 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3070 }
3071 }
3072 }
3073
3074 static bool host_supports_vmx(void)
3075 {
3076 uint32_t ecx, unused;
3077
3078 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3079 return ecx & CPUID_EXT_VMX;
3080 }
3081
3082 #define VMX_INVALID_GUEST_STATE 0x80000021
3083
3084 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3085 {
3086 X86CPU *cpu = X86_CPU(cs);
3087 uint64_t code;
3088 int ret;
3089
3090 switch (run->exit_reason) {
3091 case KVM_EXIT_HLT:
3092 DPRINTF("handle_hlt\n");
3093 qemu_mutex_lock_iothread();
3094 ret = kvm_handle_halt(cpu);
3095 qemu_mutex_unlock_iothread();
3096 break;
3097 case KVM_EXIT_SET_TPR:
3098 ret = 0;
3099 break;
3100 case KVM_EXIT_TPR_ACCESS:
3101 qemu_mutex_lock_iothread();
3102 ret = kvm_handle_tpr_access(cpu);
3103 qemu_mutex_unlock_iothread();
3104 break;
3105 case KVM_EXIT_FAIL_ENTRY:
3106 code = run->fail_entry.hardware_entry_failure_reason;
3107 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3108 code);
3109 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3110 fprintf(stderr,
3111 "\nIf you're running a guest on an Intel machine without "
3112 "unrestricted mode\n"
3113 "support, the failure can be most likely due to the guest "
3114 "entering an invalid\n"
3115 "state for Intel VT. For example, the guest maybe running "
3116 "in big real mode\n"
3117 "which is not supported on less recent Intel processors."
3118 "\n\n");
3119 }
3120 ret = -1;
3121 break;
3122 case KVM_EXIT_EXCEPTION:
3123 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3124 run->ex.exception, run->ex.error_code);
3125 ret = -1;
3126 break;
3127 case KVM_EXIT_DEBUG:
3128 DPRINTF("kvm_exit_debug\n");
3129 qemu_mutex_lock_iothread();
3130 ret = kvm_handle_debug(cpu, &run->debug.arch);
3131 qemu_mutex_unlock_iothread();
3132 break;
3133 case KVM_EXIT_HYPERV:
3134 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3135 break;
3136 case KVM_EXIT_IOAPIC_EOI:
3137 ioapic_eoi_broadcast(run->eoi.vector);
3138 ret = 0;
3139 break;
3140 default:
3141 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3142 ret = -1;
3143 break;
3144 }
3145
3146 return ret;
3147 }
3148
3149 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3150 {
3151 X86CPU *cpu = X86_CPU(cs);
3152 CPUX86State *env = &cpu->env;
3153
3154 kvm_cpu_synchronize_state(cs);
3155 return !(env->cr[0] & CR0_PE_MASK) ||
3156 ((env->segs[R_CS].selector & 3) != 3);
3157 }
3158
3159 void kvm_arch_init_irq_routing(KVMState *s)
3160 {
3161 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3162 /* If kernel can't do irq routing, interrupt source
3163 * override 0->2 cannot be set up as required by HPET.
3164 * So we have to disable it.
3165 */
3166 no_hpet = 1;
3167 }
3168 /* We know at this point that we're using the in-kernel
3169 * irqchip, so we can use irqfds, and on x86 we know
3170 * we can use msi via irqfd and GSI routing.
3171 */
3172 kvm_msi_via_irqfd_allowed = true;
3173 kvm_gsi_routing_allowed = true;
3174
3175 if (kvm_irqchip_is_split()) {
3176 int i;
3177
3178 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3179 MSI routes for signaling interrupts to the local apics. */
3180 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3181 struct MSIMessage msg = { 0x0, 0x0 };
3182 if (kvm_irqchip_add_msi_route(s, msg, NULL) < 0) {
3183 error_report("Could not enable split IRQ mode.");
3184 exit(1);
3185 }
3186 }
3187 }
3188 }
3189
3190 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3191 {
3192 int ret;
3193 if (machine_kernel_irqchip_split(ms)) {
3194 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3195 if (ret) {
3196 error_report("Could not enable split irqchip mode: %s\n",
3197 strerror(-ret));
3198 exit(1);
3199 } else {
3200 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3201 kvm_split_irqchip = true;
3202 return 1;
3203 }
3204 } else {
3205 return 0;
3206 }
3207 }
3208
3209 /* Classic KVM device assignment interface. Will remain x86 only. */
3210 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3211 uint32_t flags, uint32_t *dev_id)
3212 {
3213 struct kvm_assigned_pci_dev dev_data = {
3214 .segnr = dev_addr->domain,
3215 .busnr = dev_addr->bus,
3216 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3217 .flags = flags,
3218 };
3219 int ret;
3220
3221 dev_data.assigned_dev_id =
3222 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3223
3224 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3225 if (ret < 0) {
3226 return ret;
3227 }
3228
3229 *dev_id = dev_data.assigned_dev_id;
3230
3231 return 0;
3232 }
3233
3234 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3235 {
3236 struct kvm_assigned_pci_dev dev_data = {
3237 .assigned_dev_id = dev_id,
3238 };
3239
3240 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3241 }
3242
3243 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3244 uint32_t irq_type, uint32_t guest_irq)
3245 {
3246 struct kvm_assigned_irq assigned_irq = {
3247 .assigned_dev_id = dev_id,
3248 .guest_irq = guest_irq,
3249 .flags = irq_type,
3250 };
3251
3252 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3253 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3254 } else {
3255 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3256 }
3257 }
3258
3259 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3260 uint32_t guest_irq)
3261 {
3262 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3263 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3264
3265 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3266 }
3267
3268 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3269 {
3270 struct kvm_assigned_pci_dev dev_data = {
3271 .assigned_dev_id = dev_id,
3272 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3273 };
3274
3275 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3276 }
3277
3278 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3279 uint32_t type)
3280 {
3281 struct kvm_assigned_irq assigned_irq = {
3282 .assigned_dev_id = dev_id,
3283 .flags = type,
3284 };
3285
3286 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3287 }
3288
3289 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3290 {
3291 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3292 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3293 }
3294
3295 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3296 {
3297 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3298 KVM_DEV_IRQ_GUEST_MSI, virq);
3299 }
3300
3301 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3302 {
3303 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3304 KVM_DEV_IRQ_HOST_MSI);
3305 }
3306
3307 bool kvm_device_msix_supported(KVMState *s)
3308 {
3309 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3310 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3311 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3312 }
3313
3314 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3315 uint32_t nr_vectors)
3316 {
3317 struct kvm_assigned_msix_nr msix_nr = {
3318 .assigned_dev_id = dev_id,
3319 .entry_nr = nr_vectors,
3320 };
3321
3322 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3323 }
3324
3325 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3326 int virq)
3327 {
3328 struct kvm_assigned_msix_entry msix_entry = {
3329 .assigned_dev_id = dev_id,
3330 .gsi = virq,
3331 .entry = vector,
3332 };
3333
3334 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3335 }
3336
3337 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3338 {
3339 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3340 KVM_DEV_IRQ_GUEST_MSIX, 0);
3341 }
3342
3343 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3344 {
3345 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3346 KVM_DEV_IRQ_HOST_MSIX);
3347 }
3348
3349 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3350 uint64_t address, uint32_t data, PCIDevice *dev)
3351 {
3352 return 0;
3353 }
3354
3355 int kvm_arch_msi_data_to_gsi(uint32_t data)
3356 {
3357 abort();
3358 }
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